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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
1
Trends In Materials: The
Smartphone DriverSmartphone ICs Driving Technology to 3-
D Stacked Devices/Chips, 3-D FinFET
Transistors and High Mobility Channel
Material From 20/22nm Production to
5/7nm Exploratory ResearchJohn Ogawa Borland
J.O.B. Technologies
Aiea, Hawaii
www.job-technologies.com
April 30, 2015
-
Outline Introduction: Smartphone as new technology driver
2012: iPhone 5 uses Sonys 3-D stacked backside CMOS image sensor camera
2015: 1) Samsung Galaxy S6 and Apple iPhone 6s A9 application processors
switches to 14/16nm 3-D FinFET. 2) Samsung Galaxy S6 introduces 3-D ePoP
(embedded package on package)
22/20nm Node: Smartphone Application Processor 2014-2015
using 3-D bulk-FinFET from Intel (China low end smartphones),
2-D planar by TSMC and Samsung (A8-iPhone6 & Galaxy-S5)
14/16nm Node: Smartphone Application Processor 2015-2016
3-D bulk-FinFET 1st generation by TSMC & Samsung (Galaxy-
S6 and A9-iPhone6s), 2nd generation by Intel
10/7nm Node: High mobility material SiGe or Ge Fin channel
Formation
Exploratory Research 5nm Node: High mobility material
Nano-wire channel formation
Dopant Activation and Junction Leakage in Ge and SiGe
Summary2
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
3
2014 total smartphone sales were 1.24B units.
Q4/14=367.5B smartphones
Q1/15=71.7B PC/tablets
2014=$336B
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
4
-
USA Today March
4, 2015
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
5
2014 total=1.24B smartphones
#1 Samsung=26% (307M units)
#2 Apple=15% (191M units)
i4s i5 i5s&5c i6
S3 S4 S5 S6
Company 4Q14
Units
4Q14 Market
Share (%)
Apple 74,832 20.4
Samsung 73,032 19.9
Lenovo* 24,300 6.6
Huawei 21,038 5.7
Xiaomi 18,582 5.1
Others 155,701.6 42.4
Total 367,484.5 100.0
Gartner, March 6, 2015
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2014: 1.87B Total Mobile Phones (Smartphones + standard cell phones)
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
6
Company 2014
1000x Units
2014 Market
Share (%)
2013
1000x Units
2013 Market Share
(%)
Samsung 392,546 20.9 444,472 24.6
Apple 191,426 10.2 150,786 8.3
Microsoft 185,660 9.9 250,835 13.9
Lenovo* 84,029 4.5 66,463 3.7
LG Electronics 76,096 4.0 69,094 3.8
Huawei 70,499 3.8 53,296 2.9
TCL Communication 64,026 3.4 49,538 2.7
Xiaomi 56,529 3.0 13,423 0.7
ZTE 53,910 2.9 59,903 3.3
Sony 37,791 2.0 37,596 2.1
Micromax 37,094 2.0 25,431 1.4
Others 629,360 33.5 587,764 32.5
Total 1,878,968 100.0 1,808,600 100.0
Company 2014
1000x Units
2014 Market
Share (%)
2013
1000x Units
2013 Market
Share (%)
Samsung 307,597 24.7 299,795 30.9
Apple 191,426 15.4 150,786 15.5
Lenovo* 81,416 6.5 57,424 5.9
Huawei 68,081 5.5 46,609 4.8
LG Electronics 57,661 4.6 46,432 4.8
Others 538,710 43.3 368,675 38.0
Total 1,244,890 100.0 969,721 100.0
Gartner, March 6, 2015
Cell-P
85M
0M
3M
2M
19M
634M
Smartphones Cell-P145M
0M
839M
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
7
2005 2007 2009 2012 2014
Jan 16, 2013 Intel announced at Consumer
Electronics Show new Atom platform for
rapidly growing low-end smartphone market
in China!
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
8
& msec Flash
SF-stressor
Intel, Sept. 6, 2011
Altera to use Intel 14nm Foundry reported by EETimes Feb 26, 2013: The Mobile Foundry will ramp
to billions of IC chip units across many suppliers while the PC chip TAM is only 400M units so mobile
chip market potential to be 10x larger in size than PC and Intel wants to get part of this to continue their
growth which was -1% in 2012! (Q1/2015 smartphone AP= >5x PC!)
A5 A6 A7 A8 A9
45nm 32nm 28nm 20nm 14/16nm
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
9
9/9/14: Apple announces A8 SOC for iPhone 6 & 6+:
ApplesA8 is their first SoC built on 20nm node technology with 2B
transistors and is 13% smaller than the A7 for 25% faster CPU than the A7. Compared
to iPhone 1, iPhone 6 CPU performance is 50x as shown in the slide photo below left
and table below.
iPhone 5 uses A7: 28nm node technology from Samsung/foundry
iPhone 6 uses A8: 20nm node technology from TSMC
Next iPhone Sept 2015 will use A9: 14nm node FinFET from Samsung
& 16nm FF+ from TSMC
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
10Wakabayashi
3-D stacked devices
-CMOS image sensor
-Flash
-DRAM
Low leakage
3-D FinFET
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J.O.B. Technologies (Strategic
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11
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J.O.B.Technologies
(StrategicMarketing,Sales&Te
chnology)
12
No Micro-Lensing for
Backside Illumination
Infrared Filter
Color Filter Optional
Transparent Electrode (ITO)
Buried Photodiode
Quartz
Poly
n+n+Silicon
(Thin or Thick)
Oxide
n+
Poly
Contact
Light Shield
(Opaque)
3-D
Buried Photodiode
(Silicon on Glass)
Borland & Tokoro, Nov 2004, Asia Pacific,
Solid State Technology, p. S18
Sony Front-Side versus Back-
Side Illumination Patent
Application US 2003/0025160A1
-
Jan & July 2012
J.O.B. Technology (Strategic
Marketing, Sales &
Technology)
13
-
DRAM 3-D Capacitor Cell
J.O.B. Technology (Strategic
Marketing, Sales &
Technology)
14
1987 IBM 4Mb DRAM Trench Capacitor Cell:
1st high volume production use of CMP for
planarization of poly trench fill and selective
silicon for local strap/interconnect.
1999 Samsung DRAM HSG-
poly-Si Stack Capacitor Cell
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
15
DRAM 3-D Memory Array Transistor
-
J.O.B. Technologies (Strategic
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16
IBM 32nm 3-D Stacked
DRAM-Die + Logic-Die
in 1 Package with TSV
(through-silicon-via)
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
17
IEDM-2014 Paper 3.8 by Lin of IBM/EFK not Alliance on High Performance 14nm
SOI FinFET CMOS Technology with 0.0174um2 embedded DRAM and 15 Levels of
Cu Metallization.
eSiGe
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
18
Bez, ST, IEDM-2011 short course
2015
256Gb
128Gb
$0.50
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
19
3-D NAND Flash market delayed was reported Feb 19, 2015 in Semiconductor Engineering:
Only Samsung in production with 3-D NAND Flash since 2013. Micron/Intel will start
production 2nd half of 2015 and SK Hynix plans pilot production later in 2015. SanDisk/Toshiba
3-D NAND not until 2016 and Spansion/XMC not until 2017. Today Samsung has 128Gb Flash
using 16nm node technology and can achieve same die area at 128Gb with 32-layer 3-D NAND
based on 40nm technology node but to compete price per bit with 3-D NAND requires >48-
layers! 128Gb Flash memory stick $64 at Best Buy (50/Gb). Below is Samsungs 32-layer 3-D
NAND chip reported by Chipworks Aug 2014.
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
20
Samsung mass producing high-density ePoP memory for
SmartphonesSamsung on Feb10, 2015 announced that they will be mass producing the extremely
thin ePoP (embedded package on package) memory, a single memory package
consisting of 3GB LPDDR3 DRAM, 32GB eMMC and a controller for use in high-end
smartphones. Replacing that set-up with a Samsung ePoP reportedly decreases the total
area used by approx. 40%. Samsung is basically stacking all the memory, both RAM
and NAND, on a single ePoP module thats then positioned on top of the processor,
rather than beside it as shown below. It is rumored to be speced in the Galaxy S6 and
other top mobile devices later this year.Solid State Technology reported Feb 10, 2015
Samsung Galaxy S6 to be introduced on April 10, 2015
-
Outline Introduction: Smartphone as new technology driver
2012: iPhone 5 uses Sonys 3-D stacked backside CMOS image sensor camera
2015: 1) Samsung Galaxy S6 and Apple iPhone 6s A9 application processors
switches to 14/16nm 3-D FinFET. 2) Samsung Galaxy S6 introduces 3-D ePoP
(embedded package on package)
22/20nm Node: Smartphone Application Processor 2014-2015
using 3-D bulk-FinFET from Intel (China low end smartphones),
2-D planar by TSMC and Samsung (A8-iPhone6 & Galaxy-S5)
14/16nm Node: Smartphone Application Processor 2015-2016
3-D bulk-FinFET 1st generation by TSMC & Samsung (Galaxy-
S6 and A9-iPhone6s), 2nd generation by Intel
10/7nm Node: High mobility material SiGe or Ge Fin channel
Formation
Exploratory Research 5nm Node: High mobility material
Nano-wire channel formation
Dopant Activation and Junction Leakage in Ge and SiGe
Summary21
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22
Borland disagree, I say amorphous
implant EOR defects not n+ SEGDick James, X-TEM, Chipworks, April, 2012
Intel 22-nm nMOS Epi or Not? To understand Intels 22nm FinFET process details you must know what they did for 32nm planar!
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Intel IEDM-2012 paper 3.1 on 22nm Tri-gate
SoC Technology
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
23
Like for 32nm planar production in 2009!
-pMOS: SDE-implant, S/D recess etch then eSiGe
-nMOS: SDE-implant, S/D -implant with amorphous-P+Carbon+ Stacking Fault stressor and
raised S/D epi
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
24
Looks like 45nm eSiGe Looks like 65nm eSiGe
?
Defect layer?
Intel-SoC, IEDM-2011 & 2012
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
25
Prof. Ogura, Meiji Univ. July -2012
Intel 32nm PC Chip
Below
detection
Below
detection
As n+SDE
below
detection
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Chipworks Teardown of Intel
22nm pMOS FinFET
26
Dick James, Chipworks, Semicon/West 2013 WCJUG meeting
32nm
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J.O.B. Technology (Strategic
Marketing, Sales &
Technology)
27
Mobility IDRelax-Si 1 1
Strain-Si 10x 1.8x
Relax-Ge 4x 2x
Strain-Ge 25x 2.5x
90nm 65nm 45nm 32nm 22nm
14nm
Kirshnamohan et al., Stanford Univ. ,
VLSI Sym 2006, section 18.1
S. Thompson, U of F, VLSI Sym 2006 short course
Ge-channel
Next?
17% 22% 30% 40% 55%
Kuhn, Intel,, ECS Oct 2010
Maxed out need Ge!
-
Chipworks Teardown of Intel
22nm nMOS FinFET
28
Phos-implant?
Phos doped Epi S/D has no recess etch!
Amorphous S/D stressor implant
Dick James, Chipworks, Semicon/West 2013 WCJUG meeting
Need to look for As also!
32nm
32nm
Ogura, Meiji Univ.
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
29
But Pss~1.8E21/cm3 so this
must be chemical and not
electrical!
-
IIT-2014 nFinFET Doping Paper by Intel
4/27/2015 30
Pipes et al., Intel, IIT-2014, p. 37
Dick James, Chipworks
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
31
Nagayama, Nissin, IWJT-2010 paper 3.4
Box-like profile for P
when C dose increases
between 1-2E15/cm2
Pss=1.5E20/cm3
2.3nm/decade
5.8nm/decade
15.1nm/decade
32nm
22nmDick James, Chipworks
Ogura, Meiji Univ.
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J.O.B. Technologies (Strategic
Marketing, Sales &
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32
Borland et al., JOB/Nissin/Applied/KT/EAG/Toshiba, IEEE-RTP-2009
Amorphous implant boosts C-stressor by 50%!
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J.O.B. Technologies (Strategic
Marketing, Sales &
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33
Arsenic-SDE and Phos-S/D causes amorphization of
Fin so SPE forms Carbon+Stacking Fault Stressor
Dick James, Chipworks, Semicon/West 2014 discussions
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
34
My Sony contact in July 2012
said 8 degree Fin slope for (551)
plane reported by Tokoku Univ
in 6/2007!
Ohmi, Tokoku Univ, SSDM-2013
-
FinFET Doping Options3-D FinFET require some form of S/D extension doping under the side wall
spacer for gate overlap control. Two basic method of doping are either:
Direct junction doping by implantation with or without diffusion using:
1)Beam-line high tilt implantation for electrical conformal doping using amorphous
SPE dopant activation (JOB Tech Insight-2009 and Intel doing for 22nm FinFET)
2)Plasma implantation for chemical conformal doping (IMEC and others reported
not really conformal)
3)Plasma deposition followed by tilted beamline knock-in doping (SEN SSDM-10)
Deposited doped layer requiring lateral dopant diffusion using:
1)Plasma deposition doping and diffusion (IMEC reported, limited by dopant solid
solubility)
2)Doped epi deposition and diffusion (IBM reported, limited by dopant solid
solubility)
3)Monolayer deposition and diffusion (Sematech/CNSE reported, poor dopant
solid solubility limited)
Hydrogen surface passivation for highest retained dose and controlled amorphous
junction depth
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J.O.B. Technologies (Strategic
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36
Single & Multi-FINFET Double-Gate Devices
Y.K. Choi et al, IEDM-2001
Plasma Doping for Multi-FIN Gate/Poly
High Tilt Implant For LG-SS/D
Asymmetric n+/p+ Poly/Gate
Borland, Moroz, Iwai, Maszara & Wang, Varian/Synopsys/TIT/AMD/TSMC,
Solid State Technology, June 2003
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J.O.B. Technologies (Strategic
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Technology)
37
Intel IIT-2014: Very good conformal Fin doping with 45
degree tilted As-implantation.
Applied IIIT-2014: Poor 10x worse conformal Fin
doping with plasma!
IWJT-2011 paper S8-2 by
Vandervorst of IMEC
showing very good
conformal carrier
concentration
IWJT-2011 paper S2-1 by
Sue Felch of IBS severe
loss of plasma dopant after
annealing!
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
38
SEN, SSDM-2010
-
J.O.B. Technologies (Strategic
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39
Kennel, Intel, IEEE/RTP 2006
Boron activation limited
by low Bss (Boron solid
solubility) and not by
implanted dose
With SPE Non-Equilibrium
Activation of Boron >>Bss
But Requires Amorphization!
5.7E20/cm3
Any deposition doping requires lateral
diffusion which will be limited by dopant
solid solubility activation unless amorphous
SPE or LPE as shown by Intel.
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
40
High Tilt p+ & n+ Molecular
Implantation For 3-D Structures:
Retained Chemical Dose Versus
Electrical Activation Limited
Conformal DopingJohn Ogawa Borland
J.O.B. Technologies, Aiea, Hawaii
&
Masayasu Tanjyo, Tsutomu Nagayama and Nariaki Hamamoto
Nissin Ion Equipment, Kyoto, Japan
INSIGHTS 2009
April 28, 2009
Especially with
msec Annealing
-
J.O.B. Technologies (Strategic
Marketing, Sales &
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41
B Needs PAI or MSA >1300C!
-
J.O.B. Technologies (Strategic
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Technology)
42
IWJT-2011 paper
S8-2 by IMEC
-
Duffy et al., INSIGHTS May 2007
Tri-Gate Aspect Ratio
1 to 1 so 45 to 63.5
degree tilt is OKThinner
Photoresist
Dummy Fin
Bulk FinFET
Oxide &
Not BOX Silicon!
-
Influence of Surface Passivation on B,
B18H22 and B36H44 Retained Dose for USJ
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
44
My IWJT-2011 S7-3 paper. My message was that for Tri-Gate with a 1
to 1 aspect ratio a dual mode 63.5 degree tilt implant for the Fin will
give you equal 100% chemical conformality on the top and side wall of
the Tri-gate Fin especially when you use hydrogen surface passivation
compared to oxide surface passivation at high tilt angles and/or low
energies. (NOT AN ISSUE WITH ROUNDED FIN-TOP)
Flat Fin-Top Round Fin-Top
-
PCOR-SIMS Analysis Of Surface Oxide &
Retained Dose
45
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 10 20 30 40 50 60 70 80 90 100
Implant Retained Dose %
Su
rfac
e P
assi
vat
ion
Ox
ide
Th
ick
nes
s (n
m)
B36(R)
B18(R) B(R)
B(R)
B18 & B36(R)
As & As4
P4P
Hydrogen Bake
Surface Passivation
1 month later
-
Proof Of Surface Reflectance/Backscatter On
Retained Dose Limit & Implant Oxide Growth
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
46
Ge Ox Xj R.Dose
H2 6.9nm 0.2nm
B 7.0nm 0.57nm 8.3nm 8.89E14
B18 6.9nm 0.45nm 7.7nm 8.44E14
B36 6.9nm 0.46nm 8.6nm 8.35E14
Ox 6.9nm 1.8nm
B 7.0nm 2.05nm 7.7nm 8.0E14
B18 6.7nm 2.18nm 7.6nm 6.09E14
B36 6.9nm 2.3nm 9.6nm 5.96E14
Ge shift due to oxide growth
Implant oxide growth
Renesas/JOB/EAG, SSDM-2010
-
Hydrogen Annealing of Si & Ge Surface
4/27/2015 Advanced Integrated Photonics, Inc. -
Proprietary47
Round Top
Smooth SidewallLER (line-edge-
roughness)
-
Hydrogen Bake Causes Si-surface Migration and
Si/oxide Under-cut! Good for Bulk not SOI FinFET
4/27/2015 48
44) M. Arst, J. Chen, K. Ritz, J. Borland and J. Hann, A Novel Simultaneous Single/Poly Deposition (SSPD)
Technique For New And Scaled-Down Device Structures, Semiconductor Silicon 1990, the Electrochemical Society, PV 90-7, p.794, 1990.
45) M. Arst, K. Ritz, S. Redkar, J. Borland and J. Hann, Surface Planarity And Microstructure Of Low Temperature
Silicon SEG And ELO, Journal of Materials Research, the Materials Research Society, vol.6, no.4, p.784, April 1991.
H2 Bake Reduce LER (line-edge-roughness) Not With
SOI-FinFET!
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
49
iPhone 6 Mother board
iPhone 6+ Mother board
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
50
D. James, Chipworks, Oct 2014
TSMC, US Patent #8,674,453 B2, 3/18/14
Is SF-stressor+eSiP
epi stressor better?
Intel 32nm
TSMC 20nm Node: Stacking Fault-Stressor 4/5 years
after Intels 32nm Node in 2009
-
Outline Introduction: Smartphone as new technology driver
2012: iPhone 5 uses Sonys 3-D stacked backside CMOS image sensor camera
2015: 1) Samsung Galaxy S6 and Apple iPhone 6s A9 application processors
switches to 14/16nm 3-D FinFET. 2) Samsung Galaxy S6 introduces 3-D ePoP
(embedded package on package)
22/20nm Node: Smartphone Application Processor 2014-2015
using 3-D bulk-FinFET from Intel (China low end smartphones),
2-D planar by TSMC and Samsung (A8-iPhone6 & Galaxy-S5)
14/16nm Node: Smartphone Application Processor 2015-2016
3-D bulk-FinFET 1st generation by TSMC & Samsung (Galaxy-
S6 and A9-iPhone6s), 2nd generation by Intel
10/7nm Node: High mobility material SiGe or Ge Fin channel
Formation
Exploratory Research 5nm Node: High mobility material
Nano-wire channel formation
Dopant Activation and Junction Leakage in Ge and SiGe
Summary51
-
Intel can still use Bi-mode up to 41 degree tilt
implant or Quad-mode >45-60 degree tilt!
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
52
For 22nm I
said 3 years
ago Intel
could use up
to 52 degree
high tilt
implant.
For 14nm I
estimate Intel can
use up to 41 degree
tilt if twist is 0
degree for bi-mode
but if twist is 45
degree then Quad-
mode >45-60
degree is OK!
8 degree taper=(551) plane &
45+8=53 degree effective tilt
Intel 8/11/14
-
IEDM-2014 Paper 3.7 by Natarajan of Intel on A 14nm Logic Technology
Featuring 2nd Generation FinFET Transistors, Air-Gapped Interconnects,
Self-Aligned Double Patterning and a 0.0588um2 SRAM cell size.
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
53
First time Intel is using embedded n+epi for
nS/D which is full of epi stacking faults
sub-fin doping technique of high performance transistor by solid source doping for better punch-
through stopper dopants. Idsat & Idlin for nMOS +15% & +30% and for pMOS +41% & +38%
No discussion on p+ or n+ eS/D stressor! Chipworks
says eSiGe=55% like 22nm node
-
Intel 14nm nMOS FinFET
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
54
Dick James, Chipworks, Feb 2015
-
IEDM-2014 Paper 3.1 by Wu of TSMC on An Enhanced 16nm
CMOS Technology Featuring 2nd Generation FinFET Transistors
and Advanced Cu/low-k Interconnect for Low Power and High
Performance Applications.
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
55
A disappointment this year as in last year in that
TSMC showed no images nor listed any dimensions
of the FinFET structure so as Dick James of
Chipworks stated in his blog with NO images of the
FinFET we have no idea what the FinFET looks
like (ie tapered or vertical Fins, recess/raised S/D
WITH DUAL EPITAXY PROCESSING).
-
Samsung
Galaxy S6
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
56
Dick James, Chipworks, April 6, 2015
Battery
ePOP
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
57
Samsung Galaxy S6 Dick James, Chipworks, April 6, 2015
eSiGe?
-
J.O.B. Technologies (Strategic
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58
SAMSUNG GALAXY S6 EDGE SM-G925V Top Cost Drivers
Itemized Components MfgName Description Total Cost
Display SAMSUNGDisplay / Touchscreen Module, 5.1
Quad HD Super AMOLED,
25601440 Pixels, 577PPI, Dual Edge$85.00
IC Content
Apps Processor SAMSUNG Apps Processor Octa-Core, 64-Bit, 14nm, PoP $29.50
Baseband IC QUALCOMM Baseband Processor Multi-Mode, 28nm, PoP $15.00
Memory
NAND (eMMC, MLC, ) SAMSUNG Flash UFS NAND, 64GB, PoP $25.00
DRAM SAMSUNG SDRAM LPDDR4, 3GB, PoP $27.50
Power Management Ics $5.40
RF / PA Section $12.50
User Interface Ics $9.95
Sensors $4.80
Modules
Primary Camera Module Rear Camera Module 16MP, BSI CMOS, OIS $18.50
Secondary Camera Module Front Camera Module 5MP, BSI CMOS $3.00
BT / WLAN Module(s) MURATA BT / WLAN Module $4.00
Battery Pack(s) ITM Li-Polymer, 3.85V, 2600mAh, 10.01Wh $3.50
Other Noteworthy Items
Box Contents $6.20
Enclosure elementsDie-Cast Aluminum Center Piece &
Machined Aluminum Bottom Piece$12.00
Source: IHS Technology April 2015
39/Gb!
-
Outline Introduction: Smartphone as new technology driver
2012: iPhone 5 uses Sonys 3-D stacked backside CMOS image sensor camera
2015: 1) Samsung Galaxy S6 and Apple iPhone 6s A9 application processors
switches to 14/16nm 3-D FinFET. 2) Samsung Galaxy S6 introduces 3-D ePoP
(embedded package on package)
22/20nm Node: Smartphone Application Processor 2014-2015
using 3-D bulk-FinFET from Intel (China low end smartphones),
2-D planar by TSMC and Samsung (A8-iPhone6 & Galaxy-S5)
14/16nm Node: Smartphone Application Processor 2015-2016
3-D bulk-FinFET 1st generation by TSMC & Samsung (Galaxy-
S6 and A9-iPhone6s), 2nd generation by Intel
10/7nm Node: High mobility material SiGe or Ge Fin channel
Formation
Exploratory Research 5nm Node: High mobility material
Nano-wire channel formation
Dopant Activation and Junction Leakage in Ge and SiGe
Summary59
-
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
60
Samsung Logic Roadmap, Dec. 2014
-
4/27/2015 Advanced Integrated Photonics, Inc. -
Proprietary61
IEDM-2013 short course
*2014: SiGe-FinFET at 14nm*2016: Ge-FinFET at 10nm*2018: Nano-wire at 5nm (Si, SiGe and Ge)
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IEDM-2014 Paper 16.1 by Hashemi of IBM/GF on First Demonstration
of High-Ge-Content Strained-Si1-xGex (x=0.5) on Insulator PMOS
FinFETs with High Hole Mobility and Aggressively Scaled Fin
Dimensions and Gate Lengths for High Performance Applications.
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Fig.14 shows hole mobility increases by 2.2x from uh=160 to 400 with
decreasing Fin width (WFIN) due to the transformation of strain from biaxial to
uniaxial. The uh=160 corresponds to a 1E18/cm3 channel doping level for 50%
SiGe in the literature. The uh=400 would be for 80-100% SiGe channel at the
same doping level.
Oct 2014 ECS IBM Alliance paper P7-1791
Need >50% Ge to enhance
hole mobility?
-
4/27/2015 63
See large variation in reported Ge electron & hole mobilities reported in the literature!
Ge-Cz
U of Tokyo
Electron mobility
Hole mobility
H2 anneal
P or As
Excico
P-JOB laser
Sb-JOB laser
B-JOB laser
IBM
50%
SiGe
p+Fin
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4/27/2015 64
IEDM-2013 short course
Borland: Localized Ge-LPE by Laser Melt Oct 2004 ECS: Ge-GCIB/Infusion (E17/cm2)June 2013 IWJT: Ge-plasma implant (1E17/cm2)Oct 2014 ECS: Ge-beamline implant (5E16/cm2)
Blanket Ge-layer first
then Ge-Fin etch
Selective Ge-epi Fin
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SSDM-2013 Univ of Tokyo Si-Photonics paper K-1-1 on Ge Active Photonic Devices on Si for
Optical Interconnects was a invited review paper so no new data only a review. In Fig.2 below
he showed a 800oC Ge-Epi post anneal can reduce TDD from 109/cm2 to
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Ge-channel Formation By Ge-Infusion Doping
ALD-HfSiO
1) EOT reduced from
1.46nm to 1.26nm with in-
situ bake due to GeO
eliminationat >430C.
2) Leakage reduced from
0.07A/cm2 to 0.04A/cm2
without bake.
3) pMOS good devices
4) nMOS poor devices
nMOS Ge-channel formation using replacement gate process flow
Borland et al., JOB/ReVera/SSM/Genus/Epion, Solid State Technology, July 2005
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GCIB Ge-Doping/Deposition (Solid Phase Epitaxy)70nm Ge-DCD on 300mm bulk & SOI wafer
-
J.O.B. Technologies (Strategic
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Technology)
HF-vs-No HF
Cleaning For Ge
Infusion
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SSDM-2011: Intel 32nm NodeChannel strain measurements Munehisa Takei1, Hiroki Hashiguchi1, Takuya Yamaguchi1, Daisuke
Kosemura1, Kohki Nagata1, 2, and Atsushi Ogura1
1School of Science and Technology, Meiji University, 1-1-1
Higashimita, Tama-ku, Kawasaki, 214-8571, Japan
3.75GPa 850MPa
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Localized/Selective Ge & SiGe
Formation By Liquid Phase
Epitaxy (LPE) Using Ge+B
Plasma Ion Implantation And
Laser Melt Anealing
Ge 3keV at 1E16/cm2 (Ge=20%) & 1E17/cm2 (Ge=55%)
B2H6 500V at 4E15/cm2 & 4E16/cm2
Ge+B Plasma Implanted Wafers Provided by Micron
Laser Melt Annealing Provided by Innovavent & Excico
IWJT June 6, 2013
JOB Technology, Micron, Innovavent, Excico, KLA-Tencor, CNSE, EAG & UCLA
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0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600
Mo
bilit
y (
cm
2V
-1s
-1)
Depth ()
Mobility JA14ED12-1
Drift
0
10
20
30
40
50
60
70
80
90
100
110
120
130
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150
160
170
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600
Depth ()
Ge=1E17/cm2 + BH=4E16/cm2
Ge=1E16/cm2 + BH=4E15/cm2
>4x hole-mobility!
ALP Hall Analysis of 308nmSlot#14:Ge=1E16+B=4E15
Slot#18: Ge=1E17+B=4E16
Ge=0%+BH=4E16/cm2
Borland et al., IWJT-2013
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Liquid Phase Epitaxy (LPE)
Formation of Localized High
Quality/Mobility Ge & SiGe by High
Dose Ge-Implantation with Laser Melt
Annealing for 10nm and 7nm Node
Oct 6, 2014 ECS Conference on SiGe & Ge TechnologyJohn Borland1,2, Michiro Sugitani3, Peter Oesterlin4, Walt Johnson5, Temel
Buyuklimanli6, Robert Hengstebeck6, Ethan Kennon7, Kevin Jones7 & Abhijeet Joshi8
1JOB Technologies, Aiea, Hawaii2AIP, Honolulu, Hawaii
3SEN, Shinagawa, Tokyo, Japan4Innovavent, Gottingen, Germany5KLA-Tencor, Milpitas, California6EAG, East Windsor, New Jersey
7University of Florida, Gainsville, FL8Active Layer Parametrics, LA, CA
-
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1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
1E+17
1E+18
1E+19
1E+20
1E+21
1E+22
1E+23
0 10 20 30 40 50 60 70 80
O,S
i,G
e C
ON
CE
NT
RA
TIO
N (
ato
m%
)
Sb
CO
NC
EN
TR
AT
ION
(ato
ms/c
c)
DEPTH (nm)
JOB Sample 3 Si Sb+Ge 3E15 5E16 No Anneal (Sb, Ge)
O->
Si->Ge->
Total Sb
Fig #03 Y0DKY928_YR_37 Sample 3 Si Sb+Ge 3E15 5E16 No Anneal (Sb, Ge)
1/11/2014
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
1E+17
1E+18
1E+19
1E+20
1E+21
1E+22
1E+23
0 10 20 30 40 50 60 70 80
Sb
CO
NC
EN
TR
AT
ION
(ato
ms/c
c)
DEPTH (nm)
JOB Sample 5 Si Sb+Ge 3E15 LMA 4J 1200ms (Sb, Ge)
O->
Si->Ge->
Total Sb
Fig #05 Y0DKY928_YR_38 Sample 5 Si Sb+Ge 3E15 LMA 4J 1200ms (Sb, Ge)
1/11/2014
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
1E+17
1E+18
1E+19
1E+20
1E+21
1E+22
1E+23
0 10 20 30 40 50 60 70 80
O,S
i,G
e C
ON
CE
NT
RA
TIO
N (
ato
m%
)
Sb
CO
NC
EN
TR
AT
ION
(ato
ms/c
c)
DEPTH (nm)
JOB Sample 4 Si Sb+Ge 3E15 LMA 3.2J (Sb, Ge)
O->
Si->
Ge->
TotalSb
Fig #04 Y0DKY928_YR_54 Sample 4 Si Sb+Ge 3E15 LMS 3-2J (Sb, Ge)
1/13/2014
Ge=>7%
350nm
-
75
0
50
100
150
200
250
300
350
400
450
500
1E+12 1E+13 1E+14 1E+15 1E+16
Mo
bili
ty[c
m2
/V-s
]
Sb Concentration
Electron Mobility
Ge+Sb 3E13 4J/cm2 for 600ns
Ge+Sb 3E15 4J/cm2 for 600ns
Sb 3E15 4J/cm2 for 600ns
Ge+Sb 3E15 4J/cm2 for 1200ns
Ge=100%
Ge=100%Si=100%
Si=100%
4% Ge
Borland et al., ECS Oct 2014
B=4E16
Ge=100%
Ge=25%
Ge=0%
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Ge-channel Formation by Ge implant, plasma or
GCIB doping (n+Si-cap S/D doping)
76
nMOS Ge-channel formation using replacement gate process flow
Borland et al., SST July 2005 & US Patent #7,259,036 Aug 22, 2007
Bulk Si-wafer
Ge
or
SiGe
nMOS Ge-Fin/channel nMOS n+ Si-S/D
Si-SEG
n+ S/DBorland proposal March 2012
Bulk Si-wafer
Ge
or
SiGe
OxideOxide Oxide
n+ Si-S/D Ge-channel
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IEDM-2014 Paper 16.5 by Mitard of IMEC on First
Demonstration of 15nm WFIN Inversion Mode Relaxed Ge n-
FinFETs with Si-cap Free RMG and NiSiGe S/D.
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He listed the options for FinFET as follows:
pFinFET nFinFET
-relaxed Ge -relaxed Ge
-strained Ge on SiGe SRB -strain-Si
-strained SiGe on Si -InGaAs/InP on Si
The process flow is listed in Fig.1 below whereby they first grow a heterogenous Ge-epilayer on Si wafer
followed by Well, ground plane and anti-punch through implant. Next was the Fin defined STI etch and low
temperature fill and oxide recess (see Fig.2 of the Ge-Fin after STI oxide recess). After dummy gate they do
tilted Phos implant for extension and B implant for HALO. Following nitride spacer they grow a 45% SiGe
S/D cap followed by HDD Phos implant then junction anneal at
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1
10
100
1000
10000
100000
1000000
10000000
60 60.5 61 61.5 62 62.5 63 63.5
Series1
JB1-40+76
JB1-40+00
JB1-40-55
JB1-40-74
JB1-40+38
JB1-40+20
1
10
100
1000
10000
100000
1000000
10000000
60 60.5 61 61.5 62 62.5 63 63.5
Series1
Implant Changing Ge-epi Strain (Tensile & Compressive)
JOB/LASSE/WaferMasters
JOB/CNSE/Nissin/LASSE
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Outline Introduction: Smartphone as new technology driver
2012: iPhone 5 uses Sonys 3-D stacked backside CMOS image sensor camera
2015: 1) Samsung Galaxy S6 and Apple iPhone 6s A9 application processors
switches to 14/16nm 3-D FinFET. 2) Samsung Galaxy S6 introduces 3-D ePoP
(embedded package on package)
22/20nm Node: Smartphone Application Processor 2014-2015
using 3-D bulk-FinFET from Intel (China low end smartphones),
2-D planar by TSMC and Samsung (A8-iPhone6 & Galaxy-S5)
14/16nm Node: Smartphone Application Processor 2015-2016
3-D bulk-FinFET 1st generation by TSMC & Samsung (Galaxy-
S6 and A9-iPhone6s), 2nd generation by Intel
10/7nm Node: High mobility material SiGe or Ge Fin channel
Formation
Exploratory Research 5nm Node: High mobility material
Nano-wire channel formation
Dopant Activation and Junction Leakage in Ge and SiGe
Summary79
-
IMEC: Selective Epi Fin
80
IMEC: Si-Fin SiGe-Fin Ge-Fin InGaAs-Fin
-
Outline Introduction: Smartphone as new technology driver
2012: iPhone 5 uses Sonys 3-D stacked backside CMOS image sensor camera
2015: 1) Samsung Galaxy S6 and Apple iPhone 6s A9 application processors
switches to 14/16nm 3-D FinFET. 2) Samsung Galaxy S6 introduces 3-D ePoP
(embedded package on package)
22/20nm Node: Smartphone Application Processor 2014-2015
using 3-D bulk-FinFET from Intel (China low end smartphones),
2-D planar by TSMC and Samsung (A8-iPhone6 & Galaxy-S5)
14/16nm Node: Smartphone Application Processor 2015-2016
3-D bulk-FinFET 1st generation by TSMC & Samsung (Galaxy-
S6 and A9-iPhone6s), 2nd generation by Intel
10/7nm Node: High mobility material SiGe or Ge Fin channel
Formation
Exploratory Research 5nm Node: High mobility material
Nano-wire channel formation
Dopant Activation and Junction Leakage in Ge and SiGe
Summary81
-
Trumble, Bell Labs, 1959
4/27/2015 Advanced Integrated Photonics, Inc. - 82
Excico P-LMAStanford Sb-LMA
IBM Sb-RTA
As-MLD
As-LSA
-
Boron Activation in Si & Ge
4/27/2015 83
10
100
1000
0 200 400 600 800 1000 1200 1400
She
et R
esi
stan
ce, (
oh
m/s
q)
RTP Temperature, C
Ge, 5e15/cm2 B
Ge, 5e14/cm2 B
Ge, 5e14/cm2 BF2
Si, 5e14/cm2 B
Si, 5e15/cm2 B
Si, 5e14/cm2 BF2
Ge-Melt 937C
Si-Melt 1407C
BF2 is self-amorphizing
Room temperatureB-activation (acceptor formation ~1E14/cm2)
Boron Rs is dose limited
Borland & Konkola, AIP, IIT-2014
-
1E+15
1E+16
1E+17
1E+18
1E+19
1E+20
1E+21
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
B C
ON
CE
NT
RA
TIO
N (
ato
ms/c
c)
DEPTH (m)
11B
LD047_ym20 Sample GHC1 (B) all data
AIP Ge 5e15 B No Anneal
Carrier Concentration
Borland & Konkola, AIP, IIT-2014
Zaima, Nagoya U., ECS Oct 2014, paper P7-1772
Room temperatureB-activation (acceptor formation ~1E19/cm3)
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Borland & Konkola, AIP, IIT-2014
-
IEDM-2014 Paper 32.5 by Lee of Univ of Tokyo on Dramatic
Effects of Hydrogen-induced Out-diffusion of Oxygen from
Ge Surface on Junction Leakage as well as Electron Mobility
in n-channel Ge MOSFETs
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To examine the effects of oxygen they implanted O at 1.0 and 10.0E14/cm2 dose at 100keV
shown in Fig.6 to a depth of 75nm. Fig.7 shows the Ge n+/p junction leakage for Phos implant
50keV/1E15 after annealing 400C to 650C for 30 sec without O-implant and for the 1E13 and
1E14 O-implants. Without Oxygen the lowest n+/p junction leakage is at 600C at 8E-3A/cm2
while with the higher O-implant dose it was 40x lower at 2E-4A/cm2. No data on dopant
activation Rs values in relationship to the junction leakage.
-
IEDM-2014 Paper 16.5 by Mitard of IMEC on First
Demonstration of 15nm WFIN Inversion Mode Relaxed Ge n-
FinFETs with Si-cap Free RMG and NiSiGe S/D.
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Results for the Ge n+/p junction leakage is shown in Fig.9 below and Fig.10 shows both p+/n and n+/p
junction leakage in Ge. They also used Ge-PAI to boost the B dopant activation in Ge to ~1E20/cm3 with
500C anneal. Ge n+ junction optimization was required to reduce n+/p Ge junction leakage by 20x from
4A/cm2 to 0.2A/cm2.
-
Summary: Smartphone the technology driver for 3-D
More Moore and More Than Moore in this Decade! Samsung Galaxy S6 using 14nm 3-D FinFET Application Processor, 16M pixel
CMOS image sensor camera, up to 128Gb Flash memory (2-D planar or 3-D 32-
layers) and thin ePoP (embedded package on package) memory, a single 3-D
memory package consisting of 3GB LPDDR3 DRAM, 32GB eMMC and a controller.
Apple iPhone 6s (Sept 2015) A9 will use 3-D FinFET Application Processor 14nm
from Samsung and 16nm FF+ from TSMC, >8M pixel 3-D stacked backside CMOS
image sensor camera from Sony and 64-128Gb Flash memory.
10nm=2016, 7nm=2018 & 5nm=2020!
High tilt 35-45 degrees bi-mode or quad-mode implantation will continue to be used
for FinFET SDE & S/D doping for 14nm, 10nm and 7nm node.
Amorphous implantation of the Fin is Good as it leads to highest dopant activation and
stressor formation.
Dual recess epi for p+ & n+ S/D stressor at 14nmneed direct high mobility channel/Fin by
10nm!
Ge, SiGe or GeSn high mobility channel-FinFET at 10nm or 7nm node will require
Ge-epi first approach or amorphous-Ge+LPE.
Low Ge n+ junction leakage will require
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