system module gate circuit device

Digital Integrated Circuits © Prentice Hall 1995IntroductionIntroduction

n+n+

S

G

D

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

Complementary Metal-Oxide-Semiconductor (CMOS) Transistors

NMOS PMOS

Source

Gate Gate

Source

Drain Drain

MOS Transistors as Switches

1

00

1

NMOS PMOS

Digital Integrated Circuits © Prentice Hall 1995

Static CMOS

VDD

VSS

PUN

PDN

In1

In2

In3

F = G

In1

In2

In3

PUN and PDN are Dual Networks

PMOS Only

NMOS Only

Basic Logic Gates

A

OUT = A

Digital Integrated Circuits © Prentice Hall 1995

Example: Full Adder

VDD

VDD

VDD

VDD

A B

Ci

S

Co

X

B

A

Ci A

BBA

Ci

A B Ci

Ci

B

A

Ci

A

B

BA

Co = AB + Ci(A+B)

28 transistors

MOSFET

Metal Interconnect

Digital Integrated Circuits © Prentice Hall 1995

Modern Interconnect

Select

Feedback-Based Latch

� Pro

» Holds data as long as power applied

» Actively drives output: can be made fast

� Con

» Big (5 transistors in this configuration)

Din/Dout

Charge-Based Latch

� Pro

» Small: 1 transistor, 1 capacitor (may be gate of transistor)

� Con

» Charge leaks off capacitor (~ 1 ms)

» Reads can be destructive and slow for large fan-out

Select

Din/Dout

Digital Integrated Circuits © Prentice Hall 1995

DRAM Trench Capacitor

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Array-Structured Memory Architecture

column decode

sense amplifiers

row

dec

od

e

row address

column address

Din/Dout

� All cells on

selected row

sensed

simultaneously

RC Switch Model

CL CL CL CL

RP

RN RN

RP

Signal Propagation (1)

t < 0

Vin = 0

t = 0

Vin = 1

Vout = 0

Vout = 0

Signal Propagation (2)

t = 1

Vin = 0

t = 2

Vin = 1

Vout = 0

Vout = 1

MOSFET IV Characteristics

CMOS Inverter

IDSp = - IDSnIDSp

IDSn

VoutVin = VGSn

= VDD + VGSp

VDSp = Vout - VDD

VDSn = Vout

S

D

D

S

Digital Integrated Circuits © Prentice Hall 1995

CMOS Inverter Load Characteristics

In,p

Vin = 5

Vin = 4

Vin = 3

Vin = 0

Vin = 1

Vin = 2

NMOSPMOS

Vin = 0

Vin = 1

Vin = 2Vin = 3

Vin = 4

Vin = 4

Vin = 5

Vin = 2Vin = 3

CMOS �Load Lines�

Finding CMOS VTC--1

Finding CMOS VTC--2

Finding CMOS VTC--3

CMOS VTC--Spice Results

Digital Integrated Circuits © Prentice Hall 1995

Dynamic Power Consumption

V in V o u t

C L

Energy/transitio n = C L * V d d2

Pow er = Energy /transition * f = C L * V dd2 * f

Need to reduce C L , V dd , and f to redu ce power.

Vdd

N o t a func tion of transistor sizes!

Digital Integrated Circuits © Prentice Hall 1995Combinational LogicCombinational Logic

Dynamic Logic

Mp

Me

VDD

PDN

φ

In1

In2

In3

Out

Me

Mp

VDD

PUN

φ

In1

In2

In3

φ

φ

Out

CL

CL

φp networkφn network

2 phase operation:• Evaluation

• Precharge