state of the art in fpga technology jecel assumpção jr lcr - icmc - usp são carlos jecel...

State of the art in FPGA technology

Jecel Assumpção JrLCR - ICMC - USP

São Carlos

QuickTime™ and a decompressor

are needed to see this picture.

topicstopics

• Xilinx vs Altera• Bit players• Rookies• Alternatives

• Xilinx vs Altera• Bit players• Rookies• Alternatives

Xilinx vs AlteraXilinx vs Altera

• First FPGA (1985)• Sells

US$1.7B/year

• First FPGA (1985)• Sells

US$1.7B/year

• First reprogrammable logic device (1984)

• First CPLD (1988)• Sells

US$1.2B/year

• First reprogrammable logic device (1984)

• First CPLD (1988)• Sells

US$1.2B/year

QuickTime™ and a decompressor

are needed to see this picture.QuickTime™ and a decompressor

are needed to see this picture.

QuickTime™ and a decompressor

are needed to see this picture.

Xilinx vs AlteraXilinx vs Altera

• High End = Virtex• 1998• 1999 E• 2000 II• 2002 II Pro• 2004 4 LX/SX/FX• 2006 5

LX/LXT/SXT• 2008 5 FXT/TXT• 2009 6

• High End = Virtex• 1998• 1999 E• 2000 II• 2002 II Pro• 2004 4 LX/SX/FX• 2006 5

LX/LXT/SXT• 2008 5 FXT/TXT• 2009 6

• High End = Stratix• 2002• 2003 GX• 2004 II• 2005 II GX• 2006 III• 2008 IV E• 2008 IV GX

• High End = Stratix• 2002• 2003 GX• 2004 II• 2005 II GX• 2006 III• 2008 IV E• 2008 IV GX

Xilinx vs AlteraXilinx vs Altera

• Low End = Spartan• 1998• 1999 II• 2001 IIE• 2003 3• 2005 3E• 2006 3A• 2007 3AN/3A-DSP• 2009 6

• Low End = Spartan• 1998• 1999 II• 2001 IIE• 2003 3• 2005 3E• 2006 3A• 2007 3AN/3A-DSP• 2009 6

• Low End = Cyclone• 2003• 2004 II• 2007 III• 2009 IV

• Low End = Cyclone• 2003• 2004 II• 2007 III• 2009 IV

Xilinx vs AlteraXilinx vs Altera

Virtex 6 Stratix IV

technology 40nm 40nm

Logic cells 75K to 588K 72K to 803K

Block RAM 6M to 33M 7M to 33M

DSP 288 to 864 384 to 1024

Tranceivers Up to 48+24 Up to 48

I/O 380 to 720 372 to 920

speed 600MHz 600MHz

Bit player: LatticeBit player: Lattice

• ECP3 - lowest cost FPGA with SERDES

• XP2 - 90nm Flash• Also ECP2, ECP2M and SC

• ECP3 - lowest cost FPGA with SERDES

• XP2 - 90nm Flash• Also ECP2, ECP2M and SC

QuickTime™ and a decompressor

are needed to see this picture.

Bit player: ActelBit player: Actel

• Igloo and ProASIC3 - low power• SmartFusion and Fusion - mixed

signal• RTAX, RTProASIC3 and RTSX -

radiation tolerance• Axcelerator, SX-A, eX and MX -

antifuse

• Igloo and ProASIC3 - low power• SmartFusion and Fusion - mixed

signal• RTAX, RTProASIC3 and RTSX -

radiation tolerance• Axcelerator, SX-A, eX and MX -

antifuse

QuickTime™ and a decompressor

are needed to see this picture.

Bit player: QuickLogicBit player: QuickLogic

• Customer Specific Standard Products (CSSPs)

• Customer Specific Standard Products (CSSPs)

Bit player: AtmelBit player: Atmel

• Legacy devices - AT6000• AT40KAL + AVR8 = FPSLIC (Field

Programmable System Level Integrated Circuits)

• Legacy devices - AT6000• AT40KAL + AVR8 = FPSLIC (Field

Programmable System Level Integrated Circuits)

QuickTime™ and a decompressorare needed to see this picture.

EdinburghEdinburgh

• 1985 to 1988 - three generations of CAL up to CAL256

• 1989 - Algotronix formed, CAL1024• 1993 - bought by Xilinx: XC6200• Very popular for research, but not

commercially

• 1985 to 1988 - three generations of CAL up to CAL256

• 1989 - Algotronix formed, CAL1024• 1993 - bought by Xilinx: XC6200• Very popular for research, but not

commercially

Imperial CollegeImperial College

QuickTime™ and a decompressor

are needed to see this picture.

Rookie: Silicon BlueRookie: Silicon Blue

• Classic architecture• Low power• Low cost• Internal Flash

• Classic architecture• Low power• Low cost• Internal Flash

QuickTime™ and a decompressor

are needed to see this picture.

Rookie: AchronixRookie: Achronix

• 1.5GHz• picoPIPE assynchronous internal

architecture• SERDES• DDR3 controllers

• 1.5GHz• picoPIPE assynchronous internal

architecture• SERDES• DDR3 controllers

Rookie: TabulaRookie: Tabula

• 1.6GHz with 8 multiplexed designs• 48 SERDES• 5.5MB RAM• 220K to 630K logic cells

• 1.6GHz with 8 multiplexed designs• 48 SERDES• 5.5MB RAM• 220K to 630K logic cells

QuickTime™ and a decompressorare needed to see this picture.

Rookie: Tier LogicRookie: Tier LogicQuickTime™ and a decompressorare needed to see this picture.

QuickTime™ and a decompressor

are needed to see this picture.

Alternative: eASICAlternative: eASIC

• Standard Cell ASIC-like unit cost, power consumption performance and density

• Low up-front development cost• Simple, FPGA-like design flow• Device turnaround in only 4-6

weeks

• Standard Cell ASIC-like unit cost, power consumption performance and density

• Low up-front development cost• Simple, FPGA-like design flow• Device turnaround in only 4-6

weeks

QuickTime™ and a decompressor

are needed to see this picture.

Alternative: Stretch IncAlternative: Stretch Inc

QuickTime™ and a decompressor

are needed to see this picture.

QuickTime™ and a decompressor

are needed to see this picture.

Alternative: TripsAlternative: Trips

QuickTime™ and a decompressor

are needed to see this picture.

Alternative: XmosAlternative: XmosQuickTime™ and a

decompressorare needed to see this picture.

QuickTime™ and a decompressor

are needed to see this picture.

QuickTime™ and a decompressor

are needed to see this picture.

Alternative: MathStarAlternative: MathStar

QuickTime™ and a decompressor

are needed to see this picture.

Alternative: TileraAlternative: Tilera

QuickTime™ and a decompressor

are needed to see this picture.

QuickTime™ and a decompressor

are needed to see this picture.

Alternative: Stream Processors Inc

Alternative: Stream Processors Inc

QuickTime™ and a decompressor

are needed to see this picture.

QuickTime™ and a decompressor

are needed to see this picture.

Thanks!

referencesreferences

• http://www.xilinx.com/• http://www.altera.com/• http://lms.nthu.edu.tw/sys/read_attach.p

hp?id=17968• http://ce.et.tudelft.nl/FPL/trimbergerFPL

2007.pdf• http://www.fpga-guide.com/overview_fr

ame.html

• http://www.xilinx.com/• http://www.altera.com/• http://lms.nthu.edu.tw/sys/read_attach.p

hp?id=17968• http://ce.et.tudelft.nl/FPL/trimbergerFPL

2007.pdf• http://www.fpga-guide.com/overview_fr

ame.html

referencesreferences

• http://www.latticesemi.com/• http://www.actel.com/• http://www.quicklogic.com/• http://www.atmel.com/• http://www.algotronix.com/people/tom/a

lbum.html• http://www.doc.ic.ac.uk/~ipage/papers/c

am95.pdf

• http://www.latticesemi.com/• http://www.actel.com/• http://www.quicklogic.com/• http://www.atmel.com/• http://www.algotronix.com/people/tom/a

lbum.html• http://www.doc.ic.ac.uk/~ipage/papers/c

am95.pdf

referencesreferences

• http://www.siliconbluetech.com/• http://www.achronix.com/• http://www.tabula.com/• http://www.tierlogic.com/

• http://www.siliconbluetech.com/• http://www.achronix.com/• http://www.tabula.com/• http://www.tierlogic.com/

referencesreferences

• http://www.easic.com/• http://www.stretchinc.com/• http://userweb.cs.utexas.edu/~trips/• http://www.xmos.com/• http://www.mathstar.com/• http://www.tilera.com/• http://www.streamprocessors.com/

• http://www.easic.com/• http://www.stretchinc.com/• http://userweb.cs.utexas.edu/~trips/• http://www.xmos.com/• http://www.mathstar.com/• http://www.tilera.com/• http://www.streamprocessors.com/