si oxidation and dielectrics

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Si Oxidation and Dielectrics

Topics:

Capacitors & Dielectrics

Piezoelectrics

Oxide films on Silicon

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CapacitanceA parallel plate capacitor

when in a vacuum (above) and when a dielectric

material is present (below

Do ≡ charge density (C/m2)

o = permittivity of free space = 8.85 x 10-12 F/m

ξ ≡ electric field strength = V/l

P ≡ polarization, or increase in charge density due to presence of a dielectric

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The capacitance, C is related to the quantity of charge stored on

either plate Q by :

C = Q/V

Where V = applied voltage. Units for C are coulombs per

volt, or faradsCapacitance can also b e

expressed as

C = oA/l

Where o is permittivity of free space, A is the area of the plate and l is the plate

separation distance

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If a dielectric is placed between the plates, the capacitance is:

C = A/l

is the permittivity of the dielectric. The relative permittivity, r, called the material dielectric constant, is typically used:

r = o

Thus

C = ro A/l

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The applied electric field aligns the poles of the

molecules in the dielectric. This is the source of

polarization.

The charge density, D, is

Dξ + P

And P may be written as

P = o(r-1)ξ

Thus

D =orξ

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Effect of frequency and temperature on the

permittivity of soda-lime-silica glass

Relative permittivity of nitrobenzene as a

function of temperature

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Variation of dielectric constant with frequency of an alternating electric field. Electronic, ionic and

orientation polarization contributions to the dielectric constant are indicated

Electronic polarization: fluctuations in the electron

cloud

Ionic polarization: displacement of ions in an

ionic compound

Orientation polarization: rotation of permanent

dipole moments in presence of an applied

field

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Dielectric Breakdown

Dielectric strength of various solids, gases and vacuum in uniform fields. Breakdown voltage versus dielectric

thickness is plotted

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• In a series circuit, capacitance is :

C1 C2 ntotal CCCC 1....11

21

• In a parallel circuit, circuit, capacitance is

Ctotal = C1 + C2 +…Cn : C1C2

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Piezoelectrics

In a piezoelectric material, e.g. barium titanate, the Ti4+

and O2- ions are offset as shown

Figure (a) shows the electric dipoles in a piezoelectric material

When the material is compressed (b) the central Ti4+ is displaced,

creating a voltageApplying a voltage (c) reverses this

affect, causing the ions to move farther apart

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PiezoelectricsField produced by stress:

gStrain produced by field:

d

Elastic modulus: gd

E 1

= electric field

= applied stress

E=Elastic modulus

d = piezoelectric constant

g = constant

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Thermal Oxidation and the Si/SiO2 Interface

Oxides play an important part in semiconductor fabrication. They are:

•Easily grown or deposited on many substrates

•Adhere well

•Block diffusion of dopants and other unwanted impurities

•Resistant to most processing chemicals

•Easily patterned and etched with plasmas or specific chemicals

•Excellent insulators

•Have stable and reproducible propertiesVirtually all other semiconductor/insulator combinations suffer from one or more problems that significantly limit their

applicability

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The most critical application of insulators in CMOS devices is as gate insulators. As seen above, these need to be <1 nm thick within the next 4

years

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• SiO2 layers in CMOS are used as:– Gate dielectric layers– A mask against

implantation– An isolation region

laterally between devices

– An insulator between metal layers

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Oxide Growth

Oxides are thermally grown on wafers by heating in the presence of O2 or H2O

In ambient conditions, an oxide ~1 nm thick forms

After several hours, its final

thickness is 1-2 nm

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Basic Concepts

New interface moves downward into Si

Because SiO2 is less dense than Si, it expands.

This places the Si substrate in tension, and

compresses the SiO2, forcing it upward

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SiO2 layers are amorphous. The bridging oxygen bonds can rotate, randomly accommodating

SiO2 tetrahedra

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Charges associated with the SiO2/Si system

There are four basic types of defects or

charges at the interface:1. Qf, the fixed oxide charge. It has magnitude of 109 – 1011 cm-2 very close to the interface. Results from incompletely oxidized Si atoms with a net positive charge. Qf is stable.

2. Qit, the interface trapped charge. Similar to Qf, with dangling bonds located in oxide, very close to interface. Charge on Qit may be positive, negative or neutral and can change during operation. Density is about the same as Qf.

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Charges associated with the SiO2/Si system

There are four basic types of defects or

charges at the interface:3. Qm, mobile charges. These are often processing artifacts causing erratic gate threshold voltages. These problems have been largely eradicated with proper cleanroom techniques.

4. Qot, the oxide trapped charge. Occurring anywhere in the oxide, these result from broken Si-O bonds, away from the interface. Usually caused by processing damage, they can often be removed by high-temperature annealing.

All types of charged defects have a negative effect on device performance

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Oxide Measurement MethodsOptical

Light reflection from a sample with a transparent thin film on its surface. no is the index of refraction in air (1.0), ni is that of the film and n2 is that of the substrate. is the angle of incident light, is the angle of reflecting light at the bottom of the interface

1

1

1minmax,

sinsin

cos2

nn

wheremxn

o

o

m = 1,2,3… for maxima and ½, 3/2,

5/2… for minima

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Measurement Methods: the MOS Capacitor

accumulation

depletion

If a DC voltage +VG is applied to the gate, negative charges will be attracted across the oxide layer, producing a capacitance Cox

If a negative voltage -VG is applied to the gate, negative charges will be repelled across the oxide layer, producing depletion region with its own capacitance, CD, in series with the oxide capacitance Cox

|QG| = |QD| = ND/xD

Where QG, QD are units of number of charges per cm2, ND is the doping in the substrate (assumed uniform). xD is the depth of the

depletion region.CD = s/xD

s = permittivity of Si

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Measurement Methods: the MOS Capacitor

inversion

If a large enough –VG is applied, it will attract minority carrier holes in the substrate to the surface and form an inversion layer (in this case, of P-type carriers.

The gate voltage at which this occurs is called the threshold voltage, Vth. At this point, xD stops expanding at xDMax

For all regions of the capacitor, the gate charge must be balanced by the charge on the substrate, or:

QG = NDxD + QI,

Where QI is the charge density on the inversion layer. Since xD is maximum, the CV curve reaches a minimum as shown above.

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The End

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