safedrp: yet another way toward power-equalized designs in … · 2017-08-24 · 13.04.17 safedrp:...

13.04.17

SafeDRP: Yet Another Way TowardPower-Equalized Designs in FPGA

COSADE 2017

Maik Ender, Alexander Wild, and Amir Moradi

2COSADE 2017 | SafeDRP | Maik Ender

▪ Variety of countermeasures

• Rekeying

• Masking

• Hiding

Motivation and Background

• Rekeying

• Masking

• Hiding

▪ This talk: power equalization on FPGAs

• Dynamic power consumption switches

• Rekeying

• Masking

• Hiding

▪ Why do we need another scheme?

• Pitfalls in implementation

• Lastly published GliFreD has high resource consumption of FF

• Rekeying

• Masking

• Hiding

▪ Why do we need another scheme?

• Pitfalls in implementation

• Lastly published GliFreD has high resource consumption of FF

▪ Idea: less FF while addressing all pitfalls

Field Programmable Gate Array

Concept

Source: Electronics 2015; Optimally Fortifying Logic Reliability through Criticality Ranking; http://www.mdpi.com/2079-9292/4/1/150/htm

Field Programmable Gate Array

Concept

Source: Electronics 2015; Optimally Fortifying Logic Reliability through Criticality Ranking; http://www.mdpi.com/2079-9292/4/1/150/htm

▪ Differential encoding

▪ Valid values: 10 or 01

▪ No Inverter

Dual-Rail-Precharge (DRP)

Dual-Rail Logic

▪ No Inverter

Dual-Rail Logic Precharge Logic

▪ Alternates between

Precharge and logic value

▪ Precharge and evaluation

▪ No Inverter

Dual-Rail Precharge Logic

• Precharge phase: 00 or 11

• Evaluation phase: 01 or 10

▪ One transition per phase

▪ No Inverter

Dual-Rail Precharge Logic

• Precharge phase: 00 or 11

• Evaluation phase: 01 or 10

▪ One transition per phase

▪ Transition based on the

arriving signals

Pitfalls

Early Evaluation

arriving signals

Pitfalls

Early Evaluation Glitches

▪ Undesired transition

arriving signals

Pitfalls

Early Evaluation Glitches

▪ Undesired transition

Routing

▪ Different

capacities

Pictures Soruce: Wei He, et.al.; A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations

Idea of Our Advanced Hiding Schemes

LUT LUT

LUT• Early evaluation,

glitches

LUT LUT

glitches

• I/O-Handling

LUT LUT

glitches

• I/O-Handling

• Consider routing

LUT LUT

glitches

• I/O-Handling

LUT LUT

glitches

active signal

• I/O-Handling

LUT LUT

glitches

active signal

one after another

I/O-Handling

LUT LUT

glitches

active signal

one after another

I/O-Handling

LUT LUT

glitches

active signal

one after another

I/O-Handling

LUT LUT

glitches

active signal

one after another

I/O-Handling

LUT LUT

glitches

active signal

one after another

I/O-Handling

use FF/latches

Consider routing

LUT LUT

glitches

active signal

one after another

I/O-Handling

use FF/latches

Consider routing

LUT LUT

glitches

active signal

one after another

I/O-Handling

use FF/latches

Consider routing

LUT LUT

glitches

active signal

one after another

I/O-Handling

use FF/latches

Consider routing

Generate by Mixed-Mode Clock Manager (MMCM)

• Early evaluation,

glitches

active signal

one after another

• I/O-Handling

use FF/latches

duplication

1. Place&Route

LUT LUT

LUT FF

glitches

active signal

one after another

• I/O-Handling

use FF/latches

duplication

1. Place&Route

2. Clone

LUT LUT

LUT FF

LUT LUT

LUT FF

glitches

active signal

one after another

• I/O-Handling

use FF/latches

duplication

1. Place&Route

2. Clone

3. Place clone

LUT LUT

LUT FF

LUT LUT

LUT FF

glitches

active signal

one after another

• I/O-Handling

use FF/latches

duplication

1. Place&Route

2. Clone

3. Place clone

4. Invert

→ Equal routing

LUT LUT

LUT FF

LUT LUT

LUT FF

Side-Channel EvaluationMeasurement Setup

Source Sakura in Specification Guide and http://satoh.cs.uec.ac.jp/SAKURA/hardware/SAKURA-X.html

Source Picoscope: https://www.picotech.com/oscilloscope/6407/high-speed-digitizer

Source IBM: https://commons.wikimedia.org/wiki/File:IBM_PC_5150.jpg User Zarex

Xilinx Kintex-7 on Sakura-X

Round based AES-128

PicoScope 6402B @ 1.25 GS/s

Round based AES-128

PicoScope 6402B @ 1.25 GS/s

Round based AES-128

10,000,000 Traces

Comparison

[17] A. Moradi and A. Wild. Assessment of Hiding the Higher-Order Leakages

in Hardware - what are the achievements versus overheads? In CHES 2015

[30] A. Wild, et.al. GliFreD: Glitch-Free Duplication – Towards Power-Equalized

Circuits on FPGAs. IEEE Transactions on Computers, 2017.

Comparison

▪ Reduced FF utilization

• 8.9 Improved GliFreD

Comparison

• 17.3 GliFreD

Comparison

• 17.3 GliFreD

Comparison

• 17.3 GliFreD

Comparison

• 17.3 GliFreD

▪ Reduced latency but GliFreD might reach a higher max.

frequency

Comparison

▪ Signal-to-Noise ratio 𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

𝑣𝑎𝑟(𝑁𝑜𝑖𝑠𝑒)

• Dependency of the power traces to the plaintext

Side-Channel EvaluationMethods

▪ Information-Theoretic mutual information

• Amount of exploitable information

▪ Correlation power analysis (CPA)

• Common key recovery attack

• HW and bit model of intermediate S-Box state

▪ Moments-Correlating DPA (MC-DPA)

• Key recovery attack w/o particular power model

▪ Moments-Correlating DPA (MC-DPA)

• Key recovery attack w/o particular power model

▪ Semi-fix vs. random Welch’s t-test

• Overview of the existing detectable leakage

Side-Channel EvaluationProfiles

Duplication ± Active & Pre

✓ ✓

Profile 1 (SafeDRP)

Measurement Points

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Measurement Points

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Profile 3 (Unprotected)

Measurement Points

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Side-Channel EvaluationSNR

𝑆𝑁𝑅 =𝑣𝑎𝑟(𝑆𝑖𝑔𝑛𝑎𝑙)

Measurement Points

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Measurement Points

Decrease Factor 20.03784

0.00018≈ 214

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Measurement Points

0.00018≈ 313

0.00018≈ 214

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Side-Channel EvaluationIT (Mutual Information)

Measurement Points

✓ ✓

Profile 1 (SafeDRP)

Profile 2

0.00015≈ 183

Measurement Points

✓ ✓

Profile 1 (SafeDRP)

Profile 2

0.00015≈ 183

Measurement Points

0.00015≈ 265

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Side-Channel EvaluationCPA HW S-Box Intermediate Model

Measurement Points

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Decrease

Factor 29

Measurement Points

✓ ✓

Profile 1 (SafeDRP)

Profile 2

Decrease

Factor 29

Measurement Points

Rule of Thumb (RoT):2,184,700 𝑇𝑟𝑎𝑐𝑒𝑠to recover the key

n ≈28

✓ ✓

Profile 1 (SafeDRP)

Profile 2

RoT:𝜌2

2≈ 881

Decrease

Factor 29

Measurement Points

n ≈28

✓ ✓

Profile 1 (SafeDRP)

Profile 2

RoT:𝜌2

2≈ 881

Decrease

Factor 29

Measurement Points

HW Model does not fit

n ≈28

Profile 2

✓ ✓

Profile 1 (SafeDRP)

Side-Channel EvaluationMC-DPA

Measurement Points

Profile 2

✓ ✓

Profile 1 (SafeDRP)

Measurement Points

Rule of Thumb (RoT):244,000 𝑇𝑟𝑎𝑐𝑒𝑠

to recover the key

Profile 2

✓ ✓

Profile 1 (SafeDRP)

Measurement Points

RoT:𝜌2

2≈ 327

Decrease Factor 18

to recover the key

Profile 2

✓ ✓

Profile 1 (SafeDRP)

Measurement Points

RoT:𝜌2

2≈ 327

Decrease Factor 18

to recover the key

RoT:𝜌3

2≈ 468

Decrease Factor 21

Side-Channel EvaluationWelch’s T-Test

• Semi-fix vs. random

• 5th round first 64 bit

zero [1]

• 1,000,000 Traces

• Leakage only in 5th

[1] Evaluating the Duplication of Dual-Rail

Precharge Logics on FPGAs; Alexander

Wild, Amir Moradi, Tim Güneysu;

COSDAE 2015

Measurement Points

▪ Improved DRP scheme

• Reduce the FF utilization

• Complex control logic

▪ Addressing all pitfalls

• Avoiding glitches

• Preventing early evaluation

• Mitigate the imbalanced routings

▪ Combination [2] with sound masking scheme for a

practical secure implementation

Conclusion

[2] A. Wild and A. Moradi; Assessment of Hiding the Higher-Order Leakage in Hardware

– what are the achievements versus overheads?; CHES 2015

▪ Improved DRP scheme

• Reduce the FF utilization

• Complex control logic

▪ Addressing all pitfalls

• Avoiding glitches

• Preventing early evaluation

• Mitigate the imbalanced routings

▪ Combination [2] with sound masking scheme for a

practical secure implementation

Conclusion

[2] A. Wild and A. Moradi; Assessment of Hiding the Higher-Order Leakage in Hardware

– what are the achievements versus overheads?; CHES 2015

Thank you!

safedrp: yet another way toward power-equalized designs in … · 2017-08-24 · 13.04.17 safedrp:...

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