reconfigurable hardware design celoxica dk1.1 for rapid,fwinkler/psvfpga/... · 2003-02-21 ·...
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Celoxica DK1.1 for rapid, reconfigurable hardware design
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A Brief History of Celoxica
University Research Commercial Product Development
20001990 19991998
Joined SEHaD, an EC project with Ericsson, Matra and Infineon
100 employees
Changed name to Celoxica
Completion 3rd round private investment,
$20M, oversubscribed
Opened offices in Silicon Valley and London
40 employees
Partnered with Marconi &Xilinx for proof of concept
multimedia terminal demonstrating internet
reconfigurable logic
1996
Founded as ESL by ISIS Innovation, Oxford
University technology transfer group
Handel-Cdevelopment
begins
DK1 design suite product
launch
2001
Complete 4th
round funding of $30M
WindDirectpartnership
signed
AlteraACCESS
programme partnership
Xilinx software EDA Alliance
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A Software Approach to Designing Hardware – Why?
> Some problems are better expressed as a software algorithm
> Designs are often specified by a C/C++ executable
> Simplifies and delays hardware-software partitioning
> However - C/C++ have no support for hardware features:
� Hardware data types
� Notion of time – sequencing of operations
� Concurrency – parallelism
� Hardware style communications
� Reactivity – response to stimuli
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What is Handel-C?
> ISO-C (ANSI-C) extended for HW
� Designed to describe software algorithms compiled to hardware
> Based on OCCAM/CSP
ANSI C StandardLibrary
Side effectsi.e. x = i++ * y++;
Possible InfiniteRecursion
Parallellism - par{}
Macro procedures
Macro expressions
RAM & ROM
Enhanced bitmanipulation
Interfaces
Variable size registers
Signals
Handel-CStandard Library
Channels
ANSI-C Handel-C
ANSI-C constructsfor, while, if, switch etc.
Functions
Preprocessor macrosi.e. #define
Arrays
Structures
ArithmeticOperators
Bitwise LogicalOperators
i.e. ~, ^, &, |
Pointersi.e. +,-,*,/,%
Logical Operatorsi.e. &&, ||, !
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Key hardware adaptations> Assignment takes one clock-cycle
> Serial execution is default – Parallel is declared
> Declare and infer width of variables
int 5 a;int b;par {
a = b; // first clock-cycleb = a; // same clock-cycle
}
int 5 a;int b;par {
a = b; // first clock-cycleb = a; // same clock-cycle
}
int a;int b;{
a = b; // first clock-cycleb = a; // second clock-cycle
}
int a;int b;{
a = b; // first clock-cycleb = a; // second clock-cycle
}
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Pars and channels> With nested par and seq blocks
any serial/parallel execution tree can be built
> No finite state machines are needed to control the flow
> Parallel treads can communicate via channels
� Synchronised transfer of valuesBetween threadsBetween clock-domains
� I/O External (pads) Internal (ports) File (in simulation)
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Benefits
> A programming language for hardware rather than a hardware description language
> A high level of abstraction to express algorithmic functionalitywhile allowing full control over sequencing and resource use
> Simple timing model and par construct enables mixed sequential and parallel execution flow without FSM’s
> Compact readable code enable designers to investigate a larger design space to find more optimal solutions.
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A software-like design environment
> An integrated design environment with the look and feel of a software design system
� Manage multiple source, header and object files
� Symbol view with direct jump to definition or use
� Syntax high-lighting
> Verify and debug using a Symbolic Debugger
� Execute stepwise or to break-point or cursor
� Watch selected and local variable values
> Co-simulation with software and HDL-cores
> Fast compilation targeting FPGA (Xilinx, Altera, Actel)
> Immediate execution on plug-in prototyping boards
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SoftwareSoftware
SimulatorSimulator
Design Flow
EDIF
SimulatorSimulator
SynthesisSynthesis
VHDL/VerilogVHDL/Verilog
VHDL
EDIF
SimulatorSimulator
ExecutableSpecificationExecutable
Specification
Place and RoutePlace and RouteTarget DeviceTarget Device
Handel-CHandel-C
System Model
System Model
ASIC FlowASIC Flow
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Technology Partners
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Marconi Celoxica Technology Demonstrator
> Reconfigurable Hardware from Software
� FPGA based, no microprocessor or operating system
� Different applications from the same hardware
� Can be reconfigured over internet to new applications
> MMT 2000
� IP Phone
� MP3 player
� Games console
� Graphic display
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The MMT - Components
3Mb SRAM arranged in 3 blocks
Two XilinxV1000 FPGAs
Expansion Pins
16 Mb Flash RAM
80 MHz Clock
CPLDAudio Chip
Speaker
Ethernet Transceiver/MAC
Confidential Information of Celoxica Ltd.© Copyright 2001. All Rights Reserved.
Celoxica and the Celoxica logo are trademarks of Celoxica Ltd. All trademarks acknowledged.
Visit us on the Web:Visit us on the Web: http://www.http://www.celoxicaceloxica.com.com
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