random number generation section 3.10 section 4.12
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Random Number Generation
Section 3.10Section 4.12
Outline• Observations from the last week’s lab• Anatomy of a Verilog Program• More about Verilog
– Including a file– Test a Module with a Random Sequence
• Example: NAND Implementation of a NOT Gate
• The NAND Implementation of a NOR Gate– Implementation Using 74LS00
Observations from Last Thursday’s Lab (1)
• The verilog code should be saved in a *.v file, e.g. – fig3p37.v is the file name– to execute the simulation, you need to
type verilog +gui fig3p37.v &
Observations from Last Thursday’s Lab (2)
Correction: Remove semicolon from the end of timescale line.
Observations from Last Thursday’s Lab (3)
Correction: Use a backward quote (`), not a single quote (‘)
Observations from Last Thursday’s Lab (4)
Definition of the module
fig3p37 is the module name.I1 is the instance of the module.
Comment: You need both modules!
Observations from Last Thursday’s Lab (5)
System! Source file "fig3p37.v" cannot be opened for reading [Verilog-SFCOR]
Solution:[r2d2@localhost verilogSandBox]$ chmod 755 fig3p37.v
Question
// comments out a line
Question: How do I get the play button back?
If you comment out $stop and stop the simulation by using Initial #200 $finish, you will not get the play button.
What do you do then?
Solution: Simulation ->Reinvoke Simulator
Solution: Simulation ->Reinvoke Simulator
Select Yes
You Get the Play Button Back!
Play button
Review of What We have Learned
• A minimalist’s view of a verilog Module
• A minimalist’s view of a module test bench
Anatomy of a Verilog Module
module fig3p37 (A,B,C,D,E);output D,E;input A,B,C;wire w1;
and G1(w1,A,B);not G2(E,C);or G3(D,w1,E);
endmodule
module....endmodule
module fig3p37 (A,B,C,D,E);output D,E;input A,B,C;wire w1;
and G1(w1,A,B);not G2(E,C);or G3(D,w1,E);
endmodule
Always start the verilog programwith the keyword pairmodule…endmodule
The keyword module must always be terminated by the keywordendmodule.
output/input
module fig3p37 (A,B,C,D,E);output D,E;input A,B,C;wire w1;
and G1(w1,A,B);not G2(E,C);or G3(D,w1,E);
endmodule
1. output/input2. wire
Program Body
module fig3p37 (A,B,C,D,E);output D,E;input A,B,C;wire w1;
and G1(w1,A,B);not G2(E,C);or G3(D,w1,E);
endmodule
Program body
Anatomy of a Test BenchTest Bench
1. `timescale2. module module_tb (, , ,)…endmodule 3. ouput,reg4. Invoke the module5. Define the input vector
Use `include to reference a file
Troubleshooting Exercise:verilog +gui fig3p37.v &
Introduce a Random Test Vector• flip_me function
Q: What is the function of this module?
flip_me_tb.v• Test Bench Definition: Feed a random
sequence of binary numbers to flip_me.v
A=random inputB=flipped version of A
Test Bench for flip_me.vReference: Mano page 170-174.
`timescaleComment out time scaleEach time interval is one second.
include flip_me.v
Define outputs,regWe will read random numbers from a file.The random numbers are stored in t_A.vectornum is the index of the t_A.At the falling edge of the t_clock, a randomnumbers stored in t_A is transferred to A.
flip_me.v is called.
1000 time intervals will be simulated.
Clock Generation
t_clock is initially 0.t_clock is flipped every 5 time intervals.The period of t_clock is 10 time intervals.
Read numbers from an input file
Random number is stored in t_A.
Update at NegEdge of t_clock
At negative edge of t_clock,transfer the random number fromt_A to A.
Monitor Numbers
Monitor numbers
Waveforms
Run Verilog Using Command-line
$monitor only displays the results when A changes.Actual sequence: 101011001011…
Implement NOR with NANDs
C
D
E
F
A, B as inputs C,D, E as wiresF as output
G1
G2
G3 G4
nor_with_nand.v
nor_with_nand_tb.v
Use flip_me_tb.v as a guide. Complete the code for nor_with_nand_tb.v
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