princess sumaya univ. computer engineering dept. chapter 4: it students
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Princess Sumaya Univ.Computer Engineering Dept.
Chapter 4:Chapter 4:
IT StudentsIT Students
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Stored Program ArchitectureStored Program Architecture
Instruction Cycle
● Fetch an instruction from memory
● Decode the instruction
● Get the operands
● Execute the instruction
Where is the next instruction?
Program Counter (PC)
Instruction Pointer (IP)
Where is the operand?
Instructions(Program)
Operands(Data)
Opcode Operands
Binary Operand
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CPUCPU
Datapath
Control Unit
Register File
CU
ALU
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General-Purpose Register OrganizationGeneral-Purpose Register Organization
R1
R2
R3
R4
R5
R6
R7
MUX MUX
ALU
3 x 8Decoder
DSEL
ASEL BSEL
OPR
A B
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General-Purpose Register OrganizationGeneral-Purpose Register Organization
R1
R2
R3
R4
R5
R6
R7
MUX MUX
ALU
3 x 8Decoder
DSEL
ASEL BSEL
OPR
A B
Examples:
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General-Purpose Register OrganizationGeneral-Purpose Register Organization
Examples:
Instructions(Program)
Operands(Data)
00101 010 011 001 00
0000 0000 0000 0000
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Memory InterfaceMemory Interface
Address / Data Buses
Read / Write Control
Bidirectional /UnidirectionalData Bus
Read
Write
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Building a DatapathBuilding a Datapath
Datapath Elements
InstructionInstructionMemoryMemory
Addr
Data
AL
UA
LU
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
Write a program & compile it.Where do you want to put it?Where is the first instruction?What comes out of memory?Where to perform operation?Where are the operands?Who well tell us which reg?Where to store result?Can we save this reg to mem?
32
32
32
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Building a DatapathBuilding a Datapath
Datapath Elements
InstructionInstructionMemoryMemory
Addr
Data
AL
UA
LU
DataDataMemoryMemory
Addr
DataData
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
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Building a DatapathBuilding a Datapath
InstructionInstructionMemoryMemory
Addr
Data
AL
UA
LU
DataDataMemoryMemory
Addr
DataData
How can we read it back?
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
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Building a DatapathBuilding a Datapath
InstructionInstructionMemoryMemory
Addr
Data
AL
UA
LU
DataDataMemoryMemory
Addr
DataData
Finished executing instruction. Where is the next instruction?Why +4?
4
Ad
der
Ad
der
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
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Building a DatapathBuilding a Datapath
InstructionInstructionMemoryMemory
Addr
Data
AL
UA
LU
4
Ad
der
Ad
der
How can we add “immediate”?What if it is negative?
SignSignExtendExtend
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
DataDataMemoryMemory
Addr
DataData
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Building a DatapathBuilding a Datapath
InstructionInstructionMemoryMemory
Addr
Data
AL
UA
LU
4
Ad
der
Ad
der
SignSignExtendExtend
What about “JMP Rel Disp”?It can be positive or negative!
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
DataDataMemoryMemory
Addr
DataData
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Building a DatapathBuilding a Datapath
4
Addr
Data
SignSignExtendExtend
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
Ad
der
Ad
der
Ad
der
Ad
der
AL
UA
LU
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
DataDataMemoryMemory
Addr
DataData
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Building a DatapathBuilding a Datapath
4
Addr
Data
SignSignExtendExtend
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
Ad
der
Ad
der
Ad
der
Ad
der
AL
UA
LU
Why the shift?
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
DataDataMemoryMemory
Addr
DataData
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Building a DatapathBuilding a Datapath
4
Addr
Data
SignSignExtendExtend
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
Ad
der
Ad
der
Ad
der
Ad
der
AL
UA
LU
Why not use ALU instead of another adder?
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
DataDataMemoryMemory
Addr
DataData
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Cy, Z, etc
Adding Control Signals to the DatapathAdding Control Signals to the Datapath
4
Addr
Data
SignSignExtendExtend
00MMUUXX11
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Control Unit
Opcodeetc
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
DataDataMemoryMemory
Addr
DataData
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Adding Control Signals to the DatapathAdding Control Signals to the Datapath
4
Addr
Data
SignSignExtendExtend
00MMUUXX11
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Control Unit
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
DataDataMemoryMemory
Addr
DataData
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A Simple Implementation SchemeA Simple Implementation Scheme
ALU Control
ALUALU
3232
32
4ALU Cntrl
CyZ
slt R1, R2, R3
otherwise
RRifR
0
3211
Cy = 1 Carry from last adder
Z = 1 The result = 0
IT StudentsIT Students
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A Simple Implementation SchemeA Simple Implementation Scheme
Instruction Format
● Arithmetic/LogicOpcode Operand(s), Address, Code
0
6
Rs
5 5 5 5 6
Rt Rd Shift FunctRd = Rs Funct Rt
Funct ALU Operation ALU Cntrl Lines
100000 Add 0010
100010 Subtract 0110
100100 AND 0000
100101 OR 0001
101010 SLT 0111
Example: 000000 00011 00111 00101 00000 100000
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
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A Simple Implementation SchemeA Simple Implementation Scheme
Instruction Format
● Move ImmediateOpcode Operand(s), Address, Code
Rt = Value
Example: R1 = 12
001101 00000 00001 0000 0000 0000 1100
13
6
0
5 5 16
Rt Immediate
IT StudentsIT Students
16 bits (can be positive or negative)
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A Simple Implementation SchemeA Simple Implementation Scheme
Instruction Format
● Load MemoryOpcode Operand(s), Address, Code
35
6
Rs
5 5 16
Rt AddressRt = M [Rs + Addr]
32 bits 16 bits (can be positive or negative)
Example: R6 = M [R4 – 1 ]
100011 00100 00110 1111 1111 1111 1111
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A Simple Implementation SchemeA Simple Implementation Scheme
Instruction Format
● Store MemoryOpcode Operand(s), Address, Code
43
6
Rs
5 5 16
Rt AddressM [Rs + Addr] = Rt
Example: M [R7 – 2 ] = R9
101011 00111 01001 1111 1111 1111 1110
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A Simple Implementation SchemeA Simple Implementation Scheme
Instruction Format
● JE OperationOpcode Operand(s), Address, Code
4
6
Rs
5 5 16
Rt OffsetIf Rs = Rt then
PC = PC + 4*Addr
Example:
000100 00001 00100 1111 1111 1111 1111
PC is already incremented
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MMUUXX
Final Datapath DesignFinal Datapath Design
4
Addr
Data
SignSignExtendExtend
00MMUUXX11
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Rs
Rt
Offset, Addr, Immediate
Rt
Rd
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
DataDataMemoryMemory
Addr
DataData
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Program SetupProgram Setup
Write a Program
Assemble itStore it in Memory
Example:
001101 00000 00001 0000 0000 0000 1010
000000 00001 00001 00001 00000 100000
3 4 0 1 0 0 0 A
0 0 2 1 0 8 2 0
0
4
8000100 00001 00001 1111 1111 1111 1111
1 0 2 1 F F F F
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Datapath OperationDatapath Operation
Fetch Instruction
Decode Instruction
Get Operands
Execute it
CLKPC
I-Mem0
ƮM3401000A (MOV R1, 10)
13 0 1 10Rs Rt Immediate
Reg ASel0
0Data A ƮReg
1Reg CSel
Reg CLD
ALU MUX2 (Add)ALU Ctrl
Mem MUX
10Sign Ext10ALU ƮALU
10Data C
Adder MUX4PC Adder ƮAdder
ƮReg
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Datapath OperationDatapath Operation
How Fast Can the Clock Be?
CLKPC
I-Mem0
ƮM
Reg ASel
Data A ƮReg
Reg CSel
Reg CLD
ALU MUXALU Ctrl
Mem MUX
Sign Ext
ALU ƮALU
Data C
Adder MUXPC AdderƮclk
ƮReg
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Datapath OperationDatapath Operation
Fetch Instruction
Decode Instruction
Get Operands
Execute it
CLKPC
I-Mem4
00210820(Add R1,R1,R1)
Reg ASel1
10Data A
1Reg CSel
Reg CLD
ALU MUX2 (Add)ALU Ctrl
Mem MUX
10Data B20ALU20Data C
Adder MUX8PC Adder
0 1 1 32Rs Rt FunctRd
1 0Shift
0
4
0
1
2
0
10
10
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Datapath OperationDatapath Operation
Fetch Instruction
Decode Instruction
Get Operands
Execute it
CLKPC
I-Mem8
1021FFFF (JE R1,R1,-1)
Reg ASel1
20Data A
1Reg CSel
Reg CLD
ALU MUX6 (Sub)ALU Ctrl
20Data B0ALU
12PC Adder
4 1 1 – 1Rs Rt Offset
4
8
1
1
2
10
20
10
PC Adder 2 8
Adder MUX
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Datapath OperationDatapath Operation
How Fast Can the Clock Be?
CLKPC
I-Mem8
Reg ASel
Data A
Reg CSel
Reg CLD
ALU MUXALU Ctrl
Data B
ALU
PC Adder
4
8
1
1
2
10
20
10
PC Adder 2Adder MUX
ƮM
ƮReg
ƮALU
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Datapath OperationDatapath Operation
How Fast Can the Clock Be?
CLKPC
I-Mem8
Reg ASel
Data A
Reg CSel
Reg CLD
ALU MUXALU Ctrl
Data B
ALU
PC Adder
4
8
1
1
2
10
20
10
PC Adder 2Adder MUX
ƮAdder
ƮAdder
Ʈclk
ƮReg
ƮALU
ƮM
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Single-Cycle ImplementationSingle-Cycle Implementation
Fetch Instruction
Decode Instruction
Get Operands
Execute it
CLKPC
I-Memi
8C640007 (LD R4,[R3+7])
35 3 4 7Rs Rt Address
Reg ASel 3
dData A
4Reg CSel
Reg CLD
ALU MUX
2 (Add)ALU Ctrl
Mem MUX
7Sign Ext
d+7ALU
vData CD-Mem v
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Single-Cycle ImplementationSingle-Cycle Implementation
Clock Speed? CLKPC
I-Memi
Reg ASel
Data A
Reg CSel
Reg CLD
ALU MUX
ALU Ctrl
Mem MUX
Sign Ext
ALU
Data CD-Mem
ƮM
ƮReg
ƮALU
Ʈclk
ƮReg
ƮM
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Single-Cycle ImplementationSingle-Cycle Implementation
Example:ƮM = 200 picosecondsƮALU = 100 picosecondsƮAdder = 100 picosecondsƮReg = 50 picoseconds
Fastest Clock?
MOV/ALU: Ʈclk > ƮM + 2 ƮReg + ƮALU
Conditional Jump:
Ʈclk > Max
ƮM + ƮReg + ƮALU
Load Memory: Ʈclk > 2 ƮM + 2 ƮReg + ƮALU
Store Memory: Ʈclk > 2 ƮM + ƮReg + ƮALU
Type Delay
MOV / ALU 400 ps
LD 600 ps
ST 550 ps
Cond. Jump 350 ps
Ʈclk = ps GHz
IT StudentsIT Students
Max + ƮAdder
ƮM
ƮAdder
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Multicycle ImplementationMulticycle Implementation
Instructions take different number of clock cycles
Functional units can be shared within the execution of a single instruction
IT StudentsIT Students
XX
YY
AL
UA
LU
MemoryMemory
Addr
DataData
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
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Multicycle ImplementationMulticycle Implementation
Some registers are not visible to the programmer
XX
YY
AL
UA
LU
MemoryMemory
Addr
DataData
4
SignSignExtendExtend
Shift Shift LeftLeft 2 2
Exercise: Can you do all the previous instruction here?IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
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Multicycle ImplementationMulticycle Implementation
Some registers are not visible to the programmer
XX
YY
AL
UA
LUAddr
Data
Data
4
SignSignExtendExtend
Shift Shift LeftLeft 2 2
0011
0011223300
11
001100
11
MemoryMemory
0011
IT StudentsIT Students
SelA
SelB
Sel C
LD
DataA
DataB
Register FileRegister File
Data C
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Multicycle Datapath OperationMulticycle Datapath Operation
Fetch Instruction CLKPC 0
ƮM
3401000A
Y MUX2 (Add)ALU Ctrl
PC MUX
X MUX
4ALUƮALU
0
IRLD
MemRd
PCLD
Ʈclk
1
IR
Mem Out
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Multicycle Datapath OperationMulticycle Datapath Operation
Fetch Instruction
Decode Instruction
Get Operands
CLKPC 4 0
2
3401000A (MOV R1, 10)
13 0 1 10Rs Rt Immediate
Reg ASel0
XLD
0Data A ƮReg
X
10Sign Ext
Ʈclk
IRLD
MemRd
IR
Mem Out
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Multicycle Datapath OperationMulticycle Datapath Operation
Fetch Instruction
Decode Instruction
Get Operands
Execute it
CLKPC 4
IR 3401000A (MOV R1, 10)
13 0 1 10Rs Rt Immediate
3
X 0
Y MUX
ALU Ctrl
X MUX
ALU
2
2 (Add)
10ƮALU
ResultLD
Result
Ʈclk
XLD
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Multicycle Datapath OperationMulticycle Datapath Operation
Fetch Instruction
Decode Instruction
Get Operands
Execute it
CLKPC 4
IR 3401000A (MOV R1, 10)
13 0 1 10Rs Rt Immediate
4
ResultLD
Result
Ʈclk
10
C MUXReg CLD
ƮReg
Ʈclk
Reg CSel 1
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Multicycle ImplementationMulticycle Implementation
Example:ƮM = 200 picosecondsƮALU = 100 picosecondsƮAdder = 100 picosecondsƮReg = 50 picoseconds
Fastest Clock?
Load Immediate/ALU: 4 Clocks
Load Memory: 5 Clocks
Store Memory: 4 Clocks
Type Instr. Mix
LI / ALU 52%
LD 25%
ST 10%
Cond. Jump 13%
Ʈclk = ps GHz
Conditional Jump: 3 Clocks
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Control ImplementationControl Implementation
Control Unit
CU
Data Processing Unit
DPU or Datapath
• •
••
• •
Datapath Control Signals:ALU Operation, MUX Selection,
Memory Rd/Wr, etc
Datapath Status Signals:IR Fields, ALU Flags
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Control ImplementationControl Implementation
Hardwired
● Standard Logic Components
● Fast
● Not Flexible, i.e. Difficult to Change Control Operation
Microprogrammed
● Memory-Based
● Speed Function of Memory (slower than hardwired)
● Flexible Design
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Control ImplementationControl Implementation
Hardwired
● FiniteStateMachine
State Register
• • •
• •
•
CombinationalControlLogic
• •
• Datapath Control Outputs
• • •
Datapath Control inputs
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Microprogrammed Control ImplementationMicroprogrammed Control Implementation
Each Linein the Micro-ProgramExecutesMicro-Operations(in 1 Clock)
Fetch,Decode,ExecuteCycle
ALU Operation, MUX Selection,Memory Rd/Wr, etc
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Microprogram Control UnitMicroprogram Control Unit
Datapath Control Signals:
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Microprogram Control UnitMicroprogram Control Unit
C19 C0
1
Opcode
Funct
ZCyetc
AdderAdder
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0
1
Microprogram Control UnitMicroprogram Control Unit
Fetch Instruction
μPC M0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
IR M[PC]PC PC + 4
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Microprogram Control UnitMicroprogram Control Unit
Decode / Get Operands
0 1 1 1 0 1 0 0 0 0 0 1 0
IR M[PC]PC PC + 4
0 0 0 0 0 1 0 0 1
X Reg[IR[25:21]]Y Reg[IR[20:16]]
Opcode = 0
Funct = 100010
= 8
IT StudentsIT Students
0
1
8
μPC M0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept.Dept.
5252 / 52 / 52
Microprogram Control UnitMicroprogram Control Unit
Execute Instruction IR M[PC]PC PC + 4
X Reg[IR[25:21]]Y Reg[IR[20:16]]
1 0 0
R X – Y
Opcode = 0
Funct = 100010
= 8
IT StudentsIT Students
0
1
8
9
μPC M0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
1 1 0 1 1 1 0 1 0 0 0 0 0 1 00 0 0 0 0 1 0 0 1
Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept.Dept.
5353 / 52 / 52
Microprogram Control UnitMicroprogram Control Unit
Execute Instruction IR M[PC]PC PC + 4
X Reg[IR[25:21]]Y Reg[IR[20:16]]
R X – Y
1 0 1 0 1 1 0 10 0 1 0 0 1 0 0 1
Reg[IR[15,11]] R
Opcode = 0
Funct = 100010
= 8
IT StudentsIT Students
0
1
8
9
μPC M0 S1 S0 C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
1 0 0 1 1 0 1 1 1 0 1 0 0 0 0 0 1 00 0 0 0 0 1 0 0 1
Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept.Dept.Chapter 4Chapter 4
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