or25vsd-low power vlsi circuits

Code No. OR-25/VSD JAWAHARLAL NEHRU TECHNOLOGY UNIVERSITY, HYDER

R M.Tech II Semester Supplementary Examinations, Marc

LOW POWER VLSI CIRCUITS (VLSI System Design)

Time: 3 hours Max. Marks.Answer any Five questions

All questions carry equal marks ---

1.a] Compare 5µ and 0.1 µ Technologies in all respects. b] With the help of neat sketches explain about shallow trench isolation c] Explain about hot corner effects. 2.a] Explain how modeling of BJ is done in SPICE.

b] Explain how the structure of BJT can be modeled to get characteristics.

3.a] Assuming typical values for various parameters of a logic circu

inverter lagic circuit internal to the device , to drive large capacitive b] Explain about low power CMOS circuit design techniques. 4.a] Explain about BICMOS dynamic logic circuits. b] What are the issues involved in charge sharing? How are they addres c] Explain about Novse problems in dynamic logic circuits. 5.a] Compare SRAMs and ∆ RAMs b] Give the structure and critically analyses the SOI memory devices. 6. Draw the carry-skip CLA circuit and explain its operation.

7. Explain about various steps in low power physical design. 8. Write notes on any TWO: a] Architectural level design b] PLAs c] Narrow channel effects.

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