new compensation techniques for integrated analog device issues · 2010. 4. 2. · 2007.09.20 ssdm...
Post on 24-Oct-2020
0 Views
Preview:
TRANSCRIPT
-
2007.09.20 SSDM A. Matsuzawa
1
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Compensation techniques for integrated analog device issues
Akira Matsuzawa
Department of Physical ElectronicsTokyo Institute of Technology
-
2007.09.20 SSDM A. Matsuzawa
2
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Contents• Integrated analog devices• VT mismatch compensations
– DAC– Comparator
• Capacitor mismatch compensation– Pipelined ADC
• 1/f noise– Chopper amplifier
• Mismatch and absolute value compensations in circuits– I/Q imbalance and image rejection– CT filter tuning– Calibrations in mixed signal SoC
• Conclusion
-
2007.09.20 SSDM A. Matsuzawa
3
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Integrated analog devices
Analog circuits need many passive devices, as well as transistors
MOSTransistor Resistor Capacitor Inductor
-
2007.09.20 SSDM A. Matsuzawa
4
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Characteristics of passive devices
Passive components has some imperfections
Good Q (RF)Cost up
High VCLow VCCost up
Low VCLow leak
Large VCLeak
Comment
0.0010.010.0050.01-0.050.05-0.2Voltage Coefficient(%/V)
0.0010.0020.0020.1-0.20.05-0.2Temperature Coefficient(%/deg C)
0.05-0.20.05-0.20.05-0.20.2-20.2-2Relative accuracy(3sigma; %)
5-102-55-101010Absolute accuracy (3sigma; %)
0.5-2fF/um2
2-5fF/um2
0.5-2 fF/um220-100 ohm20-100 ohmSheet R or C
MIMCapacitance
GateCapacitance
Poly to PolyCapacitanc
e
PolyResistance
DiffusionResistance
Good Q (RF)Cost up
High VCLow VCCost up
Low VCLow leak
Large VCLeak
Comment
0.0010.010.0050.01-0.050.05-0.2Voltage Coefficient(%/V)
0.0010.0020.0020.1-0.20.05-0.2Temperature Coefficient(%/deg C)
0.05-0.20.05-0.20.05-0.20.2-20.2-2Relative accuracy(3sigma; %)
5-102-55-101010Absolute accuracy (3sigma; %)
0.5-2fF/um2
2-5fF/um2
0.5-2 fF/um220-100 ohm20-100 ohmSheet R or C
MIMCapacitance
GateCapacitance
Poly to PolyCapacitanc
e
PolyResistance
DiffusionResistance
-
2007.09.20 SSDM A. Matsuzawa
5
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
VT mismatch
VT mismatch causes offset voltage of an amplifier and a comparator.Larger gate area is needed to reduce offset voltage, however results in decrease of performances, such as BW and PD.
LWTV oxT ∝∆
( )LWTV OXT
22 ∝∆
0.13um: Morifuji, et al., IEDM 20000.4um : My data
1 10 100 1 .1030.1
1
10
100
δVT LW( )0
δVT LW( )1
δVT LW( )2
LW
0.1
1
10
100
)mV(VT∆
)m(LW 2µ1 10 100 1000
0.4um Nch
0.13um Nch In w/o Halo*
0.13um Nch Boron, w. Halo
-
2007.09.20 SSDM A. Matsuzawa
6
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
VT fluctuations in a waferVT fluctuation for small device looks random in a wafer.VT fluctuation for large device have some gradients in a wafer.
23
45
67
89
10
3
4
5
6
7
8
9
10
0.54
0.55
0.56
0.57
0.58
0.59
0.60
VtnW/L=3.8/0.38
23
45
67
89
10
3
4
5
6
7
8
9
10
0.66
0.67
0.68
0.69
0.70
0.71
0.72
VtW/L=40/4
Vt =686±7mVVt =575±18mV
-
2007.09.20 SSDM A. Matsuzawa
7
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Influence of VT mismatch in current staring DAC
Higher resolution DAC requires smaller current mismatchwhich is mainly caused by VT mismatch.
0iI ∆+ 1iI ∆+ 2iI ∆+ 1N2iI −+ ∆
N2C2
1I
)I(≈
σ
N: resolution
C: Constant determined by INL yield
NII
21)( 2
∝⎟⎠⎞
⎜⎝⎛ σ
6 8 10 12 141 .10 3
0.01
0.1
sigma 3.0 N,( )
sigma 2 N,( )
sigma 1.3 N,( )
sigma 0.8 N,( )
N
90%50%
10%
99.7%
Van den Bosch,.. Kluwer 2004
INL yield
6 8 10 14
10
1
0.112
Cur
rent
mis
mat
ch (%
)
Resolution (bit)
-
2007.09.20 SSDM A. Matsuzawa
8
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Issue in high precision analog design
LargePower
dissipation
LargePower
dissipation
High precision analog circuit design conventionally results in increase of power dissipation and IP cost, decrease of frequency performance
Large capacitance
Expensivecost
Expensivecost
Highprecisioncircuits
Highprecisioncircuits
SmallmismatchSmall
mismatchLarge
Gate sizeLarge
Gate size
Large area
Lowcutoff
frequency
Lowcutoff
frequency
Large capacitance
-
2007.09.20 SSDM A. Matsuzawa
9
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Dynamic current compensation
Each current source can be set equal by current memory method.Shit register and one extra current source can realize calibration on the job.
VDD H.J. Schouwenaas, et al.,IEEE, JSC, vol.23, pp.1290-1297, Dec, 1988.
Shift register0 0 0 0 0 0 01
16bit DAC
Iref
Switch circuit
To D/A converter Current source under calibration
Iref
CAL: ONJOB: OFF
CAL JOB
Current memory
-
2007.09.20 SSDM A. Matsuzawa
10
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Self-Calibrated DACCAL-ADC measures non-linearity of DAC and compensates it’s non-linearity by CAL-DAC with logic
14bit 100MHz DAC
External ADC
Compensation circuitsY. Cong and R. L. Geiger, Iowa state university, ISSCC 2003
-
2007.09.20 SSDM A. Matsuzawa
11
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Effectiveness and issues of CAL-DACDigital calibration can reduce non-linearity dramatically.We can realize high precision DAC in small area and power dissipation.
However, unrealistic, because it needs high precision ADC!!INL DNL14bit DAC
+/- 9 LSB
+/- 0.4 LSB
+/- 5 LSB
+/- 0.35 LSB
Before
After
14b 100MS/s DAC 1.5V, 17mW, 0.1mm2, 0.13umSFDR=82dB at 0.9MHz, 62dB at 42.5MHz
Area: 1/50 Pd: 1/20
-
2007.09.20 SSDM A. Matsuzawa
12
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Self-Calibrated Binary DACWe have developed self-calibrated Binary DAC without CAL-ADC.Comparator can calibrate non-linearity. No high precision ADC is needed.
MSBARRAY
LSBARRAY
CALARRAY
SUBARRAY
6bit+1bit 8bit 3bit+1bit 6bit+1bit
CurrentMirrorARRAY
6bit+1bit
MSBSWITCH
LSBSWITCH
CALSWITCH
SUBSWITCH
ΔI CALLOGICMEMORY
Output
IMSB028ICMSB028
ILSB727
ILSB020
IMSB5213
VDD
6+1 8 3+1 6+1
MSBDAC LSBDAC CALDAC SUBDAC
MAINDAC
~ ~ICAL02-3ICCAL02-3
ICAL22-1
~ISUB02-3
ICSUB02-3
ISUB222
~ Y. Ikeda, A. Matsuzawa, "Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC", IEICE TRANS. ELECTRON, vol. E90-C, No.6, pp.1172-1180, June. 2007
0 5000 10000 15000-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
code
INL(
LSB
)
0 5000 10000 15000-8
-6
-4
-2
0
2
4
6
8
code
INL(
LSB
)
0 5000 10000 15000-4
-2
0
2
4
6
8
code
DN
L(LS
B)
0 5000 10000 15000-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
code
DN
L(LS
B)
+/- 6 LSB +/- 0.5 LSB
+/- 0.25 LSB
INL
DNL +/- 6 LSB
Comparator 14b DACBefore After
-
2007.09.20 SSDM A. Matsuzawa
13
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Error compensation by comparator
887654 21
21
21
21
21
21
++++=imi
nnmm +
=+ += ∑ 2
12
121
1
Nature of binary weighted values
NoI
21) Measure LSB value by CAL DAC with certain accuracy.
2) Measure the error of each current source by comparator with binary search .
RL
Vout
Main DAC
Cal DAC
2oI±
4oI± 12 −
± NoI
NoI
2± 12 +−
± jNoI
ijNoI+−± 222 +−
± jNoI
ijNoI+−± 2
Comparator
Logic
Data in
1414131212
14141313
1
2222'
222'
222'
oooo
ooo
No
mN
nnm
omo
m
IIIII
IIII
IIII
−−−=δ
−−=δ
−−=δ ∑−
=+
Example
3) Compensate the errors by digitally
-
2007.09.20 SSDM A. Matsuzawa
14
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Comparator and offset suppressionStore the offset voltage in capacitor and subtract it from the signal
Offset suppressionVoff at sigma reaches 30mVin CMOS comparator S1
-
+G
S2S3
Co
S1-
+G
S2
Ci
S3
vovin
vin
(a)
(b)
+
-
High gain type (feedback method)
Low gain type (feed forward method)
Va Vo
( )
osao
aoosa
VA
AVV
VV)A(VV
+=
==−−
=∴1
Basic CMOS comparator
-
2007.09.20 SSDM A. Matsuzawa
15
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Digital Comparator offset compensation
Offset voltage of latched comparator can’t be compensated by previous method.Because it has no bias point. In this case, digital method should be applied. Input terminals are shorted and the output signal controlsapplied voltage to the differential pair in CAL circuits so that the frequency of occurrence in differential output signals become equal.
Vin+ Vin-Vcom Vcom
Latched CMPLogic
Comp_out
CCAL Cs
CCAL Cs
Vmax
Vmin
Vmax
Vmin
CCAL=10 CsCAL circuits
I∆
I∆− I∆−
V∆
“A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC”Pedro M. Figueiredo, et al., ISSCC 2006
-
2007.09.20 SSDM A. Matsuzawa
16
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Capacitor mismatch in pipelined ADC
Cf
CompDAC
G
Cs
VinVo
VDAC
S1f
S1s
S2f
S2s
DACf
s
f
sino VC
CCCVV −⎟
⎟⎠
⎞⎜⎜⎝
⎛+≅ 1
NCC
21
<∆
)(
4102)(pFCC
C −×=σ
∆( )DACinf
f
s
so VVC
CCCV −⎟
⎟⎠
⎞⎜⎜⎝
⎛ ∆−
∆=∆
Capacitor mismatch in pipelined ADC determines the conversion accuracy. For the higher resolution, the larger capacitance is needed.
12 bit
10 bit
14 bit
12 bit
10 bit
14 bit
1
0.1
0.01
0.0010.1 1 10 100
Capacitance (pF)M
ism
atch
(%)
DACino VVV −≅ 2
-
2007.09.20 SSDM A. Matsuzawa
17
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Capacitor mismatch compensation
Capacitor mismatch causes the large conversion value differencesat the input voltage where the comparator changes the DAC voltage.
Compensation method:
1) Select input signal to +/- Vref/4
Vref
DOUT
-Vref -Vref/4
Vref/4
IDEAL
ACTUAL
CAL
0 0
0 1
1 0
VINδ1
δ2Vref
DOUT
-Vref -Vref/4
Vref/4
IDEAL
ACTUAL
CAL
0 0
0 1
1 0
VIN
Vref
DOUT
-Vref -Vref/4
Vref/4
IDEAL
ACTUAL
CAL
0 0
0 1
1 0
VINδ1
δ2
Cf
CompDAC
G
Cs
Vin
Vo
VDAC
S1f
S1s
S2f
S2s
+/- Vref/4
Logic
Scal
2) Convert this value with VDAC=0 and +/- Vref and obtain and .3) Add or subtract this to or from the output values
1δ 2δ
21,δδ
S. Y. Chung and T. L. Sculley,” A Digitally Self-Calibrating 14-bit 10MHz CMOS Pipelined A/D Converter.” IEEE, JSC, Vol. 37, No.6, pp. 674-683, June 2002.
-
2007.09.20 SSDM A. Matsuzawa
18
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
1/fノイズ
fWLCKS
oxVG
1⋅=∆
Gate Oxide Gate Oxide
Si SiTrap Trap
1/f noise degrades SNR of base-band signal seriously.The 1/f noise from MOS is one or two order of magnitude higher than bipolar.The larger gate area is needed to reduction this noise.
Dra
in c
urre
nttime
-
2007.09.20 SSDM A. Matsuzawa
19
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Chopper amplifierChopper technique is often to be used to reduce the effect of 1/f noise.
-
+ +
-
+Vn
-Vn
GVin
Φs Φs
Vout
( )sNinsoddn
nNout nffSnffGn
fS −−⎟⎠⎞
⎜⎝⎛π
= ∑∞
−∞=
2
:
2
2
)(12)(
Signal Signal + Noise Signal is reconstructedNoise is filtered out
Signal
1/f noise
1/f noise
Signal
Chopped noise
Signal Chopper freq.LPF
C. C. Enz, E. A. Vittoz, and F. Krummenacher, IEEE Journal of Solid-State Circuits, Vol. 22, No. 3, pp. 335-342, June 1987 Chopper freq.=1KHz
W/ chopper
W/O chopper
-
2007.09.20 SSDM A. Matsuzawa
20
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Image-rejection mixersImage can be rejected theoretically. However, the image still remains due to gain and phase mismatch.
( )tLOωcos
LPF
+
LPF
Vin (t) Vout(t)( )tLOωsin
°90
LOω ωimωdesω
Image rejection mixerω
IFω IFω
0
IFω
IFω
Input
Output
Desired ImageV1 V3
V2
( ) ( )
( ) ( )tVtVtV
tVtVtV
imLOim
LOdesdes
imLOim
LOdesdes
ω−ω+ω−ω=
ω−ω+ω−ω−=
cos2
cos2
)(
sin2
sin2
)(
2
1
( ) ( )
( )tVtV
tVtVtVshifttV
LOdesdesout
imLOim
LOdesdes
ω−ω=
ω−ω−ω−ω==°→
cos)(
cos2
cos2
)(90)( 31
Image is rejected, however,…
-
2007.09.20 SSDM A. Matsuzawa
21
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Gain mismatch and phase error
It is very difficult to realize high image rejection rationbeing higher than 40 dB by analog techniques.
A. Rofougaran, et al., IEEE J.S.C. Vol.33, No.4, April 1998. PP. 515-534.
( )
4
22
θ∆+⎟⎠⎞
⎜⎝⎛ ∆
≈ GG
IRR
0.1 deg and 0.01% are needed for IRR of 60dBConventional IRR: 35dB IRR: Image rejection ratio
-
2007.09.20 SSDM A. Matsuzawa
22
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Digital image rejection technique
ADCVGA+FilterMIXERLNA
FMI
The dummy image signal is generated by IMO and the controller controls signal delay and amplitude on Q path to minimize the I/Q imbalance. IRR of 60dB can be realized.
Q
Deci.LPF
Vari.Delay
Vari.Gain BPF
IMO Controller
Deci.LPF
Fixed.Delay BPF
DSP
to DSP
Image Rejection Ratio >60dB
Image frequency oscillator
From ADCsIM detect
-
2007.09.20 SSDM A. Matsuzawa
23
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
CT filter tuningRC or gmC circuits can realize active filter circuits,However, frequency characteristics and Q of the filter are strongly affected byAbsolute value of R, C, gm and PVT fluctuation.Then, the filter tuning circuit is vital.Filter circuit can be used as oscillator, if the Q become infinity.
DummyOscillator
Filter
Peak DetectorPLL
go go
gm cont. go cont.
gm
gm
Q tuningfrequency tuning
Ref clock
-
2007.09.20 SSDM A. Matsuzawa
24
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Digital calibration in mixed signal SoCTo keep high production yield and stable operation against PVT fluctuation,mixed signal SoC has many digital self calibration circuits.MCU controls many analog parameters.
PRML circuit for DVD recorder
Ana
log
Buf
fers
OffsetAdjustVGA
5th orderGm-C Filter
DAC
DAC
7bitADC
OffsetControl
Defect
WobbleFilter
Frequency&
PhaseComparator
FIRFilter
LMS
ViterbiDetector
LoopFilters
DACs
VCO
ClockControlSystem
Clocks
1/N
LevelDetector
ExtractedData
WobbleDetect
Pick upOutputs
ExtractedClock
…
ServoPre-Processor
Servo Error Signals
GainControlDefectDetect
[RF input] [Analog Filter output]
[FIR output]digitalcontrol
...
DigitalCalibration
-
2007.09.20 SSDM A. Matsuzawa
25
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Issues of analog compensation techniques
• Basically use discrete-time technology– Difficult to apply Continuous-Time circuits.– Needed clock causes another noise.
• Some need calibration period– At power on
• Needs not short time to wait the system becomes stable.• Some different situation at the power on.
– Idling time on the job• Can get sufficient time for calibration?• Too much system depended.
• Calibration on the job– Conventionally needs extra circuits.
Cost and power consumption increase.– Needs many calibration time, if statistical methods are used.
-
2007.09.20 SSDM A. Matsuzawa
26
Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.
Conclusion
• Analog circuits require compensation technique– Mismatch is inversely proportional to the square root of area.
– Control of absolute vale of device parameters is difficult.– Also, device parameters are affected PVT fluctuation easily.– If not use of compensation techniques
• Large area, large power consumption, poor frequency performance.
• Compensation techniques are very effective to improve precision of circuits, production yield, and durability to PVT fluctuations
• However, they have many issues– Basically DT method are used and difficult to apply CT circuits.– Need calibration periods
SRR
CCVV fnT
1,,, /1_ ∝⎟⎠⎞
⎜⎝⎛ ∆
⎟⎠⎞
⎜⎝⎛ ∆∆
Compensation techniques for integrated analog device issuesContentsIntegrated analog devicesCharacteristics of passive devicesVT mismatchVT fluctuations in a waferInfluence of VT mismatch in current staring DACIssue in high precision analog designDynamic current compensationSelf-Calibrated DACEffectiveness and issues of CAL-DACSelf-Calibrated Binary DACError compensation by comparatorComparator and offset suppressionDigital Comparator offset compensationCapacitor mismatch in pipelined ADCCapacitor mismatch compensation1/fノイズChopper amplifierImage-rejection mixersGain mismatch and phase errorDigital image rejection techniqueCT filter tuningDigital calibration in mixed signal SoCIssues of analog compensation techniquesConclusion
top related