a 0.114-mw dual-conduction class-c cmos vco …...a 0.114-mw dual-conduction class-c cmos vco with...
TRANSCRIPT
A 0.114-mW Dual-Conduction Class-C CMOS VCO
with 0.2-V Power Supply
K. Okada, Y. Nomiyama,
R. Murakami, and A. Matsuzawa
Tokyo Institute of Technology, Japan
2009/6/18, VLSI Circuits, Kyoto
Outline of Presentation
• Motivation
– Supply voltage scaling
– Jitter degradation
• Low-voltage VCO’s issues
• The proposed Dual-Conduction topology
– Low-power and Low-phase noise
with a very low supply voltage
• Measurement results
• Conclusions
Supply Voltage Roadmap
The voltage scaling is required again.
Low-voltage circuit design is challenging.
0
0.5
1
1.5
1999 2004 2009 2014 2019
Vd
d [
V]
Year
ITRS2000
ITRS2008
Leakage current
& Process fluctuation
Phase Noise Comparison
LC-VCO
2
0
2 2
1
offsetDD bias
nkT
V I Q
2
0
22 ( ) 1
offset
DD
DD bias DD TH
n p
VkTM
V I V V
Ring-VCO
M: #stages2
, , 3, 104 3
DD
TH n p
VV M Q
+30dB worse
[A.Mazzanti, et al., JSSC 2008]
[A.Abidi, JSSC 2006]
Jitter Scaling
2007 2010 2013 2016 2019 2022
Year
Ring-VCO
LC-VCO
31.6x
15
10
5
0
Clock
6J
itte
r/C
loc
k [
%]
Clo
ck
[G
Hz]
15
10
5
0
With the same power consumption, LC-VCO has much smaller jitter performance.
Vdd=0.7V
Clock Generation with Low Vdd
• Lowering of supply voltage is required to
realize high-speed and low-active-power
circuits.
• Jitter will become larger according to the
voltage scaling.
• Ring-VCO become infeasible due to too large
jitter or too large power consumption.
• To reduce the power consumption of the clock
generator, use of LC-VCOs is an unavoidable
way in such the low-voltage condition.
Low-Voltage LC-VCO
• Transformer-Feedback VCO can operate
with a low supply voltage.
• 0.5V and 0.35V VCOs are reported.
[1] K. Kwok, and H. C. Luong, JSSC 2005
• Class-C VCO archives 196dBc/Hz of
FoM.
• Startup is an issue of Class-C VCO
under the low-voltage condition.
[2] A. Mazzanti, and P. Andreani, JSSC 2008
Summary of This Work
• Sub-0.5V LSI
• A Dual-Conduction topology is proposed
for Class-C VCO in this work.
• It is modified to work with a very low
supply voltage.
• 0.2V VCO is realized by using a 0.18 m
CMOS process with 114 W of power
consumption.
Impulse Sensitivity Function (ISF)
Phase is NOT shifted
Phase is shifted
[3] A.Hajimiri, and T.Lee, JSSC 1998
ISF0
Case 1
Case 2
Voltage
Waveform
Ideal Current Conduction
0
ISF0
Ideal Current
0t
p n p n pConventional
LC-VCO
Current Conduction of Class-C VCOs
Ideal Current
0
0
p n p n pClass-C VCO
ISF0
Current Conduction of Class-C VCOs
0
p n p n pClass-C VCO
0
p n p n pDual-Conduction
Class-C VCO
(This work)
ISF0
Class-C VCO[2]
VDD
Vgbias
L
C
Ibias Ctail
InIp
0
0
Veff =Vgs –Vth
I
0
p p p
0
In n
t
t
t
t
Class-C VCO
[2] A. Mazzanti, et al.,
JSSC 2008
p n p n p
Conventional LC-VCO
Veff =Vgs –Vth
Condition for Class-C Operation
VDD
Veff
=Vgs –Vth
Vds
0
0 /2- /2-
[rad.]
-Vod
=Vgbias –Vth
Active region: Vds > Veff
Vod
Issue of Class-C VCO for Low Vdd
VDD
0
0 /2- /2-
[rad.]Vod has to be small due to the start-up problem,
so conduction angle cannot be reduced.
Veff
=Vgs –Vth
Vds
Vod-Vod
=Vgbias –Vth
Dual-Conduction Class-C VCO
(Proposed)VDD
Vod1>0 Vod2 0
L
C
Ids1 Ids2
for start-upfor Class-C operation
Dual-Conduction Current Waveform
Ids1+Ids2Dual Conduction
(proposed)
0 /2- /2- [rad]
Ids1
Vod1=0.12V ( 1=0.2 )
Vod2=0V ( 2=0.5 )
Ids2
Comparison of Current Waveforms
Ids1+Ids2Dual Conduction
(proposed)
Single Conduction
(conventional)
Dual Conduction realizes
a narrower current waveform.
0 /2- /2- [rad]
=0.5 & 0.2
0=0.4
Analytical Comparison
Vod=0.05V ( 0=0.4 )
PN: -106dBc/Hz-1MHz
Pdc: 168 W
FoM: 188dBc/Hz
Vod1=0.12V ( 1=0.2 )
Vod2=0V ( 2=0.5 )
PN: -109dBc/Hz-1MHz
Pdc: 162 W
FoM: 191dBc/Hz
( ) Vdd=0.2V, A=0.15V, Vth=0.5V, f0=5GHz, Q=10
Dual Conduction
(proposed)
Single Conduction
(conventional)
Chip Micrograph
• 0.18 m CMOS process
• 670 m x 440 m for core area
core area
I/O buffer
Phase Noise Measurement
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
10k 100k 1M 10M
Offset Frequency [Hz]
Ph
ase N
ois
e [
dB
c/H
z]
Vdd=0.2V
Vdd=0.3V
-104dBc/Hz@1MHz for 0.2V-109dBc/Hz@1MHz for 0.3V
Vgbias1=0.45, Vgbias2=0.55
f0=4.5GHz
Performance Comparison
[2] [1] This work
Technology0.13 m
CMOS
0.18 m
CMOS
0.18 m
CMOS0.18 m CMOS
Vdd [V] 1.0 0.5 0.35 0.3 0.2
PDC [mW] 1.3 0.57 1.46 0.159 0.114
f0 [GHz] 4.9 3.8 1.4 4.5 4.5
Phase noise
[dBc/Hz]
-130
@3MHz
-119
@1MHz
-129
@1MHz
-109
@1MHz
-104
@1MHz
FoM [dBc/Hz] 196 193 190 190 187
TopologyClass-C
(single)
Transformer
feedbackClass-C (dual)
[1] K. Kwok, et al., JSSC 2005 [2] A. Mazzanti, et al., JSSC 2008
Conclusion
• A 0.2V LC-VCO is realized by using a dual-
conduction Class-C topology, which has a
smaller conduction angle than the conventional
Class-C VCO under the low supply voltage
condition.
• The significance of this work is improvement of
FoM for the low-voltage oscillators.
• A low-jitter and low-power clock generator can
be realized.
• Bias generation is a remaining issue.