low voltage power mosfet_final

- Jinrong Liu- Somsubhra Ghosh- Ramya Hemant- Yukui Luo

Low Voltage Power MOSFET

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Overview1 Trench MOSFET2 NexFET3 “Rad-Hard” MOSFET4 LV Super-Junction5 Refrences

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Trench MOSFET-Yukui Luo

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History of Trench-MOSFET development

• Timeline of Trench-MOSFET

… ...1993

First Trench-MOSFET

Siliconixintroduces industry-first

POWER MOSFETsBase on Trench Technology

2000Trench-MOSFET version II

2009TrenchFET Gen III

VishayDevelop the TrenchFET Gen III

2015TrenchFET Gen IV2005

Siliconix becomes a wholly owned subsidiary of Vishay

Developing TrenchFETTrenchFET version II

2015

TINexFET

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FOM(Figure of Merit)

FOM factors to benchmark MOSFET products

FOM = Rds(on) *Qgd

[13]

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The structure of VDMOS and Trench-MOSFET

Fig. VDMOS structure[13]Fig.Trench-MOSFET structure[13]

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Pitching current(JFET effect)

Thicker N epitaxial layerHigher Breakdown voltage

Large Cgd

Fig. VDMOS structure[13]

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VDMOS-vertical double diffused MOSFET

• Improve the current capability of the power MOSFET

• Advantage• High breakdown voltage.• Large Current Density.

• Disadvantage• JFET effect• Large Cgd

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Trench-MOSFET• Advantage:

• Low Rds(on)

As for VDMOS, Rds(on) = R(Source diffusion resistance) + R(Channel resistance) + R(Accumulation resistance) + R(JFET

component-resistance) + R(drift region resistance) + R(substrate

resistance) + R(wire resistance)

Removed JFET implies no R(JFET component-resistance). And it is easy to make cell pitch smaller.

• Disadvantage:• Large value of built-in capacitors• Large capacitance from gate-to-

drain (Cgd).

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Cbuild-in Cgd

No JFET structureGenerate the advantage of VDMOS High Breakdown Voltage

Large value of built-in capacitorsLarge capacitance from gate-to-drain

Fig.Trench-MOSFET structure[13]

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Trench-MOSFET – Versions

Thick oxide[15]Shielding Effect[15]

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The latest trench technology - TRENCHFET® GEN IV

Latest Trench-MOSFET Vishay TrenchFET Gen IV

Package(small to large) Configuration VDS (V) RDS(on) @ 4.5 V

(mΩ)Qgd (nC) ID Max.

(A)

PowerPAIR 3 x 3 N-type DUAL 30 Min 7-Max 13.8 Max 1.8-Min 0.7 30

ThinPower PAK1212-8 N-type SINGLE 30 12 1.6 38.3

PowerPAK1212-8 N-type SINGLE 30 Min 3.1-Max 12.5

Max 4-Min 1.6 20-40

So-8 N-type SINGLE 30 4.4 4 31.3

PowerPaKSo-8 N-type SINGLE 30, 40,60

Min 1.35-Max 13.5

Max 8.6-Min 1.6 20-100

PowerPAIR 6 x 5skyFET

N-type DUAL PLUS INTEGRATED SCHOTTKY 30 Min 1.75-Max

10Max 5-Min

0.75 16-60

D2PAK(TO-263) N-type SINGLE 60 2.6 7.1 120TO-220 N-type SINGLE 60 2.8 7.1 120

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NexFET-Jinrong Liu

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Lateral Double Diffused MOSFET (LDMOS)

Fig. Lateral MOSFET structure representing the channel region under very small drain bias voltages[9]

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Fig. Lateral MOSFET structure representing the channel region under channel pinch-off conditions and above channel pinch-off conditions[9]

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NexFET• Cons• The Trench-FET channel density is very high, leading to low

channel resistance. But the direct overlap of gate to drain results in large Cgd, slowing down the switching speed, leading to high switching loss.

• Pros• NexFET can reduce parasitic capacitances Cgd and Cgs, while

achieving similar specific RDS(ON), like in the Trench-FET technology.

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The improvement from NexFET• The gate has the minimum overlap with source

and drain regions and effectively shielded by the source metal.

• Low resistivity polycide gate material – reduced gate resistance.

• Thick top reduces the metal resistance and prevents electro-migration effects.

• The gate portions are minimized which reduce Cgs and Cgd values.

• The field plate introduces a shielding effect which reduces Cgd

• Shield effect helps to push the electric field distribution towards the drain sinker. Fig. Schematic cross-section of the first

generation NexFET[10]

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• The current flow pass through the lateral channel into the substrate.

• A heavily-doped drain sinker helps to direct the current flow reach drain.

• Vertical current flow makes this device suitable for carrying high current density.

• The heavily doped drain sinker region is very helpful to achieve smaller resistance in chip scale parts than conventional VDMOSFET.

Fig. Drain Down (right) NexFET Power MOSFETs[11]

The Current Flow Of NexFET

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Regions to support breakdown• The one is the underneath of

the source contact• Another one is along the

LDD, N-epitaxial layer and sinker region.

Fig. Schematic cross-section of the new low voltage NexFET[12]

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• Current flows through the following path,• Source Terminal on the

substrate• Vertical Sinker• Metallization layer• N+ Source Region

• Forwarded to drain terminal by the LDD region.

Fig. Source Down (right) NexFET Power MOSFETs[11]

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Stack-Die Technique• Stack-die Power Module Package

technique reduces the parasitic inductance and resistance

• Structure of Stack-Die:

• Integration of high-side (HS) and low-side (LS) transistors.

• Thick copper clips • high-current connections such as

input and switching node terminals• Substantially reduces the RDS(ON) of

the power block. Fig. SEM image of NexFET Power Block[11]

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Comparative Simulation – Switch On

Trench FET

NexFET

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Comparative Simulation – Switch Off

Trench FET

NexFET

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“Rad-Hard” MOSFET -Somsubhra Ghosh

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Rad-Hard MOSFETRadiation hardened or “Rad-Hard” MOSFETs are enhanced Field Effective Transistors to withstand the effects of Radiation.

©Infinion, 100 Krad TID

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Radiation• Terrestrial• Emissions from Nuclear Reactors.• Emissions from Nuclear Core Enrichment process• Fusion reactors.

• Extra Terrestrial• Solar radiation.

• Primarily Solar Heavy Ion emissions in Van Allen Belts.(~7 MeV - GeV)[1][2].

• Galactic Cosmic Rays (GCR)• Primarily heavy bursts of protons (~10s of TeV)[2]

©K. Endo, Prof. Yohsuke Kamide

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Radiation Effects - Failures• Total Ionizing Dose (TID)

• Total amount of radiation energy imparted to the electronic device.

• TID CMOS structure vulnerability effects• Change in Threshold Voltage (Vth tox

2)• Sub threshold leakage current.

• Single Event Effects (SEE) – device status altering events.• Single Event Upsets (SEU) - Heavy ion induced leakage

current turning on the self sustaining parasitic BJT• Single Event Transients (SET) – Reversible transient

glitch in combinational logic caused by excessive charge formation

• Single Event Gate Rupture (SEGR) – Electrically overstressed gate.

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Effects of Radiation-on VDMOSFET• Semiconductor Material (Lattice

Displacement)• Penetrating heavy ions create ehps in the

semiconductor through transfer of energy or Coulomb Scattering[4] and Compton scattering[4].

• Redistribution of Electric field - ‘Funneling Effect’ to maintain charge neutrality easier with higher electron mobility (1350 cm2/V-s)[3].

• Gate MO (Ionization)• Lower hole mobility (~10-4-10-11)[3]

• Trapped charges at various energy levels moving towards SiO2-Si interface.

• MOSFET Drain is shorted to the base – parasitic transistor is turned on.

N- Epi

Poly Gate

N+

N+P+ N+ P+P-+ -+ -+ -

+ -+ -+ -

P-

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Effects of Radiation-on P-LDMOSFET• Advantage over VDMOS• Benefits from the same

layer position of the Gate, Base and Drain.• Lower gate charge – higher

switching frequency (up to 1-2 GHz)[5]

• Compatible with TID hardened CMOS fabrication process.

P-Epi

P+

SiO2

Poly Si

LDD N+P+ N+

P-Body

Source

Gate

Drain

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TID Effects

© A J Womac, “The Characterization of a CMOS Radiation Hardened-by-Design Circuit Technique”

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SEB Simulation

© M Landowski “Design and modeling of radiation hardened lateral power mosfets”

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Radiation Hardening• Hardening process• Hardened by Design (HBD) – provides better cost to

performance.-Combines current CMOS intrinsic hardness along with special transistor design technology• Layout Level enhancement Technologies• Circuit Level enhancement Technologies

• Hardening by Process (HBP)• Hard reset by watchdog timer• Redundant circuits

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Layout Level Enhancement – Removal of Edge Leakage Current

• Annular gate/Enclosed Gate Transistor• Thin gate MO removes threshold voltage shifts. But

due to Ionizing radiation, the positive charge trapping gives rise to various leakage current from drain source.

• Also, the presence of gate MO between transistors provides path for intertransistional current that can be eliminated by enclosing the gate with drain or source.[6][7]

• Enclosed Source Transistor• Removal of leakage current by removing the edge.

• H Gate Transistor• Dog Bone Transistor [8]

[6]

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Circuit level Enhancement• Redundant circuits

• P1 and N1 works as a typical inverter when Vi is ‘high’. And when Vi is ‘low’ the additional circuit output is high, and N1 has a negative VGS. This ensures the transistor is fully turned-off reducing leakage current.

[1]

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Low Voltage Super-Junction

-Ramya Hemant

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Super-Junction Technology• Super-Junction• Long P Type Pillars.• Charge balancing mechanism• High Breakdown Voltage

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Benefits of Super-Junction• Low RDS(on) and switching loss.• Higher Breakdown Voltage for the same die size due to

more distributed electric field.• Faster Switching due to smaller lightly doped region.

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Low Voltage Super-Junction - Challenges

• Resistance of lightly doped region is very small for low voltages.• So, low voltage super

junction is not very effective for reducing RDS(ON).

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Low Voltage Super-Junction – nextPower MOSFET• Combines the benefits of a

LMOS with that of a Trench MOS.• Less cell density unlike Trench

MOSFET• Low Qg and low QGD, Cout

• Better Safe Operating Area.• Low RDS(on).

[16]

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Low Voltage Super-Junction – nextPower MOSFET• Higher Efficiency

[16]

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Overall Performance

[16]

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Application• DC-DC Conversion• Low Voltage isolated power supply topologies

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References1. A. J. Womac “The Characterization of a CMOS Radiation Hardened by Design Circuit Technique”,

Master’s Thesis, University of Tennessee, Knoxville, 20132. M. M. Landowski “Design and Modeling of Radiation Hardened lateral Power MosFETs”, Master’s

Thesis, University of Central Florida, 20083. D. A. Neamen, “Semiconductor Physics and Devices: Basic Principles”, 4th ed., New York, NY:

McGraw-Hill, 2012.4. R. Lacoe, "CMOS Scaling, Design Principles and Hardening-by-Design Methodologies”, in IEEE

NSREC, Monterey, 2003.5. A. A. Tanany “A Study of Switched Mode Power Amplifiers using LDMOS”, Master’s Thesis,

University of Gavle, 2007.6. L. Zhi, N. Hongying, Y. Hongbo, L. Youbao “Design of a total-dose radiation hardened monolithic

CMOS DC–DC boost converter”, Journal of Semiconductors, Vol. 32, No. 7, pp. 075006-1 – 075006-6, Jul 2011.

7. L. J. Bissey, K. G. Duesman, W. M. Farnworth “Annular gate and technique for fabricating an annular gate”, United States Patent, No. US 6,794,699 B2, Sept. 2004.

8. J. D. Cressier, H. A. Mantooth, “Extreme Environment Electronics”, CRC Press

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References9. B. J Baliga “Fundamentals of Power Semiconductor Devices”, Power Semiconductor Research

Center North Carolina State University, USA10. J. Wang, J. Korec, S. Xu, “Low Voltage NexFET with Record Low Figure of Merit”, Texas

Instruments Incorporated, Power Stage BU Bethlehem, PA, USA11. B. Yang, et.al, “NexFET Generation 2, New Way to Power”, Texas Instruments Incorporated12. J. Wang, J. Korec, S. Xu, ”Low Voltage NexFET with Record Low Figure of Merit”, Texas

Instruments Incorporated, Power Stage BU, Bethlehem, PA, USA13. J. Korec “Low Voltage Power MOSFETs – Design, Performance and Applications”, Vol. 7, Springer,

ISBN: 978-1-4419-9319-9, 201114. J. Korec, C. Bull “History of FET technology and the Move to NexFETTM”, Bodo’s Power system,

May 2009, pp. 44-46.15. S. Sapp, R. Sodhi, S. Sekhawat, “New Power Semiconductors Cut Data Center Energy”, Fairchild

Semiconductors, Oct. 2009.16. P. Rutter, S. T. Peake “Low Voltage Superjunction Power MOSFET: An Application Optimized

Technology ”, 26th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2011, pp. 491 – 497.

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Thank You