low cost tdc using fpga logic cell delay

Low Cost TDC Using FPGA Logic Cell Delay

Jinyuan Wu, Z. Shi

For CKM Collaboration

Jan. 2003

Introduction

PMThit

Q ADC/

QIE FPGACOM

PORTTDC

Need TDC

Low cost

FPGA

Low Cost FPGA

• Companies maintain low cost product lines.– Altera: ACEX 1K ($11.50 -- $31.50).– Xilinx: Spartan-IIE ($17.50 -- $26.50).

• The low cost devices have enough logic cells and RAM for data packing, etc.

• TDC can be implemented using internal chain structure. (This is not as good as DESER, but is available today).

• Use digital method to do compensation.

TDC Using FPGA Logic Chain Delay

• This scheme uses current FPGA technology

• Low cost chip family can be used. (e.g. EP1K10QC208-2 $15.25)

• Chain structure exists in Altera ACEX, Xilinx Spartan families.

IN

CLK

Problem 1: Logic Cell Delay Time Difference

• Delay times in different logic paths are different.

• The FPGA compiler is not easy to control. -- The logic path is not easy to predict.

• Solution: use chain structure in the FPGA.

• There are many type of chain structures: cascade chain, carry chain, sum of product chain, BY – YB chain, etc.

Problem 2: Delay Time Change With Temperature

• Delay time changes with temperature and power supply voltage.

• In DESER or TMC, the delay time of the delay chain is compensated by adjusting relevant voltages. – Analog compensation.

• In FPGA, digital compensation is needed.

• Digital compensation uses delay speed measured in the same delay chain to correct the arrival time of a hit.

Delay Chain Digital Compensation

IN

CLK

• Cell delay is not easy to adjust with analog methods.

• Digital compensation is needed:– Use longer delay line.

– Some signals may be registered twice.

N2-N1=(1/f)/t

• The two measurements can be used:– to calibrate the delay.

– to reduce digitization errors.

A Test Implementation

• Chip: Altera ACEX, EP1K10QC208-1 ($22.50) on the COMADC board.

• Clock: 35 MHz external (to fit QIE test readout), 70 MHz inside the chip.

• Digitization error: 0.4 ns/LSB, (too good. The chip is too fast).

• Jitter: < 1 LSB.

The Board and the Chip

The Core Part of the Chip

Delay Chain

Altera “cascade”

chain

Register Array

Compiled Resource Map

Delay Chain and Register Array (48 Steps)

Logic Analyzer Output (1)

Input

Hit Pattern in Delay Chain

TDC OK

TDC Value

Logic Analyzer Output (2)Different

Input

Time

Different Hit Pattern

TDC OK

Different TDC Value

Logic Analyzer Output (3)Some

Signals

…

… can be seen 2 times… … generating 2 TDC values.

Test Results: Raw Data

• Power supply voltage changed to create variation of the delay.

• V = 2.5 to 1.8V: the change is very big.

• 30% cell delay variation is seen.

TDC Output at Different PS Voltage

0

5

10

15

20

25

1.5 2 2.5

VCCINT (V)

TD

C O

utp

uts

N1

n2

2nd TDC

1st TDC

Effect of Digital Compensation

• Without compensation, 2.5ns error is seen.

• With compensations, error reduced to <1ns.

Time Measurement with and without Digital Compensation

6.00

7.00

8.00

9.00

10.00

1.5 2 2.5

VCCINT (V)

tao (

ns)

tao

tao3

t0

Two Compensation Methods

• Method 1: (tao) allows divisions. It is suitable for offline compensation.

• Method 2: (tao3) uses Taylor expansion to avoid divisions. It is suitable for FPGA hardware.

Time Measurement with Digital Compensation

8.75

9.00

9.25

9.50

9.75

1.5 2 2.5

VCCINT (V)

tao

(ns) tao

tao3

0.5 ns

To Do

• Use slower chip: EP1K10QC208-2 ($15.25) to repeat the study.

• Implement hardware compensation algorithm in the chip.

• Hook up to QIE test readout system to study random signal performance.

• Documentation.

The End

Thanks