lecture 03 - deep submicron (dsm) cmos technology · lecture 03 - deep submicron (dsm) cmos...
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Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-1
CMOS Analog Circuit Design © P.E. Allen - 2016
LECTURE 03 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY
LECTURE ORGANIZATION
Outline
• Characteristics of a deep submicron CMOS technology
• Typical deep submicron CMOS technology
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
New material
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-2
CMOS Analog Circuit Design © P.E. Allen - 2016
CHARACTERISTICS OF A DEEP SUBMICRON CMOS TECHNOLOGY
Isolation of Transistors
The use of reverse bias pn junctions to isolate transistors becomes impractical as the
transistor sizes decrease.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-3
CMOS Analog Circuit Design © P.E. Allen - 2016
Use of Shallow Trench Isolation Technology
Shallow trench isolation (STI) allows closer spacing of transistors by eliminating the
depletion region at the surface.
p+ p p- MetalSaliciden- n n+Oxide Poly
070330-03
PolycideGate Ox
n+
n-well
n+
p-well
n+
Substrate
n+
Shallow
Trench
Isolation
n+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p+p+ n+n+
Substrate Salicide
Well Salicide Decreased
spacing
Substrate Salicide
Sha
llow
Trench Isolation
Isol
atio
n
Sha
llow
Tre
nch
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-4
CMOS Analog Circuit Design © P.E. Allen - 2016
Comparison of STI and LOCOS
What are the differences between a LOCOS and STI technology?
Comments:
• If the n+ to p+ spacing is large, the Bird’s beak can be compensated using techniques
such as poly buffered LOCOS
• At some point as the n+ to p+ spacing gets smaller, the restricted bird’s beak leads to
undesirable stress effects in the transistor.
• An important advantage of STI is that it minimizes the heat cycle needed for n+ or p+
isolation compared to LOCOS. This is a significant advantage for any process where
there are implants before STI.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-5
CMOS Analog Circuit Design © P.E. Allen - 2016
Shallow Trench Isolation (STI)
060203-01
Nitride
Silicon(1)
(2)
(3)
(4)
(5)
(6)
1.) Cover the wafer with pad oxide and silicon nitride.
2.) First etch nitride and pad oxide. Next, an anisotropic
etch is made in the silicon to a depth of 0.4 to 0.5 microns.
3.) Grow a thin thermal oxide layer on the trench walls.
4.) A CVD dielectric film is used to fill the trench.
5.) A chemical mechanical polishing (CMP) step is used to
polish back the dielectric layer until the nitride is reached.
The nitride acts like a CMP stop layer.
6.) Densify the dielectric material at 900°C and strip the
nitride and pad oxide.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-6
CMOS Analog Circuit Design © P.E. Allen - 2016
Illustration of a Deep Submicron (DSM) CMOS Technology
In addition to NMOS and PMOS transistors, the technology provides:
1.) A deep n-well that can be utilized to reduce substrate noise coupling.
2.) A MOS varactor that can serve in VCOs
3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.
n+
p-substrate
Metal Layers
NMOS
Transistor
PMOS
Transistor
031211-02
M1M2M3M4M5M6M7
M80.8mm
0.3mm7mm
Deep n-wellDeep p-well
n+
STI
p+ p+
STI STI
Salicide
Polycide
Salicide
PolycideSidewall Spacers
Salicide
Source/drain
extensionsSource/drain
extensions
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-7
CMOS Analog Circuit Design © P.E. Allen - 2016
Transistors
fT as a function of gate-source overdrive, VGS-VT (0.13µm):
The upper frequency limit of the transistors varies with overdrive and process corners.
The NMOS transistor has an fT of 40GHz at low overdrives and increases to above
60GHz at the slow-high temperature corner with 0.5V overdrive.
100 200 300 400 500
20
30
40
50
60
70
10
00
Typical, 25°C
Slow, 70°CPMOS
Typical, 25°C
Slow, 70°CNMOS
f T (
GH
z)
|VGS-VT| (mV) 030901-07
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-8
CMOS Analog Circuit Design © P.E. Allen - 2016
Resistors
1.) Diffused and/or implanted resistors.
2.) Well resistors.
3.) Polysilicon resistors.
4.) Metal resistors.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-9
CMOS Analog Circuit Design © P.E. Allen - 2016
Capacitors
Polysilicon-polysilicon
capacitors:
Metal-metal capacitors:
060530-01
Third level
from top metal
Second level
from top metalInter-
mediate
Oxide
Layers
Top
Metal
Protective Insulator Layer
Metal Via
Capacitor Top Metal
Capacitor bottom plate
Capacitor
dielectric
Fourth level
from top metal
Vias connecting bottom
plate to lower metal
Vias connecting top
plate to top metal
Vias connecting bottom
plate to lower metal
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-10
CMOS Analog Circuit Design © P.E. Allen - 2016
Inductors
Top view and cross-section of a planar inductor:
Enhanced inductor removing the substrate†:
†M. Raieszadeh, Integrated Inductors on Trenched Silicon Islands, MS Thesis, School of Electrical and Computer Engineering, Georgia Institute of Technology, April 2005
W
S
D
D
Top Metal
Next Level
Metal
Top Metal
Next Level
MetalVias
Oxide
Oxide
Silicon Substrate
N turns
030828-01
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-11
CMOS Analog Circuit Design © P.E. Allen - 2016
TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS
Major Fabrication Steps for a DSM CMOS Process
1.) p and n wells
2.) Shallow trench isolation
3.) Threshold shift and anti-punch through implants
4.) Thin oxide and gate polysilicon
5.) Lightly doped drains and sources
6.) Sidewall spacer
7.) Heavily doped drains and sources
8.) Siliciding (Salicide and Polycide)
9.) Bottom metal, tungsten plugs, and oxide
10.) Higher level metals, tungsten plugs/vias, and oxide
11.) Top level metal, vias and protective oxide
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-12
CMOS Analog Circuit Design © P.E. Allen - 2016
Starting Material
The substrate should be highly doped to act like a good conductor.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-02PolycideGate Ox
Substrate
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-13
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 1 - n and p wells
These are the areas where the transistors will be fabricated - NMOS in the p-well and
PMOS in the n-well.
Done by implantation followed by a deep diffusion.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-03PolycideGate Ox
p+ n+
n-well p-well
Substrate
n well implant and diffusion p well implant and diffusion
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-14
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 2 – Shallow Trench Isolation
The shallow trench isolation (STI) electrically isolates one region/transistor from
another.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-04PolycideGate Ox
p+ n+
n-well
Shallow
Trench
Isolation
p-well
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Substrate
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-15
CMOS Analog Circuit Design © P.E. Allen - 2016
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-05PolycideGate Ox
n+
n-well p-well
Shallow
Trench
Isolation
Substrate
p threshold implant p threshold implant
n+ anti-punch through implant p+ anti-punch through implant
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Step 3 – Threshold Shift and Anti-Punch Through Implants
The natural thresholds of the NMOS is about 0V and of the PMOS is about –1.2V. An
p-implant is used to make the NMOS harder to invert and the PMOS easier resulting in
threshold voltages balanced around zero volts.
Also an implant can be applied to create a higher-doped region
beneath the channels to prevent punch-through from the drain
depletion region extending to source depletion region.
Source Drain
Punch-through
120521-02
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-16
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 4 – Thin Oxide and Polysilicon Gates
A thin oxide is deposited followed by polysilicon. These layers are removed where they
are not wanted.
p+ p p- MetalSaliciden- n n+Oxide Poly 060118-06PolycideGate Ox
p+ n+
n-well p-well
Substrate
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-17
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 5 – Lightly Doped Drains and Sources
A lightly-doped implant is used to create a lightly-doped source and drain next to the
channel of the MOSFETs.
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-01PolycideGate Ox
p+ n+
n-well
Shallow
Trench
Isolation
p-well
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Substrate
Shallow n-
Implant
Shallow n-
Implant
Shallow p-
Implant
Shallow p-
Implant
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-18
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 6 – Sidewall Spacers
p+ p p- MetalSaliciden- n n+Oxide Poly 070321-02PolycideGate Ox
p+ n+
n-well
Shallow
Trench
Isolation
p-well
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Substrate
Sidewall
Spacers
Sidewall
Spacers
A layer of dielectric is deposited on the surface and removed in such a way as to leave
“sidewall spacers” next to the thin-oxide-polysilicon-polycide sandwich. These sidewall
spacers will prevent the part of the source and drain next to the channel from becoming
heavily doped.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-19
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 7 – Implantation of the Heavily Doped Sources and Drains
Note that not only does this step provide the completed sources and drains but allows for
ohmic contact into the wells and substrate.
p+ p p- Metal Salicide n- n n+ Oxide Poly 070321-03Polycide Gate Ox
n+
n-well
n+
Shallow
Trench
Isolation p-well
p+
Shallow
Trench
Isolation
Substrate
p+
implant
n+
implant
n+
implant
n+
implant
p+
implant
p+
implant
Shallow
Trench
Isolation
p+ p+ n+ n+
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-20
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 8 – Siliciding (Salicide and Polycide)
This step reduces the resistance of the bulk diffusions and polysilicon and forms an
ohmic contact with material on which it is deposited.
Salicide = Self-aligned silicide
p+ p p- Metal Salicide n- n n+ Oxide Poly 070321-04Polycide Gate Ox
Salicide Salicide Salicide
Polycide
p+ n+
n-well
n+
Shallow
Trench
Isolation p-well
p+
Salicide
Shallow
Trench
Isolation
Substrate
Polycide
Shallow
Trench
Isolation
n+ n+ p+ p+
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-21
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 9 – Intermediate Oxide Layer
An oxide layer is used to cover the transistors and to planarize the surface.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-22
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 10- First-Level Metal
Tungsten plugs are built through the lower intermediate oxide layer to provide contact
between the devices, wells and substrate to the first-level metal.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-23
CMOS Analog Circuit Design © P.E. Allen - 2016
Step 11 – Second-Level Metal
The previous step is repeated for the second-level metal.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-24
CMOS Analog Circuit Design © P.E. Allen - 2016
Completed Fabrication
After multiple levels of metal are applied, the fabrication is completed with a thicker top-
level metal and a protective layer to hermetically seal the circuit from the environment.
Note that metal is used for the upper level metal vias. The chip is electrically connected
by removing the protective layer over large bonding pads.
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-25
CMOS Analog Circuit Design © P.E. Allen - 2016
Scanning Electron Microscope of a MOSFET Cross-section
Fig. 2.8-20
TEOS
TEOS/BPSG
Tungsten Plug
SOG
Polycide
Poly
Gate
Sidewall
Spacer
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-26
CMOS Analog Circuit Design © P.E. Allen - 2016
Scanning Electron Microscope Showing Metal Levels and Interconnect
Fig.180-11
Metal 1
Metal 2
Metal 3
Tungsten
Plugs
Aluminum
Vias
Transistors
Lecture 03 – DSM CMOS Technology (11/16/15) Page 03-27
CMOS Analog Circuit Design © P.E. Allen - 2016
SUMMARY
• DSM technology typically has a minimum channel length between 0.35µm and 0.1µm
• DSM technology addresses the problem of excessive depletion region widths in
junction isolation techniques by using shallow trench isolation
• DSM technology may have from 4 to 8 levels of metal
• Lightly doped drains and sources are a key aspect of DSM technology
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