gts issues & status - agata.pd.infn.it

GTS Issues & Status

AGATA Electronics Meeting Padova 1/12/2004

Work in Progress

• GTS mezzanine PCB• Alignement algorithm• Atca boards• Vhdl development

GTS Mezzanine

• Pcb layout entirely redone at Cern– Fixes manufacturing problems– Signal integrity analysis on critical nets– New functionalities added

GTS Mezzanine layout

Alignment Algorithm

• Two models– Phase equalization by consecutive MGT

resets– Phase equalization by direct

measurements

Consecutive MGT resetsRoot node

MGT Opt Fiber

Mezzanine

Tx

Rx

Root tx

Root rx

GTS clock

Consecutive MGT resets

• Mgt wakes up with arbitrary phase• Almost uniformly distributed in one clk cycle• At the root node the phase of RXUSRCLK is

the sum of downstream and upstream MGT pairs clk phases

• Idea : minimize or maximize this sum– The contribution of each pair almost equal– By halving the measure we obtain the latency of

each pair

TEST CONDITIONS

TX1

RX1

RX2

TX2

DATA

100 MHz OSC

RDOUT CLK

“ROOT”

P1

SHIFTER / FILTER

RECOV. CLOCK100m FIBRE

DATA PATTERN

DATA OUT

RDOUT CLK

“NODE”

RocketIO MGT RocketIO MGT

P2P3

oscilloscope

ASYMMETRY = |TD-TU| / 10 [ns]

NUMBER OF MEASURES = 11481

TD TU

TL

DOWN-LINK LATENCY DISTRIBUTIONS (TD)

0

200

400

600

800

1000

1200

1400

160083

5

837

838

840

841

843

844

846

847

849

850

852

853

855

latency [ns]

freq

. [#]

UP-LINK LATENCY DISTRIBUTION (TU)

0

100

200

300

400

500

600

70083

5

836

837

838

839

840

841

842

843

844

845

846

847

848

849

850

851

latency [ns]

freq

. [#]

LOOP LATENCY DISTRIBUTION (TL)

0

200

400

600

800

1000

120016

73

1675

1677

1679

1681

1683

1685

1687

1689

1691

1693

1695

1697

1699

1701

1703

latency [ns]

freq

. [#]

ASYMMETRY vs LOOP LATENCY

0,0%

50,0%

100,0%

150,0%

200,0%

250,0%

300,0%

350,0%16

7016

7116

7216

7316

7416

7516

7616

7716

7816

7916

8016

8116

8216

8316

8416

8516

8616

8716

8816

8916

9016

9116

9216

9316

9416

9516

9616

9716

9816

9917

0017

0117

0217

0317

0417

05

latency [ns]

asym

met

ry

Direct MeasurementsMezzanine

Tx

MGT Opt Fiber

Rx

Select

Direct Measurements1. Measure RTT without MGTs

1. Fixed value (Tf)

2. Insert MGT pair on downstream channel

3. Measure RTT again 1. (Fixed value + MGT latency) = Ttx

4. Subtract value from measure at point 11. Ttx – ½ Tf = Tdown

5. Insert upstream MGT pair

6. Measure RTT1. (Fixed value + 2 x MGT latencies) = Ttot

7. Subtract measure at 48. Ttot – Tdown = Tup

Atca Boards

1. Rapid testbed for VHDL development

2. Used as fanin-fanout& root node

3. Programmable4. Customizable area 5. Provided by Xilinx &

Avnet

Vhdl Development

• Standalone GTS Mezzanine– Needed for LLP testing– Needed for Ancillary I/F testing– Functionalities

• Global clock and timestamp• GTS I/F protocol compliant• Validates all trigger requests