george mason university ece 545 – introduction to vhdl logic synthesis with synopsys ece 545...
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ECE 545 – Introduction to VHDL George Mason University
Logic Synthesis with Synopsys
ECE 545Lecture 11
ECE 545 – Introduction to VHDL 2
Basic High-Level
Design Flow
ECE 545 – Introduction to VHDL 3
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
beginA1<=A when (NEG_A='0') else
not A;B1<=B when (NEG_B='0') else
not B;Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;
with (L1 & L0) selectY1<=MUX_0 when "00",
MUX_1 when "01",MUX_2 when "10",MUX_3 when others;
end MLU_DATAFLOW;
VHDL description Circuit netlist
Logic Synthesis
ECE 545 – Introduction to VHDL 4
Basic Synthesis Flow
ECE 545 – Introduction to VHDL 5
Synthesis using Design Compiler
ECE 545 – Introduction to VHDL 6
ECE 545 – Introduction to VHDL 7
ECE 545 – Introduction to VHDL 8
Scripts
ECE 545 – Introduction to VHDL 9
Synthesis script (1)
designer = "Pawel Chodowiec"company = "George Mason University"search_path = "./opt3/synopsys/TSMCHOME/digital/Front_End/timing_power/tcb013ghp_200a "link_library = "* tcb013ghptc.db" /* Typical case library */target_library = "tcb013ghptc.db "symbol_library = "tcb013ghp.sdb "
/* Directory configuration */
src_directory = ~/exam1/vhdl/report_directory = ~/exam1/reports/db_directory = ~/exam1/db/
ECE 545 – Introduction to VHDL 10
Synthesis script (2)
/* Packages can be only read */
read_file -format vhdl -rtl src_directory + "components.vhd"
blocks = {regne, upcount, RAM_16Xn_DISTRIBUTED, exam1}
foreach (block, blocks) {block_source = src_directory + block + ".vhd"read_file -format vhdl -rtl block_sourceanalyze -format vhdl -lib WORK block_source}
current_design block/* All commands now apply to the entity "exam1" */
ECE 545 – Introduction to VHDL 11
Synthesis script (3)
uniquify/* Creates unique instances of multiple refrenced entities */
linkcheck_design/* Checks the current design for consistency */
/*******************************************//* apply block attributes and constraints *//*******************************************/create_clock -period 10 clk/* Defines that the port "clk" on the entity "clk" is the clock for the design. Period=10ns 50% duty cycleUse -waveform option to define duty cycle other than 50%*/
set_operating_conditions NCCOM/*Normal Case Commercial Operating Conditions*/
ECE 545 – Introduction to VHDL 12
Synthesis script (4)
/***************************************************//* Apply these constraints to the top-level entity*//***************************************************/
set_max_fanout 100 blockset_clock_latency 0.1 find(clock, "clk")set_clock_transition 0.01 find(clock, "clk")set_clock_uncertainty -setup 0.1 find(clock, "clk")set_clock_uncertainty -hold 0.1 find(clock, "clk")set_load 0 all_outputs()set_input_delay 1.0 -clock clk -max all_inputs()set_output_delay -max 1.0 -clock clk all_outputs()set_wire_load_model -library tcb013ghptc -name "TSMC8K_Fsg_Conservative"
ECE 545 – Introduction to VHDL 13
Wireload model basics (1)
ECE 545 – Introduction to VHDL 14
Wireload model basics (2)
ECE 545 – Introduction to VHDL 15
Synthesis script (5)
set_dont_touch block
compile -map_effort medium
change_names -rules vhdlvhdlout_architecture_name = "sort_syn"vhdlout_use_packages = {"IEEE.std_logic_1164"}write -f db -hierarchy -output db_directory + "exam1.db"/*write -f vhdl -hierarchy -output db_directory + "exam1_syn.vhd"*/report -area > report_directory + "exam1.report_area"report -timing -all > report_directory + "exam1.report_timing"
ECE 545 – Introduction to VHDL 16
Tips & Hints
ECE 545 – Introduction to VHDL 17
Tips & Hints (1)
Each entity and each package should be placedin a different file.
The name of each file should be exactly the sameas the name of an entity or package it contains.
Arrange entity names in the bottom-up order(the top-most entity at the end of the list)and define this list in your script using the command
blocks = { entity1, entity2, …, entityN}
ECE 545 – Introduction to VHDL 18
Tips & Hints (2)
Use only one clock in your entire design.
Use an identical name for the clock signal in all yourentities and packages (including declarationsof components).
Use the same clock name in all clock-related commandsof your script, such as create_clock, set_clock_transition, etc.
ECE 545 – Introduction to VHDL 19
Avoid advanced features, such as:• multiple clocks, • gated clocks, • multicycle paths, • circular feedback loops containing only combinational logic.
Although these features are supported by Synopsys,their correct use requires additional knowledgeand experience that are beyond the scope of ECE 545.
Tips & Hints (3)
ECE 545 – Introduction to VHDL 20
Tips & Hints (4)
Create a project directory in your main user directory.
Create the following subdirectories in the project directory: db, docs, log, reports, scripts, tb, vhdl.
Place all your synthesizable source files in the vhdl directory, and your testbench files in the tbdirectory.Place your scripts in the script directory.
Define at least the following directories close to thebeginning of your script: src_directory, report_directory, db_directory.
ECE 545 – Introduction to VHDL 21
Tips & Hints (5)
Change your current directory to your log directory before you execute design_analyzer.
After executing your script within design_analyzer,analyze the contents of log files generated in the directory log.
These files contain the exact description of warningsand errors generated during synthesis.
Please do your best to eliminate all errors andmajority of warnings generated by the scripts and written to the log files.
ECE 545 – Introduction to VHDL 22
Results of synthesis
ECE 545 – Introduction to VHDL 23
Area report after synthesis (1)
report_areaInformation: Updating design information... (UID-85) ****************************************Report : areaDesign : exam1Version: V-2003.12-SP1Date: Tue Nov 15 20:39:06 2005****************************************
Library(s) Used:
tcb013ghptc (File: /opt3/synopsys/TSMCHOME/digital/Front_End/timing_power/
tcb013ghp_200a/tcb013ghptc.db)
ECE 545 – Introduction to VHDL 24
Area report after synthesis (2)
Number of ports: 75Number of nets: 346Number of cells: 107Number of references: 28
Combinational area: 10593.477539Noncombinational area: 14295.521484Net Interconnect area: undefined (Wire load has zero net area)
Total cell area: 24888.976562Total area: undefined
ECE 545 – Introduction to VHDL 25
Critical Path (1)
• Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers
D Qin
clk
D Qout
t logic
tCritical = tFF-P + tlogic + tFF-setup
ECE 545 – Introduction to VHDL 26
Critical Path (2)
• Min. Clock Period = Length of The Critical Path
• Max. Clock Frequency = 1 / Min. Clock Period
ECE 545 – Introduction to VHDL 27
n+m
n+m
ECE 545 – Introduction to VHDL 28
Clock Jitter
• Rising Edge of The Clock Does Not Occur Precisely Periodically• May cause faults in the circuit
clk
ECE 545 – Introduction to VHDL 29
Clock Skew
• Rising Edge of the Clock Does Not Arrive at Clock Inputs of All Flip-flops at The Same Time
D Qin
clk
D Qout
delay
D Qin
clk
D Qout
delay
ECE 545 – Introduction to VHDL 30
H-clock tree used to minimize clock skew
ECE 545 – Introduction to VHDL 31
Timing report after synthesis (1)
****************************************Report : timing -path full -delay max -max_paths 1Design : exam1Version: V-2003.12-SP1Date : Tue Nov 15 20:39:06 2005****************************************
Operating Conditions: NCCOM Library: tcb013ghptcWire Load Model Mode: segmented
ECE 545 – Introduction to VHDL 32
Timing report after synthesis (2)
Startpoint: in_addr(1) (input port clocked by clk) Endpoint: RegSUM/Q_reg[34] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max
Des/Clust/Port Wire Load Model Library ----------------------------------------------------------------------------------- exam1 TSMC8K_Fsg_Conservative tcb013ghptc RAM_16Xn_DISTRIBUTED ZeroWireload tcb013ghptc exam1_DW01_cmp2_32_0 ZeroWireload tcb013ghptc exam1_DW01_cmp2_32_1 ZeroWireload tcb013ghptc exam1_DW01_add_35_0 ZeroWireload tcb013ghptc regne_1 ZeroWireload tcb013ghptc regne_2 ZeroWireload tcb013ghptc regne_n35 ZeroWireload tcb013ghptc
ECE 545 – Introduction to VHDL 33
Timing report after synthesis (3)
Point Incr Path ------------------------------------------------------------------------------------------------ clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.10 0.10 input external delay 1.00 1.10 f in_addr(1) (in) 0.00 1.10 f U98/Z (CKMUX2D1) 0.13 1.23 f Memory/ADDR[1] (RAM_16Xn_DISTRIBUTED) 0.00 1.23 f Memory/U41/ZN (INVD1) 0.08 1.31 r Memory/U343/Z (OR3D1) 0.10 1.41 r Memory/U338/ZN (INVD2) 0.20 1.61 f Memory/U40/ZN (MOAI22D0) 0.17 1.78 f Memory/U350/Z (OR4D1) 0.26 2.03 f Memory/DATA_OUT[0] (RAM_16Xn_DISTRIBUTED) 0.00 2.03 f
ECE 545 – Introduction to VHDL 34
Timing report after synthesis (4)
add_96xplusxplus/B[0] (exam1_DW01_add_35_0) 0.00 2.03 f add_96xplusxplus/U9/Z (AN2D0) 0.12 2.15 f add_96xplusxplus/U1_1/CO (CMPE32D1) 0.10 2.25 f add_96xplusxplus/U1_2/CO (CMPE32D1) 0.10 2.34 f add_96xplusxplus/U1_3/CO (CMPE32D1) 0.10 2.44 f add_96xplusxplus/U1_4/CO (CMPE32D1) 0.10 2.54 f add_96xplusxplus/U1_5/CO (CMPE32D1) 0.10 2.63 f add_96xplusxplus/U1_6/CO (CMPE32D1) 0.10 2.73 f add_96xplusxplus/U1_7/CO (CMPE32D1) 0.10 2.82 f add_96xplusxplus/U1_8/CO (CMPE32D1) 0.10 2.92 f add_96xplusxplus/U1_9/CO (CMPE32D1) 0.10 3.02 f add_96xplusxplus/U1_10/CO (CMPE32D1) 0.10 3.11 f add_96xplusxplus/U1_11/CO (CMPE32D1) 0.10 3.21 f add_96xplusxplus/U1_12/CO (CMPE32D1) 0.10 3.31 f add_96xplusxplus/U1_13/CO (CMPE32D1) 0.10 3.40 f add_96xplusxplus/U1_14/CO (CMPE32D1) 0.10 3.50 f
ECE 545 – Introduction to VHDL 35
Timing report after synthesis (5) add_96xplusxplus/U1_15/CO (CMPE32D1) 0.10 3.60 f add_96xplusxplus/U1_16/CO (CMPE32D1) 0.10 3.69 f add_96xplusxplus/U1_17/CO (CMPE32D1) 0.10 3.79 f add_96xplusxplus/U1_18/CO (CMPE32D1) 0.10 3.88 f add_96xplusxplus/U1_19/CO (CMPE32D1) 0.10 3.98 f add_96xplusxplus/U1_20/CO (CMPE32D1) 0.10 4.08 f add_96xplusxplus/U1_21/CO (CMPE32D1) 0.10 4.17 f add_96xplusxplus/U1_22/CO (CMPE32D1) 0.10 4.27 f add_96xplusxplus/U1_23/CO (CMPE32D1) 0.10 4.37 f add_96xplusxplus/U1_24/CO (CMPE32D1) 0.10 4.46 f add_96xplusxplus/U1_25/CO (CMPE32D1) 0.10 4.56 f add_96xplusxplus/U1_26/CO (CMPE32D1) 0.10 4.66 f add_96xplusxplus/U1_27/CO (CMPE32D1) 0.10 4.75 f add_96xplusxplus/U1_28/CO (CMPE32D1) 0.10 4.85 f add_96xplusxplus/U1_29/CO (CMPE32D1) 0.10 4.94 f add_96xplusxplus/U1_30/CO (CMPE32D1) 0.10 5.04 f add_96xplusxplus/U1_31/CO (CMPE32D1) 0.10 5.14 f
ECE 545 – Introduction to VHDL 36
Timing report after synthesis (6)
add_96xplusxplus/U7/Z (AN2D0) 0.10 5.24 f add_96xplusxplus/U5/Z (AN2D0) 0.08 5.32 f add_96xplusxplus/U4/Z (CKXOR2D0) 0.15 5.47 f add_96xplusxplus/SUM[34] (exam1_DW01_add_35_0) 0.00 5.47 f RegSUM/R[34] (regne_n35) 0.00 5.47 f RegSUM/U32/Z (AO21D0) 0.11 5.57 f RegSUM/Q_reg[34]/D (EDFQD1) 0.00 5.57 f data arrival time 5.57
ECE 545 – Introduction to VHDL 37
Timing report after synthesis (7)
clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.10 10.10 clock uncertainty -0.10 10.00 RegSUM/Q_reg[34]/CP (EDFQD1) 0.00 10.00 r library setup time -0.12 9.88 data required time 9.88 ------------------------------------------------------------------------------------- data required time 9.88 data arrival time -5.57 ------------------------------------------------------------------------------------- slack (MET) 4.31
ECE 545 – Introduction to VHDL 38
Timing parameters
ECE 545 – Introduction to VHDL 39
Timing parameters
definition units pipelining
delay
clock period
clock frequency
time pointpoint
rising edge rising edgeof clock
1clock period
ns
ns
MHz
good
good
latency
throughput
time inputoutput
#output bits/time unit
ns
Mbits/s
bad
good
ECE 545 – Introduction to VHDL 40
register
combinationallogic
one round
multiplexer
Basic iterative architectureof the encryption/decryption unit
round keys
enc_dec
ECE 545 – Introduction to VHDL 41
IN
OUT
M1
C1
M2
C2
M3
Basic iterative architecture: Timing
k · clock_period
CLK
Latency
ECE 545 – Introduction to VHDL 42
Increasing throughput using pipelining
round 1
round 16
. . .
Throughput =
target_clock_period
block sizetargetclock period,e.g., 20 ns
ECE 545 – Introduction to VHDL 43
Optimizationcriteria
ECE 545 – Introduction to VHDL 44
Degrees of freedom and possible trade-offs
speed area
power testability
ECE 545 – Introduction to VHDL 45
speed
area
latency
throughput
Degrees of freedom and possible trade-offs
ECE 545 – Introduction to VHDL 46
Optimizationmethods
ECE 545 – Introduction to VHDL 47
Speed optimization methods (1)
• better architecture (e.g., CLA vs. ripple carry adder)
• pipelining
• parallel processing
• optimization options of synthesis and implementation tools
ECE 545 – Introduction to VHDL 48
Speed optimization methods (2)
• reducing fanout of control signals
• better state encoding
• registered outputs from the state machine
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