Altera Quartus II – Synopsys Design Vision Tutorial

Part III

ECE 465 (Digital Systems Design)

ECE Department, UIC

Instructor: Prof. Shantanu Dutt

Prepared by: Xiuyan Zhang, Ouwen Shi

In tutorial part II, we discussed the reasons why we need Synopsys Design Vision for a more accurate power and

area estimation, and static timing analysis of a design (in Section 7). For this purpose, we converted a Quartus II

schematic design to a VHDL design. As an example, we converted a hierarchical based 4-bit ripple carry adder

(RCA) schematic, RCA_4b, and a 1-bit full adder (FA), FA_1b, to VHDL designs using Quartus II.

In this tutorial, RCA_4b will be compiled and synthesized by Design Vision. This tutorial will also introduce power

estimation, area estimation, and static timing analysis performed by Design Vision.

Please note that this tutorial is based on Synopsys Design Vision on UIC ECE department server: jump.ece.uic.edu.

Content 1. VHDL Design Compilation

2. Power Estimation

3. Area Estimation

4. Static Timing Analysis

5. Appendix: The Schematic Design before and after VHDL Design Compilation

1. VHDL Design Compilation (Circuit Synthesis)

In this section, we use the example of RCA_4b which contains two VHDL files: RCA_4b.vhd and FA_1b.vhd. These

two files are generated from Quartus II as explained in the tutorial Part II, Section 7.

(1) File Directory Setting and Design Vision Initialization

First, use FileZilla to login jump.ece.uic.edu. Under your home directory, create a project directory called “RCA4b”.

Next, transfer from your computer (where you ran Quartus II) files RCA_4b.vhd, FA_1b.vhd, and the setup file

.synopsys_dc.setup to the project directory.

Now, launch Xming and PuTTY. Use PuTTY to login jump.ece.uic.edu.

Access the directory “RCA4b”. Then, enter the command design_vision to launch Design Vision. A window of Design

Vision appears (shown in Fig. 1).

Figure 1. Window of Design Vision

In the top panel, there are two panes. The left pane is a full “Logical Hierarchy” pane. It shows the entire hierarchy of the

current design. The right panel is a context based panel which will display contents based upon the selection in the drop

down box at the top of the panel. The bottom panel has three different tabs: log, history and errors/warnings. The important

thing to note about this panel is that every command you perform will appear in this panel, allowing you to learn the

commands and create scripts of commands for future use. It is also the panel that you must monitor to determine the source

of errors and warnings, allowing you to fix the code or correctly determine if a warning is expected.

(2) VHDL File Compilation

Design Vision has three main steps:

1. Analysis: The Analyze command checks the HDL designs for proper syntax and synthesizable logic, translates

the design files into an intermediate format, and stores the intermediate files in the directory you specify.

2. Elaboration: The Elaborate command first checks the intermediate format files before building a .db design.

During this process, Elaborate determines whether it has the necessary synthetic operators to replace the HDL

operators, and it also determines correct bus size.

3. Design Compilation (Circuit Synthesis): The Compile Design command results in the synthesis the circuit based

on the VHDL files and the library files of logic gates/cells/components specified in the Synopsys setup file

.synopsys_dc.setup.

First, click to open the top-level design, which is RCA_4b.vhd.

Figure 2. Open VHDL Design File

If we start Design Vision under the project directory, the VHDL design files will automatically appear in the file panel.

Next, analyze all the VHDL files of a hierarchical based design to elaborate the top-level design.

Note that, the top-level design cannot be elaborated if any low-level designs are missing.

To analyze designs, click File > Analyze. Then, we click Add, and select ALL VHDL files that have appeared. Click OK

to analyze designs. Add both RCA_4b.vhd and FA_1b.vhd.

Figure 3. Window of “Analyze Designs”

Then, we elaborate the design of the top-level VHDL design by selecting File > Elaborate.

Figure 4. Window of “Elaborate Designs”

Select the top-level design for “Design”. Only the top-level design needs to be elaborated in Design Vision. Select

RCA_4b(BDF_TYPE).

Figure 5. Hierarchy of the Design after Elaborating

The left pane of the main window shows the full hierarchy of the design starting from the design that is specified as the

top-level. Right click on RCA_4b can view the VHDL-based schematic (equivalently Quartus II) design. Various examples

of different schematic types are shown in the Appendix.

Finally, we compile RCA_4b by clicking Design > Compile Design.

Figure 6. Window of Compile

We compile the design by the default setting which is shown in Fig. 6 which includes all 3 mapping “efforts” being

“medium”. Do NOT change any setting except when there is a particular requirement in the project instruction. If you do

so, we will detect it and your project will be invalidated. Please pay careful attention to this as this is needed for a fair and

correct grading of projects.

As we discussed in the setup documentation (Part I of this tutorial set), it is possible that a set of library files in the setup

file cannot provide all the required components; the corresponding error is shown below:

Figure 7. Error of Missing Component.

If you see this error, you need to change the current setup file to a larger setup file which contains a larger library set. All

details regarding this are provided in the setup documentation Section 2.3.4.

If the design compiles successfully, the console window will display the following information:

Figure 8. Successful Compilation.

Next, we will discuss how to perform power/area/static timing analysis in Design Vision (with default setting).

2. Power Estimation

Power estimation in Design Vision provides the total power consumption, as well as its various categories, of the

synthesized circuits.

After compiling the design RCA_4b, we can do power estimation by clicking Design > Report Power.

Figure 9. Power Estimation.

When performing power estimation (shown in Fig. 9), we should select “high” for “analysis effort” to obtain a more

accurate power result than the results generated from the default setting of “low”. Then, click OK to get the power result

which is shown in Figure 10. To save the report, select “To file” to save the report with a particular name and to a particular

directory.

Figure 10. Power Result Report.

In the report, there are different categories of power: Internal power; Switching power; Leakage power; Total power.

Click can also save the report with entering the path (directory) and file name.

3. Area Estimation

Similar to power estimation, we can do area estimation by clicking design > Report Area.

Figure 11. Power Result Report.

Similarly to the power report, by selecting “To File”, we can save the area report to a particular directory (make sure

to name the file differently from the power and timing reports). Then, click OK to obtain the area report.

Figure 12. Area Report.

The area report shows certain important data that will be asked in the project: total area; total cell area; number of

ports; number of nets; number of cells.

4. Static Timing Analysis

The Static Timing Analysis (STA) in Design Vision provides the (worst-case) propagation delay of a design. To

perform STA, click Timing > Report Timing Path. Figure 13 shows the STA window.

Figure 13. Initial Window of Report Timing Path.

We do analysis by using the default setting shown in Fig. 13.

On the top panel, we can select a particular path that we want to analyze by providing the “From”, “Through”, and

“To” pin/net/port/clock. In general, the default setting will provide the worst-case delay among all possible paths.

Figure 14. Static Timing Analysis Result.

Figure 14 show the static timing analysis result for RCA_4b. In the result panel, “f” stands for the falling edge, “r”

stands for rising edge, of the concerned signal, and the unit of timing result is ns. The category “Incr” stands for

incremental timing which shows the incremental timing contributions from each cell in the path. 0.17 ns is the

cumulative timing or data arrival time at the output of the entire design of RCA_4b (with default setting). Again, by

selecting “To File”, the timing report can be saved to a particular directory (make sure to name the file differently

from the power and area reports).

Now, we have collected all required results for power, area, and static timing.

5. Appendix: Schematic Design before and after VHDL Design Compilation

Figure 15. shows the VHDL-schematic design view (by exposing the entire design hierarchy, up to the lowest-level)

of the VHDL design RCA_4b.vhd before Design Vision’s compilation/synthesis of the design. We call this

schematic the VHDL-based schematic.

Figure 15. VHDL-based Schematic view of a FA in RCA_4b before Compilation.

Figure 16. shows the schematic design view (lowest level) of RCA_4b after Compilation (final circuit synthesis).

We call this schematic the DV-synthesis schematic.

Figure 16. DV-Synthesis Schematic View of the Same FA after Compilation (Final Circuit Synthesis).

After compilation, the VHDL design file is transferred to the corresponding mapped design file which is a gate-level

design implementation that uses components from the selected technology library in the setup file. Thus, the

difference between VHDL-based schematic and DV-synthesis schematic is each gate has been mapped to a particular

component i.e., two XOR gates “C11” and “C12” in VHDL-based schematic had been mapped to two

“XOR2X1_RVT” cells “U3” and “U1” in DV-synthesis schematic respectively, where “XOR2X1_RVT” in the

selected technology library stands for: functional operation is XOR; 2X1 is 2 1-bit inputs, with “X1”: 1x standard

load (Csl, which is provided in the selected library) as the input pin capacitance; “RVT” is the standard threshold

voltage, Vth. Also, one compact cell “AO22X1_RVT” (which is an AND-OR gate/cell) in DV-synthesis schematic

has replaced the two AND gates and an OR gate in DV-synthesis schematic. This has been done as such a single

compact cell reduces all three metrics, delay, power and area (approximately number of transistors plus wiring)

compared to the two And and one OR gates and the interconnects/wires between them that it replaces (AO22X1

means the following: AO: And-OR; 22X1: two ANDs with 2 1-bit inputs each and connect to OR gate which has 2

1-bit inputs from two AND gates, with 1x standard load as the input pin capacitance).

References:

1) Design Compiler® Tutorial Using Design Vision™ http://lyle.smu.edu/~manikas/SDC_help/dvtut.pdf

2) Design Vision Tutorial, Department of ECE, University of Wisconsin Madison

http://coefs.uncc.edu/amukherj/files/2012/04/DesignVisionTutorial_f07.pdf

Latest modified by Xiuyan Zhang on Feb. 16, 2017.