ese570 inv stat12

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 1

ESE 570 MOS INVERTERS STATIC CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 2

Vin

Vout

0

Logic “0” = 0 VLogic “1” = V

DD V

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 3

VDD

0VDD

VOLV

T0n

VOH

≤ VDD

VOL

≥ 0

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 4

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 5

Slope of VTC or

inverter gain

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 6Minimum area nMOS, pMOS transistor layouts limited by design rules

Pstatic = VDD ID

Tj = T

a + ΘP

Θ -> Thermal Resistance (oC/W) (W)

(oC) (oC)

Steady-State (Static) Output Voltage Behavior

P → Pstatic

, Pdynamic

P static=V DD

2[ I D V in=V OLI D V in=V OH ]

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 7

Area=16∗82=12822

6

2 4

3

16

84

2

6

2

3144

5 5

3

24

Area=24∗142=3362

Minimum pMOS Layout

Minimum nMOS Layout

Minimum Area MOS Transistor Layouts

1

E2 = 2λ

Relevant Design Rules

4

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 8

VSB

kn' = KP

n

kn'

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 9

NMOS driver transistor

A

C

B

“Visual” Representation of the Resistive-Load Inverter

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 10

Vin = V

OL < V

T0,n => nMOS Cut-off

Vout

= VOH

= VDD

VDD

CALCULTION OF VOH

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 11

Vin = V

DDimplies

CALCULTION OF VOL

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 12

-1

VIL

@ Vin = V

IL

CALCULTION OF VIL

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 13

VIH

CALCULTION OF VIH

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 14

CALCULTION OF VIH CONT.

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 15

CALCULTION OF Vth

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 16VT0n

VDD

0 VDD

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 17

-> VT0n

-> VT0n

-> VT0n

-> 0

VDD

Vout

VDD

VinV

T0n

knR

L -> ∞

0

semi-ideal VTC

Take Limit as knR

L -> ∞

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 18

1

Vout = VOL

P staticaverage=V DD

2[ I D V in=V OL I D V in=V OH ]

ID(V

in = “1”) = I

L =

P(Vin = “0”) = 0

Pstatic

(average)

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 19

NO UNIQUE W/L, RL

5−0.2=30 x10−6

2WL RL [2 5−10.2−0.22]

Multiplying by RL

WL

RL=2.05 x 105

WL

RL=2V DD−V OL

k n' 2V DD−V T0nV OL−V OL

2 =

25−0.230 x 10−625−10.2−0.22

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 20

WL

RL=2.05 x 105

P staticaverage =V DD

2V DD−V OL

RL

Pstatic

(average) [mW]

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 21

VOL

= 0.147 V or 8.503 V ?

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 22

Preferred Design

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 23

VSB,d

VSB,L

VSB,L

≠ 0

SATURATED NMOS ENHANCEMENT-LOAD INVERTER

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 24

SATURATED NMOS ENHANCEMENT-LOAD INVERTER

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 25

NMOS DEPLETION-LOAD INVERTER

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 26

=> VGSp

= Vin - V

DD

=> VDSp

= Vout

- VDD

IDn

= IDp

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 27

V DD

-1

-1

V ILV IH

Vin

Vout

VT0n V

DD+V

T0p

A E

A

E

-VT0n

-VT0p

LIN

SATLIN

SAT

Vout

= Vin - V

T0n

Vout

= Vin - V

T0p

LIN&

OFF

LIN&

OFF

“Visual” Representation of the CMOS Inverter

V th

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 28

V th V DD

-1

-1

V ILV IH

Vin

Vout

VT0n V

DD+V

T0p

A E

-VT0n

-VT0p

LIN

SATLIN

SAT

Vout

= Vin - V

T0n

Vout

= Vin - V

T0p

LIN&

SAT

LIN&

SAT

“Visual” Representation of the CMOS Inverter

SAT&

SAT

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 29

V th−V T0p

V th−V T0n V out

V in=∞

V th

V th V DD

-1

-1

V ILV IH

Vout

= Vin - V

T0p

Vout

= Vin - V

T0n

IDn

= IDp

(iff λ = 0)

-VT0n

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 30

0 =

= 0

IDn

= IDp = 0

IDn

= IDp = 0

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 31

Eq.(1)

IDn

= IDp

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 32

k n'

2WL

n2V in−V T0n=

k p'

2WL

p[2V out−V DD2 V in−V DD−V T0p

d V out

d V in]

VIL

VIL

(-1)

¿[−2 V out−V DDd V out

d V in](-1)

(1)Eq.(1)

Eq.(2)

SOLVE Eq. (1) and Eq. (2) for Vout

and VIL

or use simulation.

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 33

IDn

= IDp

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 34

Eq.(3)

Eq.(4)

SOLVE Eq. (3) and Eq. (4) for Vout

and VIH

or use simulation.

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 35

IDn

= IDp

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 36

RECALL THAT

Setting for Vin = V

th and solving for V

th

wherek R=

k n' W /Ln

k p' W /L p

=n W /Lnp W /Lp

np

Eq.(5)

Usually Ln = L

p is set to min L:

k R=k n

' W /Lnk p

' W /L p

=n W n

p W p

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 37

If Vth is set to

If, also

ideal Vth

Eq.(5)

Solving Eq.(5) for kR

DESIGN OF CMOS INVERTERS

V th=V T0n 1

k RV DDV T0p

1 1k R

k R=V DDV T0p−V th

V th−V T0n

2

k R=0.5V DDV T0p

0.5V DD−V T0n

2

V th=V th ideal =12

V DD

Symmetric CMOS InverterIf V

th(ideal) and V

T0n = - V

T0p = V

T0k Rsymetric=1

Important design Eq. for CMOS inverter VTC.

Eq.(5)

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 38

Vth (v

olts

)

1/kR

V th=V T0n 1

k RV DDV T0p

1 1k R

VDD

= 5V; VT0n

= - VT0p

= 1 V

Vth vs. 1/k

R

1k R

=p W p

n W n

where Ln = L

p

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 39

W /Lp≈2.52 W /Ln

FROM Eq. (1) and Eq. (2)

FROM Eq. (3) and Eq. (4)

Symmetric CMOS inverter Vth(ideal)

and VT0n

= - VT0p

= VT0

=>k Rsymetric=1

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 40

V IL=V out−12

V DD

2V IL V DD−4 V IL V T0=−V T02 −V T0 V DD

34

V DD2

V IL2 −2V IL V T0V T0

2

V IL2V DD−4V T0=34

V DD2 −V T0 V DD−V T0

2V IL=

183V DD2V T0V DD−2V T0

V DD−2V T0

DERIVE: for Symmetric CMOS Inverter

Eq.(1)

Symmetric CMOS inverter: Vth = V

DD/2, V

T0n = - V

T0p = V

T0 and k

R = 1

Eq.(2) =>

Substitute V out=V IL12

V DD into Eq.(1), i.e.

.=2V IL2 −2V IL V DD2V IL V T0−V IL V DDV DD

2 −V T0 V DD−V IL2 V IL V DD−

14

V DD2

, Vin = V

IL and Sym-Inv Cond.

QED

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 41

EXAMPLE: Compute the noise margins for a symmetric CMOS inverter has been designed to achieve V

th = V

DD/2, where V

DD = 5 V

and VT0n

= - VT0p

= 1 V.

NMH = NM

L = 2.5 V > V

DD/2

RECALL

NM H=V OH−V IH=V DD−58

V DD−28

V T0=38

V DD28

V T0

NM L=V IL−V OL=V IL=38

V DD28

V T0=38

V DD28

V T0

0

V DD

1.

2.

1.

Ideal NM =>

1. NMH, NM

L > V

DD/2 = 1.25 V

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 42

Pstatic

= 0

Pstatic

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 43

Smaller Area Layout

If the inverter cell is part of a standard cell library, it will adhere to the cell layout protocols.

Kenneth R. Laker, University of Pennsylvania, updated 13Feb12 44

Pstatic

> 0

VDD

≥ Vout

> - VT0p