elad hadar omer norkin supervisor: mike sumszyk winter 2010/11 date: technion – israel institute...

Elad Hadar

Omer Norkin

Supervisor: Mike Sumszyk

Winter 2010/11

Date:

Technion – Israel Institute of TechnologyFaculty of Electrical EngineeringHigh Speed Digital System Lab (HS DSL)

Exploring new implementation tools for GIDEL PROCSTAR platform

(Characterization presentation)

Motivation• Implementing simple video analysis designs on

GIDEL PROCSTAR III platform that will enable usage and exploration of new platform dedicated development tools.

Proper usage of development tools throughout all stages of implementation from algorithm to hardware.

Usage of powerful debug tools as part of the workflow.

• GIDEL PROC HILs - enable HW acceleration under SIMULINK environment.

• GIDEL PROC API – enable real-time configuration and querying of the board.

• GIDEL TOTAL HISTORY (based on ALTERAs SignalTap) – provide true tracing capabilities.

Development & debug tools

Project objective

Learning and practice of effective debug methodology using PROC API and Total History/SignalTap.

Implementation of a simple algorithm of computer vision performing edge detection using gradient computation in DSPbuilder.*

Testing of the algorithm with Hardware in the loop (Gidel PROC HILs)Partial porting to the FPGA

* Two different algorithms will be implemented

Phase I Phase II

• GiDEL's PROCStar III is an ALTERA Stratix III based board.

• 4xFPGA integrated on single board.

Hardware

Workflow

PROC HILs

PROC APITotal History/

Signal Tap

•Simple algorithm code.

• Stream-based implementation.

• Simulink designs based on ALTERA IPs.

• Load the design on FPGA using PROC HILs – Analyzing tool’s performance.

Workflow (phase I)

•Simple algorithm code.

• Stream-based implementation.

• Simulink designs based on ALTERA IPs.Automatic generation of VHDL/Verilog scripts based on a block design.

• Perform Synthesis & Place and Route.

Workflow (phase II)

Workflow (phase II)

• Generate interface envelope (VHDL code)

• Create a project including all VHDL files (from DSPbuilder as well as from Procwizard)

• Load the design on the FPGAs and apply PROC API functions to create an effective real time debug environment combined with Toatal History / Signal Tap.

Video stream diagram (phase II)

RX - FIFO TX - FIFO

PROC MegaFIFO

PROC API

Full project plan1) Learning the work environment (Simulink, DSPBuilder, Quartus, PROC

Wizard, PROC Hils)

2) Implement the basic algorithm of gradient computation using DSPbuilder in Simulink environment

3) Testing the design using PROC Hils and analyzing prformance

4) Build a simple hardware design (Adder) combining DSPbuilder and the PROC Wizard

5) Learning Total history, PROC API, PROC MegaFIFO

6) Build an Adder design combining DSPbuilder and the PROC Wizard using PROC API

7) Define an integrated design combining PROC API video streaming functions and data channels, PROC MegaFIFO memories and DSPbuilder design

8) Real-time debug with Total history and Signal Tap (comparison of the tools)

Time table to mid. presentationWeek

8Week

7Week

6Week

5Week

4Week

3Week

2Week

1Task

Learning the work environment (Simulink, DSPBuilder, Quartus, PROC Wizard, PROC Hils)

Implement the basic algorithm of gradient computation using DSPbuilder in Simulink environment

Testing the design using PROC Hils and analyzing prformance

Build a simple hardware design (Adder) combining DSPbuilder and the PROC Wizard