ee104 project (2)

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Class Project

For the center-tapped full wave rectifier shown in Figure 1, given that VS(t) is sinusoidal with

peak voltage VP =10V and frequency f=50Hz:

(a) Refer to Figure 2 to show that, when a capacitor C is connected in parallel with the load

resistor R, the value of the ripple voltage (Vr) can be controlled by designing the time constant

RC to be as follows:

=1 (

2

)

(

2)

Where:

VP and are the peak voltage and the radian frequency of the secondary voltage VS

2 is the peak-to-peak ripple voltage

VDon is the forward voltage drop across the diodes.

(b) If R=10, what is the value of C to maintain ripple voltage less than or equal to 5% of the

maximum voltage (i.e., 0.05 )?

(c) If the output DC voltage of this rectifier is approximated as , what is the

maximum power delivered to the load in point (b)?

(d) In order to validate your design, use PSPICE to simulate the output voltage of the above

rectifier. Plot VO(t) and show that your design satisfies the ripple voltage requirements, as

shown in Figure3.

(e) Using the capacitor you designed in (b), what happens to the ripple voltage if the value of R

is changed to be 1. What is the output power of the rectifier in this case?

Figure 1

Electronics (EE104) 1st Year (2014-2015)

Dr. Mohammed Hassan

Fayoum University Faculty of Engineering Electrical Engineering Dep.

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Figure 2

Figure 3