ece 448 – fpga and asic design with vhdl lecture 15 external sram

ECE 448 – FPGA and ASIC Design with VHDL

Lecture 15

External SRAM

2ECE 448 – FPGA and ASIC Design with VHDL

Required reading

• P. Chu, FPGA Prototyping by VHDL Examples

Chapter 10, External SRAM

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Block diagram of a typical SRAM

ECE 448 – FPGA and ASIC Design with VHDL

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SRAM Functional Table

ECE 448 – FPGA and ASIC Design with VHDL

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SRAM Simplified Functional Table

ECE 448 – FPGA and ASIC Design with VHDL

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Timing diagram of an address-controlled read cycle

ECE 448 – FPGA and ASIC Design with VHDL

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Timing diagram of an output_enable-controlled read cycle

ECE 448 – FPGA and ASIC Design with VHDL

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SRAM Timing Parameters (in ns)

ECE 448 – FPGA and ASIC Design with VHDL

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Timing diagram of write cycle

ECE 448 – FPGA and ASIC Design with VHDL

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SRAM Timing Parameters (in ns)

ECE 448 – FPGA and ASIC Design with VHDL

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Role of a memory controller

ECE 448 – FPGA and ASIC Design with VHDL

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Block diagram of a memory controller

ECE 448 – FPGA and ASIC Design with VHDL

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ASM chart of a safe SRAM

controller

ECE 448 – FPGA and ASIC Design with VHDL

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ASM chart of a testing

circuit

ECE 448 – FPGA and ASIC Design with VHDL

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ASM chart of an alternative

SRAM controller: design I

ECE 448 – FPGA and ASIC Design with VHDL

16

ASM chart of an alternative

SRAM controller: design II

ECE 448 – FPGA and ASIC Design with VHDL

17ECE 448 – FPGA and ASIC Design with VHDL

ASM chart of an alternative

SRAM controller: design III

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Generating a half cycle with DDR

ECE 448 – FPGA and ASIC Design with VHDL