digital system design verilog ® hdl useful modeling techniques maziar goudarzi

Digital System Design

Verilog® HDLUseful Modeling Techniques

Maziar Goudarzi

2005 Verilog HDL 2

Today Program

Procedural Continuous AssignmentOverriding ParametersConditional Compilation and ExecutionUseful System Tasks

Procedural Continuous Assignment

Useful Modeling Techniques

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Procedural Continuous Assignment

Overrides, for a certain time, the effect of regular assignments to a variable.

Two types assign/deassign

Works only on register data types force/release

Works on both register and net data types

Note: Not synthesizable. Use only for modeling and simulation

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Procedural Continuous Assignment (cont’d)assign/deassign

Keywordsassign: overrides regular procedural assignments

• LHS: reg or concatenation of regs. No nets. No arrays. No bit-select or part-select

deassign: re-enables regular procedural assignments

After deassign: Last value remains on the register until a new

procedural assignment changes it.

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Procedural Continuous Assignment (cont’d)

force/release Keywords:

force: overrides all procedural/continuous/ procedural continuous assignments

release: re-enables other assignments Hence, assignments in priority order:

1. force

2. assign (procedural continuous)

3. Procedural/continuous assignments

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force/release on reg variables

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force/release on nets

Net value immediately returns to its normal assigned value when released

Overriding Parameters

Useful Modeling Techniques

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Overriding Parameters

Two methods defparam statement Module instance parameter value assignment

defparam statement Keyword: defparam Syntax:

defparam <parameter_hierarchical_name>=<value>;

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Overriding Parameters (cont’d)

Module instance parameter values Parameters are overridden when the module is

instantiated Syntax:

<module_name> #(<param_vals>) <instance_name>;

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Example with multiple parameters

Conditional Compilation and Execution

Useful Modeling Techniques

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Conditional Compilation

Usage: To compile some part of code under certain

conditions

Keywords: ‘ifdef, `else, `endif ‘define to define the flag

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Conditional Execution

Usage: To execute some part of code when a flag is set at runtime Used only in behavioral modeling

Keywords: $test$plusargs

Syntax: $test$plusargs( <argument_to_check> )

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Useful System Tasks

Useful Modeling Techniques

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Useful System TasksFile Output

Opening a file Syntax:

<file_handle> = $fopen( “<file_name>” ); <file_handle> is a 32 bit value, called multi-channel descriptor Only 1 bit is set in each descriptor Standard output has a descriptor of 1 (Channel 0)

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Useful System TasksFile Output (cont’d)

Writing to files $fdisplay, $fmonitor, $fstrobe $strobe, $fstrobe

The same as $display, $fdisplay, but executed after all other statements schedule in the same simulation time

Syntax: $fdisplay(<handle>, p1, p2,…, pn);

Closing files$fclose(<handle>);

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Example: Simultaneously writing to multiple files

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Useful System TasksRandom Number Generation

Syntax:$random;

$random(<seed>);

Returns a 32 bit random value

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Useful System TasksInitializing Memory from File

Keywords: $readmemb, $readmemh

Used to initialize memory (reg [3:0] mem[0:1023]) Syntax:

$readmemb(“<file_name>”, <memory_name>);

$readmemb(“<file_name>”, <memory_name>, <start_addr>);

$readmemb(“<file_name>”, <memory_name>, <start_addr>, <finish_addr>);

The same syntax for $readmemh

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Useful System TasksValue Change Dump (VCD) File

ASCII file containing information on Simulation time Scope and signal definitions Signal value changes

Keywords $dumpvars $dumpfile $dumpon $dumpoff $dumpall

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Today Summary

Introduced a number of modeling techniques useful in various applications

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Other Notes

Homework 8 Chapter 9:

All exercises with ModelSim, except for 3 and 5 3 and 5 in paper and pencil Due date: Sunday, Day 11th