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A language based on ISO-C, extended for hardware design

( HandleC )HandleC )

prepared by:prepared by:Mitra Khorram AbadiMitra Khorram Abadi

professor:professor:Dr. Maziar GoudarziDr. Maziar Goudarzi

Addressing System Design ChallengesAddressing System Design Challenges

A Crisis of ComplexityA Crisis of Complexity

- - Existing FPGA flows inadequate for emerging designsExisting FPGA flows inadequate for emerging designs- - Design capacity outstripping ability to design and verifyDesign capacity outstripping ability to design and verify- - Systems contain both hardware and softwareSystems contain both hardware and software- - Algorithmic design path to performance too longAlgorithmic design path to performance too long

Celoxica System Design SolutionsCeloxica System Design Solutions

- - System-level Electronic Design Automation company,System-level Electronic Design Automation company, established in 1996 with technology from Oxford University established in 1996 with technology from Oxford University- - Design tools apply C-based languages to FPGA designDesign tools apply C-based languages to FPGA design

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What are Handel-C and DKWhat are Handel-C and DK

Handel-CHandel-C

High-level language based on ISO/ANSI-C for the High-level language based on ISO/ANSI-C for the implementation of algorithms in hardwareimplementation of algorithms in hardware

Allows software engineers to design hardware without Allows software engineers to design hardware without retrainingretraining

Clean extensions for hardware design including hardware data Clean extensions for hardware design including hardware data types, flexible data widths,types, flexible data widths,

parallelism and communicationsparallelism and communications

higher level than HDLs such as VHDL and Veriloghigher level than HDLs such as VHDL and Verilog

based on extensive hardware compilation research at Oxfordbased on extensive hardware compilation research at Oxford

Core building block for Celoxica™ DK design suiteCore building block for Celoxica™ DK design suite

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DK design suitDK design suit

A design environment for Handel-C, targeting FPGAs and A design environment for Handel-C, targeting FPGAs and reconfigurable hardwarereconfigurable hardware

– – project managementproject management

– – hardware compilation with optimizationhardware compilation with optimization

– – simulationsimulation

– – generates output for FPGA place-&-route toolsgenerates output for FPGA place-&-route tools

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Why Handel-CWhy Handel-C

• Chip design is becoming prohibitive for all but large production • Chip design is becoming prohibitive for all but large production runsruns – increased complexity, high cost, long lead-time, short product – increased complexity, high cost, long lead-time, short product life-cycleslife-cycles• Potential solutions• Potential solutions – design reuse (e.g., IP blocks) – design reuse (e.g., IP blocks) – raise the level of abstraction, leading to rapid design – raise the level of abstraction, leading to rapid design methodologymethodology – use reconfigurable hardware to extend product life-cycles – use reconfigurable hardware to extend product life-cycles• in-service upgrades• in-service upgrades• Handel-C provides for these solutions• Handel-C provides for these solutions – increased system performance – increased system performance – lower system power – lower system power – reduced cost – reduced cost• Handel-C and DK provides for rapid development• Handel-C and DK provides for rapid development – bring hardware and software engineers closer together – bring hardware and software engineers closer together

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Applications for Handel-CApplications for Handel-C

Handel-C enables concurrent hardware and software application Handel-C enables concurrent hardware and software application design within a common C language environment.design within a common C language environment.Celoxica’s rapid hardware prototyping capability offers an unparalleled Celoxica’s rapid hardware prototyping capability offers an unparalleled ability to design and build fully optimized applications, thus boosting ability to design and build fully optimized applications, thus boosting performance and reducing costs. performance and reducing costs. This allows software engineers to reduce development complexity and This allows software engineers to reduce development complexity and compress the time-to-market by directly participating in the hardware compress the time-to-market by directly participating in the hardware design process.design process.A number of recent projects developed under Handel-C illustrate the A number of recent projects developed under Handel-C illustrate the language’s wide applications fit.language’s wide applications fit.

• Internet Security• Internet Security-DES encryption algorithm in hardware for SSL -DES encryption algorithm in hardware for SSL accelerationacceleration• Digital Music• Digital Music-MP3 decoding in reconfigurable hardware-MP3 decoding in reconfigurable hardware• Internet Telephony• Internet Telephony-Voice-over-IP phone implementing H.323 and -Voice-over-IP phone implementing H.323 and TCP/IP in hardwareTCP/IP in hardware• Image Processing• Image Processing-Accelerating complex image processing -Accelerating complex image processing algorithms in FPGAsalgorithms in FPGAs

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OverviewOverview

• Overview of Handel-C• Overview of Handel-C– what is like C– what is like C– what is different from C– what is different from C

• Design flow• Design flow

• DK Features• DK Features

• DK Compiler Features• DK Compiler Features

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Handel-C is Like CHandel-C is Like C

• Standard ISO-C (ANSI-C)• Standard ISO-C (ANSI-C)• Basic data types• Basic data types – signed/unsigned integers, char, enums – signed/unsigned integers, char, enums• Composite data types• Composite data types – arrays, structs, unions – arrays, structs, unions – pointers – pointers• Control structures• Control structures – if, while, for, switch, etc. – if, while, for, switch, etc.• Functions with parameters• Functions with parameters• Preprocessor, separate compilation, linker• Preprocessor, separate compilation, linker

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Handel-C Extends CHandel-C Extends C

• Arbitrary widths on variables• Arbitrary widths on variables• Bit manipulation operators• Bit manipulation operators• Timing model• Timing model• par{…} construct for parallelism• par{…} construct for parallelism• Channels for communication and synchronization• Channels for communication and synchronization• Sharing/copying expressions• Sharing/copying expressions• RAMs/ROMs and external pin connections• RAMs/ROMs and external pin connections

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Widths of Variables

• 32-bit integers would consume excessive hardware resources• Handel-C allows specification of bit-width as part of integer types

int 6 a; // signed 6-bit integerunsigned 9 b; // unsigned 9-bit integer

• Variables compile to hardware registers– size determined by data type

• Arithmetic operator hardware sized by type of operands• Compiler can infer bit width in most cases

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Bit Manipulation Operators

• The usual C bit-wise operators on integer types can be used

>> << & | ^ ~

• Additional operators on integer typesa <- 5 // take 5 least significant bits of aa \\ 5 // drop 5 least significant bits, return the resta @ b // concatenate bits of a and ba[3] // select bit 3 of aa[4:1] // select bits 4 through 1 of a

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Timing model

• An assignment statement takes one cycle• A delay statement takes one cycle• Combinatorial expressions computed between clock edges

– most complex expression determines clock period• Example: the following takes 1 + n cycles (n is number of iterations)

index = 0; // 1 cyclewhile (index < length) {

if (table[index] = key)found = index; // 1 cycle per iterationbreak;

elseindex = index + 1;

}

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Parallelism

• Handel-C blocks are by default sequential• par { ... } executes statements in parallel

par { a = 1; b = 2; c = 3;}

• par block completes when all statements complete– time for par block is the time for the longest statement

• Can nest sequential blocks in par blocks

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Channels

• Channels allow communication and synchronization between par blocks – semantics based on CSP: unbuffered (synchronous) send and receive• Channel declaration – specifies the data type to be communicated, e.g.:

chan unsigned 6 c;

• Send statement transfers a value when receiver is ready• Receive statement copies a value into a variable when sender is ready• One cycle for transfer, plus wait cycles if either party not ready• Example

{ { ... ... c ! val + 1; c ? x; ... ...} }

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Sharing Hardware for Expressions

• Functions provide a means of sharing hardware for expressions• By default, compiler generates separate hardware for each expression – hardware is idle when control flow is elsewhere in the program { ...

x = x*a + b;y = y*c + d;

}• Hardware for function body is shared among call sites

int mult_add(int z, c1, c2) { return z*c1 + c2; }

...

{ ...x = mult_add(x, a, b);y = mult_add(y, c, d);

}

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Replicating Hardware for Expressions

• Inline functions are expanded at the call site– provide for functional abstraction of complex hardware

inline complex mult_complex(complex x, y) {complex z;par {

z.re = x.re*y.re - x.im*y.im;z.im = x.re*y.im + x.im*y.re;

}return z;

}...complex x1, y1, x2, y2, z1, z2;...par {

z1 = mult_complex(x1, y1);z2 = mult_complex(x2, y2);

}

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Memories

• ROM and RAM data types are like arrays– implemented using FPGA memory resources

• Example

#define packet_length 18ram unsigned 8 packet_buf[packet_length]...packet_buf[index] = received_byte;...if (packet_buf[0] == my_addr) {

...}

• ROMs are similar, but initialized with data• RAMs and ROMs can be internal (on-chip) or external (off-chip)

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Differences between RAMs and arraysDifferences between RAMs and arrays

RAMs differ from arrays in that an array is equivalent to declaring a RAMs differ from arrays in that an array is equivalent to declaring a number of variables. Each entry in an array may be used exactly like number of variables. Each entry in an array may be used exactly like an individual variable, with as many reads, and as many writes to a an individual variable, with as many reads, and as many writes to a different element in the array as required within a clock cycle. different element in the array as required within a clock cycle.

RAMs, however, are normally more efficient to implement in terms ofRAMs, however, are normally more efficient to implement in terms ofhardware resources than arrays, but they only allow one location to be hardware resources than arrays, but they only allow one location to be accessed in any one clock cycle. accessed in any one clock cycle. Therefore, you should use an array when you wish to access theTherefore, you should use an array when you wish to access theelements more than once in parallel and you should use a RAM when elements more than once in parallel and you should use a RAM when you need efficiency.you need efficiency.

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Targeting hardware; FPGAs and PLDs

The set family and set part constructs allow you to specify the device you want to target in your source code. You can also set the device using the DK GUI.

Targeting hardware; memory

The ram and rom keywords allow you to create on-chip RAM and ROM, and to interface to external RAM and ROM. If you want to create a block RAM, use the block specification.To interface to off-chip RAMs or ROMs, use the offchip specification. The addr, data, we, cs, oe and clk specifications define the pins used between the FPGA/PLD and external RAM or ROM.

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Design flowDesign flow

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DK Design SuiteDK Design Suite

The Celoxica DK Design Suite is a fully featured development The Celoxica DK Design Suite is a fully featured development environment for software-compiled system design. It enables all environment for software-compiled system design. It enables all members of the design team, from system architects and hardware members of the design team, from system architects and hardware developers to software and firmware designers and verification developers to software and firmware designers and verification engineers, to share code from system specification through to engineers, to share code from system specification through to implementation.implementation.Software-compiled system design is a methodology for designing Software-compiled system design is a methodology for designing modern electronic systems that contain both software-driven modern electronic systems that contain both software-driven microprocessors and programmable hardware, either as discrete microprocessors and programmable hardware, either as discrete components or as integrated Field Programmable System on Chip components or as integrated Field Programmable System on Chip (FPSoC) devices. Where both processors and custom logic are (FPSoC) devices. Where both processors and custom logic are required it is clearly beneficial for the design and implementation required it is clearly beneficial for the design and implementation process of both software and hardware to have a common language process of both software and hardware to have a common language base and a connected methodology.base and a connected methodology.

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Software-compiled system design enables:Software-compiled system design enables:

• The system specification to be written in a form that both teams can • The system specification to be written in a form that both teams can immediately use;immediately use;• Improved communication and shared understanding between the • Improved communication and shared understanding between the development teams;development teams;• Simplified partitioning and migration of code between software and • Simplified partitioning and migration of code between software and hardware;hardware;• Iterative design exploration and implementation;• Iterative design exploration and implementation;• Re-partitioning to optimize the system at any stage in the design • Re-partitioning to optimize the system at any stage in the design process; and,process; and,• Verification of design implementations using high-level test benches • Verification of design implementations using high-level test benches derived from the system requirements in the original specification.derived from the system requirements in the original specification.The benefits of the DK Design Suite result in increased design The benefits of the DK Design Suite result in increased design productivity, reduced development time, and improved overall quality of productivity, reduced development time, and improved overall quality of design (QoD). design (QoD).

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Development EnvironmentDevelopment Environment

The Celoxica DK Design Suite has an easy to use Integrated The Celoxica DK Design Suite has an easy to use Integrated Development Environment (IDE) that provides facilities for:Development Environment (IDE) that provides facilities for:

• Project file management• Project file management• Source code editing• Source code editing• Fast simulation and debugging• Fast simulation and debugging• Compilation of the Handel-C language direct to FPGA hardware • Compilation of the Handel-C language direct to FPGA hardware (EDIF)(EDIF)• Compilation of the Handel-C language to Hardware Description • Compilation of the Handel-C language to Hardware Description Languages (VHDL and Verilog)Languages (VHDL and Verilog)• Co-simulation between• Co-simulation between

- C/C++- C/C++- Handel-C- Handel-C- HDLs- HDLs- Instruction Set Simulators (ISSs)- Instruction Set Simulators (ISSs)- Modeling languages such as SystemC and Matlab- Modeling languages such as SystemC and Matlab

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DK Compiler FeaturesDK Compiler Features

• Compiler output is• Compiler output is – optimized – optimized – deterministic – deterministic – target specific – target specific

• Targets Xilinx and Altera netlists directly (EDIF)• Targets Xilinx and Altera netlists directly (EDIF)• RTL VHDL output• RTL VHDL output• IP Cores• IP Cores – generation of IP cores (Handel-C, EDIF, VHDL) – generation of IP cores (Handel-C, EDIF, VHDL) – inclusion of IP cores as “black boxes” – inclusion of IP cores as “black boxes”

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