digital electronics, 2003 - eeng.dcu.iedigital1/notes/notes3.pdf · digital electronics, 2003...

Digital Electronics, 2003

Ovidiu Ghita Page 118

5. SHIFT REGISTER WITH FEEDBACK IF THE SERIAL OUTPUT OF A SHIFT REGISTER IS CONNECTED BACK TO THE INPUT [Q � J], [Q � K] THEN THE SEQUENCE OF NUMBERS STORED IN THE REGISTER WILL CIRCULATE

Q3 Q2 Q1

E.G. Q3 Q2 Q1 Q0 CLOCK

PULSE * 1 0 1 1 1 1 0 1 1 1 1 1 0 2 0 1 1 1 3

* 1 0 1 1 4 * IDENTICAL SEQUENCE

POSSIBLE SEQUENCES: a) (b) (c)

STATE DIAGRAM

0 0 0 0

1 1 1 1

1 0 0 1

1 1 0 0

0 1 1 0

0 0 1 1

6. RING COUNTER AN N-BIT RING COUNTER HAS N-STATES EACH OF WICH CONTAINS ALL 0’s EXCEPT FOR A SINGLE 1 E.G.

Q0 Q1 Q2 Q3 CLOCK PULSE

* 0 0 0 1 0 0 1 0 1 0 1 0 0 2 1 0 0 0 3

* 0 0 0 1 4 * IDENTICAL SEQUENCE A 4 - BIT RING COUNTER COULD BE MADE FROM OUR PREVIOUS REGISTER BY PARALLEL LOADING WITH 0001, 0010 OR 1000 BUT A SIMPLER METHOD IS TO USE SELF CORRECTING FEEDBACK

Q1 Q2 Q3 Q4

GATED FEEDBACK

E.G. Q1 Q2 Q3 Q4 CLOCK PULSE 1 1 1 1 SWITCH ON 0 1 1 1 1 0 0 1 1 2 0 0 0 1 3 1 0 0 0 4 0 1 0 0 5

NORMAL OPERATION

CHARACTERISTICS: A RING COUNTER IS WASTEFUL OF FLIP FLOPS AS WE GET N STATES WHEREAS UP TO 2N STATES SHOULD BE POSSIBLE WITH N FLIP-FLOPS

DIFFERENT TYPES OF FEED BACK REGISTERS CAN GENERATE OTHER DESIRED SEQUENCES. E.G. CONNECT COMPLEMENT OF OUTPUT (Q) TO INPUT J AND CONNECT Q TO K >>>>> TWISTED RING COUNTER

ADVANTAGES DISADVANTAGES RING SIMPLE

DECODING MANY FLIP-

FLOPS [N FLIP-FLOPS]

BINARY [RIPLE]

EFFICIENT USE OF FLIP

FLOPS [log2N]

COMPLEX DECODING

[EXTRA GATES]

TWISTED RING

SIMPLE DECODING

REQUIRES MANY FLOP-FLOPS

ASYNCHRONOUS BINARY COUNTERS

REMEMBER A N-BIT RING COUNTER HAS N STATES >>> INEFICIENT USE OF N FLIP-FLOPS. IF WE CONNECT THE OUTPUT OF ONE COUNTER TO THE CLOCK INPUT OF THE NEXT, THEN ALL 2N STATES CAN BE USED BY THE BINARY COUNTER. I.E. N FLIP-FLOPS >>>> 2N STATES >>>> BASE 2N E.G. N=3 >>>> 8 DIFFERENT STATES

Q Q QCLK

1 1 1 LSB MSB

OPERATION : ALL FLIP-FLOPS ARE IN TOGGLE MODE SINCE J=K=1 >>> Qt+1 = Qt ON RECEIPT OF A CLOCK PULSE. AS WE ARE USING MASTER-SLAVE FLIP-FLOPS >>> OUTPUT WILL CHANGE ON FALLING EDGE OF CLOCK PULSE. CLK

1 1 1 1

NOTE: Q0 CHANGES AT ½ CLOCK FREQ. Q1 CHANGES AT ½ FREQ. OF Q0

Q2 CHANGES AT ½ FREQ. OF Q1

STATE TABLE FOR 3-BIT COUNTER

STATE Q2 Q1 Q0

0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1

8 = 0 0 0 0 9 = 1

FROM THE COUNTER OUTPUT WAVEFORMS Q0, Q1 AND Q2 APPEAR TO CHANGE SIMULTANEOUSLY. HOWEVER THERE WILL BE A TIME DELAY FOR EACH FLIP-FLOP SO THAT ALL OUTPUTS DO NOT CHANGE IN SYNCHRONISM WITH THE CLOCK PULSE.

A MORE CORRECT WAVEFORM IS AS FOLLOWS:

�t = FLIP-FLOP TIME DELAY CUMULATIVE DELAY OF ASYNCHRONOUS COUNTER >>> MAJOR DISADVANTAGE.

THE EFFECT OF THE CLOCK “RIPPLES” THROUGH THE COUNTER AND TAKES SOME TIME TO REACH THE LAST FLIP-FLOP. CONSEQUENCE: THIS CUMULATIVE DELAY OF AN ASYNCHRONOUS COUNTER LIMITS THE RATE AT WHICH A COUNTER CAN BE CLOCKED AND CAN ALSO CREATE DECODING PROBLEMS. E.G. AT TIME ta � tb THE OUTPUT GOES 011 � 010 � 000 � 100 INSTEAD OF THE IDEAL TRANSITION 011 � 100. THESE FALSE STATES OF THE OUTPUT ARE KNOWN AS GLITCHES.

BASE K COUNTERS

OUR PREVIOUS COUNTER, COUNTED TO BASE 8 (23) SINCE WE HAD 3 FLIP-FLOPS. WE CAN COUNT TO ANY BASE 2N BY USING N FLIP-FLOPS THAT ARE CONNECTED SUCH AS THE OUTPUT OF ONE COUNTER IS CONNECTED TO THE CLOCK INPUT OF THE NEXT FLIP-FLOP. BUT WHEN WE WANT TO COUNT TO A BASE K WHICH IS NOT A POWER OF 2 >>>> WE NEED TO USE A CHAIN OF N FLIP-FLOPS WHERE N IS THE SMALLEST NUMBER FOR WHICH 2N > K ALSO FOR A “BASE K” COUNTER WE NEED CIRCUITRY TO RESET ALL FLIP-FLOPS ONCE THE MAXIMUM COUNT IS REACHED.

E.G. >>>> IN BASE 10 WE WANT TO COUNT FROM 0000 � 1001. THE NEXT PULSE CHANGES THE COUNTER OUTPUT TO 1010. >>>>THIS STATE IS NOT ALLOWED AND ONCE IT OCCURS WE HAVE TO DECODE IT WITH ADDITIONAL CIRCUITRY TO RESET ALL FLIP-FLOPS TO 0000. >>> THIS PRODUCES A BCD COUNT. THE RESETING GATE IS A NAND GATE CONNECTED TO THE ASYNCHRONOUS RESET INPUTS OF THE FLIP-FLOPS WE WISH TO RESET. THE GATE INPUTS ARE CONNECTED TO THE Q’s [or Q’s] OUTPUTS OF THE FLIP-FLOPS WHICH GO TO 1 JUST AFTER THE MAXIMUM COUNT WE WISH TO RECORD.

EXAMPLE: BASE 7 COUNTER COUNT = 0 � 6 = 000 � 110 FIND NUMBER OF FLIP-FLOPS: 22 < 7 < 23 >>> WE NEED 3 FLIP-FLOPS MAXIMUM COUNT = 1102 >>> WHEN COUNT GOES TO 1112 WE MUST RESET THE FLIP-FLOPS.

WHEN Q0, Q1 and Q2 GO HIGH: >>> R GOES LOW AND WE RESET THE COUNT TO 000. A LATCH MAY BE NEEDED TO ELIMINATE RESETING DIFFICULTIES DUE TO UNEQUAL INTERNAL DELAYS. THIS SHOULD BE PLACED BETWEEN R INPUT AND NAND GATE OUTPUT. CLK

1 1 1 0

RMOMENTARLY GOES TO 111

ASYNCHRONOUS UP/DOWN COUNTERS

COUNTING DOWN: E.G. >>>> BASE 8 COUNT 111→ 000 STATE Q2 Q1 Q0 DECIMAL

EQUIVALENT 1 1 1 1 7 2 1 1 0 6 3 1 0 1 5 4 1 0 0 4 5 0 1 1 3 6 0 1 0 2 7 0 0 1 1 8 0 0 0 0 9

1 1 1 7

Q0 [LSB] CHANGES AT EVERY CLOCK PULSE, THEN WHEN DOES Q1 CHANGE? FROM EXAMINING THE STATE TABLE, Q1 CHANGES EVERY TIME Q0 CHANGES FROM 0 → 1

Q2 CHANGES EVERY TIME Q1 CHANGES FROM 0 → 1 BUT A CLOCK TRANSITION OF 1 → 0 CAUSES A FLIP-FLOP TO CHANGE STATE >>>> CONNECT Q0 AS INPUT CLOCK OF FLIP-FLOP1 AND Q1 AS INPUT CLOCK OF FLIP-FLOP2 A BASE 8 ASYNCHRONOUS DOWN COUNTER:

Q Q QCLK

UP/DOWN COUNTER WE COMBINE THE TWO CIRCUITS (FOR COUNTING UP AND DOWN) USING AND OR GATES AND CONTROL INPUT UP/DOWN E.G. >>>> BASE 8 UP/DOWN COUNTER:

CLK Q0

CLK Q1

Q Q QCLK

UP/DOWN UP/DOWN = 1 >>> TOP PATH ENABLED >>> COUNT UP UP/DOWN = 0 >>> LOW PATH ENABLED >>> COUNT DOWN

SYNCHRONOUS COUNTERS

PROBLEMS ASSOCIATED WITH ASYNCHRONOUS COUNTERS:

• SINCE THE CLOCK PULSE RIPPLES THROUGH THE COUNTER >>> THE MAXIMUM DELAY OF THE COUNTER IS THE SUM OF THE DELAYS FOR EACH FLIP-FLOP

N = NUMBER OF FLIP-FLOPS �t = PROP. DELAY OF EACH FLIP- FLOP >>> TOTAL DELAY = N. �t

• THE OUTPUTS OF THE FLIP-FLOPS

DON’T CHANGE SIMULTANEOUSLY • WRONG OUTPUTS WILL APPEAR

MOMENTARILY ON THE COUNTER [GLITCHES].

THESE PROBLEMS CAN BE REDUCED BY USING A SYNCHRONOUS COUNTER IN WHICH EVERY FLIP-FLOP IS CLOCKED BY THE SAME PULSE.

>>> ALL STATES CHANGE SIMULTANEOUSLY.

BASE 8 SYNCHRONOUS COUNTER STATE TABLE:

Q2 Q1 Q0

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0

>>> Q0 TOGGLES ON EVERY CLOCK PULSE. >>> J0 = K0 = 1 >>> Q1 TOGGLES WHEN Q0 = 1 >>> J1 = K1 = Q0 >>> Q2 TOGGLES WHEN Q1 AND Q0 = 1 >>> J2 = K2 = Q1Q0

CLK CLK

KEY DIFFERENCE

THIS MAY BE EXTENDED TO BASE M COUNTERS M = 2N I.E. QM TOGGLES WHEN Q0=Q1=…QM-1=1 >> JM = KM = Q0Q1…QM-1

IF WE ASSUME THE DELAY OF EACH FLIP-FLOP IS THE SAME: >>> TOTAL DELAY = �t + �g �t = PROP. DELAY OF FLIP-FLOP �g = PROP. DELAY OF GATE THIS IS BECAUSE EACH FLIP-FLOP CHANGES STATE AT THE SAME TIME [NOTE] WE ASSUME ALL FLIP-FLOPS HAVE THE SAME �t

• FOR LARGER COUNTERS THERE ARE 2 METHODS OF GENERATINNG THE J AND K

1. “AND” ALL THE Q’s DIRECTLY USING “AND” GATES WITH MANY INPUTS. [PARALLEL CARRY] 2. “AND” QM WITH JM USING 2-INPUT “AND” GATES. [SERIES CARRY]

I.E. J0 = K0 = 1 J1 = K1 = Q0 J2 = K2 = Q0Q1= J1Q1 J3 = K3 = Q0Q1Q2 = J2Q2 : JM= KM = Q0Q1… QM-1 = JM-1QM-1 QUESTION: WHAT’S THE TOTAL PROP. DELAY IN THE SECOND METHOD ?

Q1Q2 Q3

DELAY BETWEEN Q0 AND JM ? PARALLEL CARRY: TMIN = �t + �g SERIES CARRY: TMIN = �t + [N-2]�g

>>> MAX CLOCK = 1/TMIN

TMIN CAN BE CONSIDERABLY SMALLER FOR A PARALLEL CARRY IMPLEMENTATION THAN FOR A SERIAL CARRY APPROACH [PARTICULARLY IF N IS LARGE] BUT PARALLEL CARRY COUNTER HAS DISADVANTAGES:

• LARGE NUMBER OF INPUTS ON THE “AND” GATE

• THE HEAVY LOADING OF THE FLIP-FLOPS AT THE BEGINNING OF THE CHAIN.

BASE K SYNCHRONOUS COUNTER

• K IS NOT A POWER OF 2 • WE CHOOSE N FLIP-FLOPS WHERE

2N > K

E.G. BASE 5 SYNCHRONOUS COUNTER

STATE Q2 Q1 Q0 DECIMAL 1 0 0 0 0 2 0 0 1 1 3 0 1 0 2 4 0 1 1 3 5 1 0 0 4 6 0 0 0 0

WE NEED TO DETECT WHEN THE COUNTER GOES TO ‘101’ AND RESET ALL FLIP-FLOPS. THIS HAPPENS WHEN Q2 AND Q0 ARE BOTH = 1. NOTE: COUNTER GOES TO ‘101’ [5] MOMENTARILY BEFORE RESETING >>>> GLITCH PRESENT

CLK CLK

2R R R

FOR THIS COUNTER A GLITCH WILL BE GENERATED BEFORE THE COUNTER IS RESETED. WE CAN OVERCOME THIS PROBLEM IF WE DESIGN THE COUNTER USING DIRECT OBSERVATION

SYNCHRONOUS BCD COUNTER

Q3 Q2 Q1 Q0 DECIMAL 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 0 0 0 0 0

Q0 CHANGES AT EVERY CLOCK PULSE >>>> J0 = K0 =1 Q1 CHANGES WHEN Q0 =1 AND Q3 = 0 >>>> J1 = K1 = Q0Q3 Q2 CHANGES WHEN Q0 = Q1 = 1 >>>> J2 = K2 = Q0Q1 Q3 CHANGES WHEN Q0 = Q1 = Q2 =1 OR Q3 = Q0 =1 >>>> J3 = K3 = Q0Q1Q2 + Q0Q3

2Q Q Q

CLK CLK

NOTE: THE AND - OR GATE COMBINATION EFFECTIVELY DETECTS THE OCCURANCE OF 1001 AND CAUSES THE COUNTER TO RECICLE PROPERLY ON THE NEXT CLOCK PULSE >>>> OVERCOME GLITCH

GENERAL METHOD TO DESIGN SYNCHRONOUS COUNTERS

IN THE EXAMPLE OF THE BASE 5 SYNCHRONOUS COUNTER WE STILL HAVE GLITCHES. WE NEED TO DEVISE A WAY OF DESIGNING SYNCHRONOUS COUNTERS WHICH WILL ELIMINATE GLITCHES.

1. DRAW THE STATE TABLE FOR EACH OF THE J-K FLIP-FLOPS IN THE COUNTER

2. DRAW KARNAUGH MAPS FOR EACH J AND K INPUTS.

RECALL THE TRUTH TABLE FOR OUR J-K MASTER-SLAVE FLIP-FLOP

J K Qn Qn+1 0 X 0 0 MAINTAIN 0 1 X 0 1 0�1 CHANGE X 1 1 0 1�0 CHANGE X 0 1 1 MAINTAIN 1

INPUTS OUTPUT CHANGE

“X” � DON’T CARE TERM CAN BE EITHER 0 OR 1 EXAMPLE : BASE 6 SYNCHRONOUS COUNTER 1. WE DRAW UP THE TRUTH TABLE FOR EACH J-K FLIP-FLOPS Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 X 0 X 1 X 0 0 1 0 X 1 X X 1 0 1 0 0 X X 0 1 X 0 1 1 1 X X 1 X 1 1 0 0 X 0 0 X 1 X 1 0 1 X 1 0 X X 1 0 0 0

DESIRED REQUIRED INPUT SEQUENCE SEQUENCE TRANSITION Qn � Qn+1 DECIDES VALUES OF J AND K

J AND K INPUTS ARE FOUND FROM FINDING WHAT INPUT VALUES ARE NEEDED TO PRODUCE THE DESIRED OUTPUT CHANGE. WE FILL ALL KNOWN STATES >> REST OF K-MAP TERMS WILL BE DON’T CARE’s 2. WE NOW DRAW THE K-MAPS FOR EACH J, K IN TERMS OF Q2,Q1,Q0

J2 = Q1Q0 K2 = Q0

00 01 11 10Q1Q0

J1 = Q0Q2 K1 = Q0

J0 = 1 K0 = 1 RULES FOR K-MAP:

• ALWAYS INCLUDE 1’s • INCLUDE X’s TO MAXIMISE THE

SIZE OF THE SUBCUBES

00 01 11 10Q1Q0

CLK CLK

digital electronics, 2003 - eeng.dcu.iedigital1/notes/notes3.pdf · digital electronics, 2003...

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