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Designing an LLC Resonant Half-Bridge Power Converter
Hong Huang
Topic 3
Texas Instruments—2010 Power Supply Design Seminar 3-2
Agenda1. Introduction
– Brief review– Advantages
2. Design Prerequisites– Configuration– Operation– Modeling– Voltage gain function
3. Design Considerations– Voltage gain and switching frequency– Line and load regulation– Zero voltage switching (ZVS)– Steps for designing and a design example
4. Conclusions
Texas Instruments—2010 Power Supply Design Seminar 3-3
Introduction• Brief review of resonant converters
– Series resonant converter (SRC)– Parallel resonant converter (PRC)
Lr L rCr
CrRL
SRC PRC
RL
• Single resonant frequency• Circuit frequency increases
with lighter load
• Resonant point changes with load• Large amount of circulating current
Texas Instruments—2010 Power Supply Design Seminar 3-4
Introduction• Brief review of resonant converters
– Combination of SRC and PRC LCC• Two resonant frequencies• Requires three elements
– LLC: alternative LCC• Lr and Lm integrated in a transformer
• Advantages of LLC– High efficiency (ZVS)– Less frequency variation and lower circulating current– ZVS over operating range
Lr LrCr1 Cr
LmCr2 RL RL
LCC LLC
Texas Instruments—2010 Power Supply Design Seminar 3-5
Design Prerequisites • Configuration
– Variable-frequency square-wave generator
– Divider formed by resonant network and RL
– Rectifier to get DC output
– Changing frequency varies voltage across RL
– Frequency-modulated converter instead of PWM
Ir Ios
L r
+ +
Cr
Vsq
Vsq Vso
Vso Lm
Im
RL
Rectifiers for DC Output
Square-Wave Generator
Resonant Network
Cr Lr
LmVso
++
–
– VsqIr
D2
Co
Io
RL
VoD1Q1
Q2
n:1:1Vin = VDC
Texas Instruments—2010 Power Supply Design Seminar 3-6
Design Prerequisites • Operation
– fsw switching frequency – f0 series resonant frequency (Cr and Lr)– fco circuit resonant frequency (Cr Lr, and Lm, together RL)
fsw = f0
Vg_Q1 Vg_Q1 Vg_Q1
Vg_Q2 Vg_Q2 Vg_Q2
Ir IrI r
Is Is IsD1 D1 D1D2 D2 D2
I m I mIm
Vsq Vsq Vsq
0 0 0
0 0 0
0 0 0t0t0t0 t1t1t1 t3t3t3 t2t2t2
time, t time, t time, tt4t4t4
fsw < f0 fsw > f0
Texas Instruments—2010 Power Supply Design Seminar 3-7
Design Prerequisites • Modeling
– First harmonic approximation (FHA)
I r
Lr
+
–
+ +
–
+
Cr
VoeLm
Im Ioe
Re
IrIos
LrCr
Vsq Vge
Vsq Vso
Vso Lm
Im
RL
(a) (b)
• Input and output: Square wave voltages
• Sinusoidal current in resonant circuit
• Input and output: Fundamental components to approximate FHA
• Rectifier and RL equivalent to Re
• AC circuit method can be used
Texas Instruments—2010 Power Supply Design Seminar 3-8
Design Prerequisites • Voltage gain function
– Expression from impedance divider
I r
Lr
+
–
+
–
Cr
VoeLm
Im Ioe
ReVge
o so oeg _DC g _ sw g _ ac
in sq ge
n V V VM M M V /2 V V
×= ≈ = ≈ =
o oeg _ DC
in ge
m e
m e rr
sw
n V VM V /2 V
( j L ) || R 1( j L ) || R j Lj C
where 2 f 2 f and j = 1
×= ≈
ω=
ω + ω +ω
ω = π = π −
Texas Instruments—2010 Power Supply Design Seminar 3-9
Design Prerequisites • Voltage gain function
– Expression (Normalization)
o so oeg _DC g _ sw g _ ac
in sq ge
n V V VM M M V /2 V V
×= ≈ = ≈ =
2n n
g 2 2n n n n e n
L fM
[(L 1) f 1] j[(f 1) f Q L ]×
=+ × − + − × × ×
Normalized Gain
Resonant Frequency Quality Factor
Normalized Frequency
Inductor Ratio
Eq. Load R.
og
in
VM V /2= 0
r r
1f2 L C
=π
r re
e
L /CQ R= sw
n0
ff f= m
nr
LL L=
2
e L28 nR R×= ×π
Texas Instruments—2010 Power Supply Design Seminar 3-10
Design Prerequisites • Voltage gain function
– Plots of gain magnitude, fixed Ln = 5– Qe (load current) increases ⇒ peak gain decreases ⇒ curves shrink
Qe Mg_pk
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.1 1 10Normalized Frequency
Gai
n
Qe = 0.1
Qe = 0.5
Qe = 10
Texas Instruments—2010 Power Supply Design Seminar 3-11
Design Prerequisites • Voltage gain function
– Plots of gain magnitude, fixed Qe = 0.5
– Ln decreases ⇒ peak gain increases ⇒ ZVS obtained but conduction losses increase
Ln Mg_pk
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.1 1 10Normalized Frequency
Gai
n
Ln = 10 Ln = 5
Ln = 3
Texas Instruments—2010 Power Supply Design Seminar 3-12
Design Considerations• Where to base a design?
– In the vicinity of series resonance, fn = 1 ⇒ narrowest frequency variation⇒ Mg able to = 1, >1, and <1
– Right side of the resonant peak ⇒ ZVS requirement
Normalized Frequency, fn
Gai
n, M
g
10.5 2
1.6
1.4
1.2
1
0.8
0.6
a2
a0
Qe = 0
Qe = 0
a4
a1
a3
Qe= max
Frequency in operation
Texas Instruments—2010 Power Supply Design Seminar 3-13
Design Considerations• Line and load regulation
– Properly set up Mg_max and Mg_min
– Frequency limit set up
Normalized Frequency, fn
Gai
n, M
g
1fn_min fn_max
1.6
1.4
1.2
1
0.8
0.6
a2
a0
Qe = 0Qe = max at full load
Qe = 0
a4
a1
a3
Qe= max
Qe= max
M =g_maxn x VV /2
o_max
in_min
M =g_minn x VV /2
o_min
in_max
Qe = 0 at no load
Texas Instruments—2010 Power Supply Design Seminar 3-14Normalized Frequency, fn
Gai
n, M
g
1fn_min fn_max
1.6
1.4
1.2
1
0.8
0.6
a2
a0
Qe = 0
Qe = 0
Qe = 0a4
a1
a3
Qe= max
Qe= max
M =g_maxn x VV /2
o_max
in_min
M =g_minn x VV /2
o_min
in_max
Design Considerations• Overload current operation
– Qe = max to include and meet the required Mg_max
– Operation still on the right side of resonant peakFrequency in operation
Texas Instruments—2010 Power Supply Design Seminar 3-15
0.1 1 10fn_min fn_max
Normalized Frequency, fn
Gai
n, M
g
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Curve 1(Q = 0)e
a2
a0
Q = 0e
a4a1
Curve 3Curve 4
a3
Curve 2 (Q = max)e
M =g_maxn x VV /2
o_max
in_min
M =g_minn x VV /2
o_min
in_max
Design Considerations• Load short circuit • Protection options
– Increase fsw rapidly to reduce Mg to zero – Operation with fn > 1, i.e., fsw > f0 at all times– Independent protection function
Texas Instruments—2010 Power Supply Design Seminar 3-16
Design Considerations
• Zero voltage switching (ZVS)– How ZVS is achieved?
Vg_Q1
Vg_Q2
Q2 Turns On
Q1 Turns Off
Body Diode Turns On
V = 0ds_Q2
I r
Im
Vsq
t0
0
0
t1 t3t2time, t
tdead
t4
Q2: C Discharge,ds
Cr
Lr Lm+– Vsq
Im
Ir
Q1CDS1
CDS2
Q2
V in
V g
V g
n:1:1
Texas Instruments—2010 Power Supply Design Seminar 3-17
Design Considerations
• Zero voltage switching (ZVS)
– Necessary condition
• Input impendence of the resonant network inductive
• Operation on the right side of the resonant peak
– Sufficient condition
• Enough energy stored in the magnetic field, mainly Lm
• Enough time to discharge the capacitors, mainly CDS
Texas Instruments—2010 Power Supply Design Seminar 3-18
Design Considerations
• Why not design on the left side of the resonant peak?
– Capacitive current results
– ZVS lostHard switching Switching losses increase
– Body diode reverse recovery lossesPrimary MOSFET failure
– Higher EMI noise
– Reversed frequency relationship to feedback loop
Texas Instruments—2010 Power Supply Design Seminar 3-19
Design Considerations
• Design Steps – How to initially select?
– fsw, switching frequency
– n, transformer turns ratio
– Ln, inductance ratio
– Qe, series resonant quality factor
Texas Instruments—2010 Power Supply Design Seminar 3-20
Design Considerations
• Design Steps – Switching frequency
– Usually selected for particular applications• Example in off-line applications: Typical below 150 kHz
– Selecting the switching frequency• f decrease ⇒ Bulkier converter• f decrease ⇒ Switching losses decrease ⇒ ZVS benefit decrease• f increase ⇒ ZVS benefits increase vs. hard switching converters
• Very High f : – Component availability– Additional switching losses– Additional concerns due to parasitic effects
Texas Instruments—2010 Power Supply Design Seminar 3-21
Design Considerations
• Design Steps – Transformer turns ratio, n
– Voltage gain can be larger and smaller than unity
– Flexibility in selecting the turns ratio, n
– Turns ratio design with Mg =1, initially, and nominal Vin and Vo
g
in _ noming
o o_ nom M = 1
V /2V /2n M V V= × =
Texas Instruments—2010 Power Supply Design Seminar 3-22
Design Considerations• Design Steps – Ln and Qe
– Ln and Qe to achieve Mg_pk > Mg_max for maximum load
– Select Ln and Qe from pre-plotted peak gain curves
– Initial selection • Ln = 5• Qe = 0.5
– Example: Select Ln and Qefor Mg_max = 1.2
– To achieve design margin –Final selection
• Ln - 3.5, Qe = 0.45• 30% margin over
0.15 1.150.950.750.550.35Quality Factor, Qe
Atta
inab
le P
eak
Gai
n, M
g_pk
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
L = 3.5 byInterpolationM = 1.56Q = 0.45
n
g_pke
L = 5M = 1.2Q = 0.5
ng_pke
L = 1.5n
L = 3.0n
L = 1.5nL = 2.0nL = 3.0nL = 4.0nL = 5.0nL = 6.0nL = 8.0nL = 9.0n
Texas Instruments—2010 Power Supply Design Seminar 3-23
Design Considerations
• Design Steps – Trade-offs to select Ln and Qe
– Different requirements for different applications
– Fixed Qe, Ln decrease ⇒ peak gain increase ⇒ good for ZVS and avoids capacitive current
– But, Ln decrease ⇒ Lm decrease ⇒ conduction losses increase
– Fixed Ln, Qe decrease ⇒ peak gain increase ⇒ frequency variation increase
– Recommend starting with Ln = 5, and Qe = 0.5 (from design practice)
Texas Instruments—2010 Power Supply Design Seminar 3-24
Design Considerations• Resonant circuit design flow
Converter Specifications
Magnetizing Inductance
Resonant Inductor
Resonant Capacitor
Calculate Re
Choose Ln and Qe
Change L and Qn e
NoYes
Check M g and fnAgainst Graph
in
o
Vn
2V=
o_ming_min
in_max
n VM
V / 2×
=
o_maxg_max
in_min
n VM
V / 2×
=
m n rL L L= ×
( )r 2
sw r
1L
2 f C=
π ×
r1C =
π
0 0.5 1 1.5
f = 1.02n_max
Gain
, Mg
1 .9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
M = 1.3g_max
Q = 0e
Q = 0.47e
M = 0.99g_min
Q = 0 .52e
f = 0 .65n_min
L = 3.5n
0.15 1.150.950.750.550.35Quality Factor, Qe
Atta
inab
le P
eak
Gai
n, M
g_ap
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
L = 3.5 byInterpolationM = 1.56Q = 0.45
n
g_ape
L = 5M = 1.2Q = 0.5
ng_ape
L = 1.5n
L = 3.0n
L = 1.5nL = 2.0nL = 3.0nL = 4.0nL = 5.0nL = 6.0nL = 8.0nL = 9.0n
L2 2out
V2o8 × n2 8 × n2
Re × R ×P
= =π π
Are Values Within Limits?Mg_maxMff
g_minn_maxn_min
Texas Instruments—2010 Power Supply Design Seminar 3-25
Design Considerations
• Design example
– Specifications
• Rated output power: 300 W
• Input voltage: 375 to 405 VDC
• Output voltage: 12 VDC
• Rated output current: 25 A
• Efficiency (Vin = 390 VDC and Io = 25 A): >90%
• Switching frequency: 70 kHz to 150 kHz
• Topology: LLC resonant half-bridge converter
Texas Instruments—2010 Power Supply Design Seminar 3-26
Design Considerations• Design example
– Proposed converter circuit block diagram
CBCSS
UCC25600
8
5
7
6
OC
RT
DT
SS
3
2
1
4
GD
GD
VCC
GND
1
2
Cin
ID1 ID2
Cr
T1Lr
Lm
Ir
Co
Io
RL
RDT
RT2
RT1Vs
Ro1
R o2
Vo
D1 D2
U3
U2
U1
Cf Rf1
Q1
Q2
DT1
+
n:1:1
Texas Instruments—2010 Power Supply Design Seminar 3-27
8-pin SOIC (D), Top View
DT
RT
OC
SS
8
7
6
5
1
2
3
4
GD1
VCC
GND
GD2
Design Considerations
• Design example – UCC25600 Features– 8-pin SOIC package
– Programmable:
• dead time
• fmin and fmax
• soft start time
– Protection
• OCP: hiccup and latch-off
• VCC UVLO and OVP
• OTP
– Burst operation
Drive 1
Drive 2
Texas Instruments—2010 Power Supply Design Seminar 3-28
Design Considerations• Resonant circuit design flow
Converter Specifications
Magnetizing Inductance
Resonant Inductor
Resonant Capacitor
Calculate Re
Choose Ln and Qe
Change L and Qn e
NoYes
Check M g and fnAgainst Graph
in
o
Vn
2V=
o_ming_min
in_max
n VM
V / 2×
=
o_maxg_max
in_min
n VM
V / 2×
=
m n rL L L= ×
( )r 2
sw r
1L
2 f C=
π ×
r1C =
π
0 0.5 1 1.5
f = 1 .02n_max
Gai
n, M
g
1 .9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
M = 1.3g_max
Q = 0e
Q = 0.47e
M = 0.99g_min
Q = 0.52e
f = 0 .65n_min
L = 3.5n
0.15 1.150.950.750.550.35Quality Factor, Qe
Att
aina
ble
Pea
k G
ain,
Mg_
ap
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
L = 3.5 byInterpolationM = 1.56Q = 0.45
n
g_ape
L = 5M = 1.2Q = 0.5
ng_ape
L = 1.5n
L = 3.0n
L = 1.5nL = 2.0nL = 3.0nL = 4.0nL = 5.0nL = 6.0nL = 8.0nL = 9.0n
L2 2out
V2o8 × n2 8 × n2
Re × R ×P
= =π π
Are Values Within Limits?Mg_maxMff
g_minn_maxn_min
n = 16
L = 3.5Q = 0.45
ne
L = 210 µHL =
mr 60 µH
C = 27.3 nFr
Texas Instruments—2010 Power Supply Design Seminar 3-29
Design Considerations• Design check
0 0.5 1 1.5Normalized Frequency, fn
Gai
n, M
g1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
M = 1.3g_max
Q = 0e
Q = 0.47e
M = 0.99g_min Q = 0.52e
f = 0.65(80.9 kHz)n_min
L = 3.5n
150 kHz70 kHz 124.4 kHz
f = 1.02(126.9 kHz)n_max
Texas Instruments—2010 Power Supply Design Seminar 3-30
Design Considerations• Design check
– Verification with computer-based circuit simulation – Design reiteration, if needed– Size/select components– Build the board– Verification with bench tests– Re-spin the board/design, if needed
Texas Instruments—2010 Power Supply Design Seminar 3-31
Design Considerations• Experiment results (Lm = 280 µH, Lr = 60 µH, Cr = 24 nF)
1 5 1510 20 25Load Current (A)
Effi
cien
cy ( %
)
95
85
75
65
405 V390 V375 V
Input Voltage, Vin
Output Ripple Voltage(50 mV/div)
90 mV
Time (5 µs/div)
4
2
1
3 VLr
VLm
Vds_Q2
VCr
(200 V/div)
(200 V/div)
Time (5 µs/div)
(200 V/div)
(500 V/div)4
2
1
3
Vds_Q2
Vgs_Q2
VCr
Ir
(500 V/div)
Time (1 µs/div)
(20 V/div)
(100 V/div)
(1.2 A/div)
Efficiency
Resonant Network Voltages (full load)
Resonant Network Current and Voltage(full load)
Output Ripple Voltage(full load)
Texas Instruments—2010 Power Supply Design Seminar 3-32
Test Result versus FHA from the Design• In the vicinity of f0, FHA-
based result very accurate to the final test result (Lr = 60 µH and Cr = 24 nF)
• Away from f0, less accuracy from FHA-based result
• Equation (18)
10 100 1000Frequency, f (kHz)sw
Gai
n, M
g0.6
0.0
2.0
1.4
(170, 0.87)
Bench Test Measurements
Plot Based on Equation 18
(65, 1.90)
(60, 1.57)
(55, 1.27)
(40, 0.70)
(30, 0.51)
(80, 1.58)
(100, 1.21)
(135, 0.99)
(200, 0.78)(240, 0.72)
(400, 0.56)
f = 135 kHz0
m
m r r
L eoeg
ge L e L C
m e
m e rr
jX || RVMV (jX || R ) j(X X )
( j L ) || R1( j L ) || R j L
j C
= =+ −
ω=
ω + ω +ω
Texas Instruments—2010 Power Supply Design Seminar 3-33
Conclusions
• FHA-based method approximately, while effectively, converted complicated LLC resonant-converter circuit to standard AC circuit – greatly simplified its analysis and design
• Method results effective for LLC converter design, especially for initial parameters determination
• Design example with comprehensive design considerations in procedural design steps demonstrating method effectiveness
• Possibility of FHA-based approach for other resonant converters
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