dc2405a: ltm2893 isolated 100mhz adc serial interface and
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1dc2405af
DEMO MANUAL DC2405A
DESCRIPTION
LTM2893 Isolated 100MHz ADC Serial
Interface and LTC2328-18
Demonstration circuit 2405A shows an LTM®2893 isolating and interfacing an LTC®2328-18. The LTM2893 is a high speed SPI isolator for interfacing read only ADCs with a full complement of control signals. The LTC2328-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC. Low noise isolated power is delivered to the isolated side with an LT3999 push-pull driver and isolation transformer.
The DC2405A demonstrates the DC and AC operation of the LTC2328-18 without performance degradation with the LTM2893. The Serial Peripheral Interface (SPI) runs
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
PERFORMANCE SUMMARY
at a maximum 100MHz SCK frequency. The LTM2893 is compatible with many ADCs with SPI clock frequencies up to 100MHz.
The DC2405A connects to either the DC890 for measure-ments with PScope™, or DC590 for measurements with QuikEval™, or DC2026 for measurements with QuikEval and a DC590 sketch or single sample measurements with an example sketch.
Design files for this circuit board are available at http://www.linear.com/demo/DC2405A
Specifications are at TA = 25°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply Range VCC – GND 4.75 5.25 V
Analog Signal Input Range (AIN) ±10.24 V
Clock Frequency (CLK IN) 10 100 MHz
DC590 Interface Voltage Supply 3.0 3.3 3.6 V
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DEMO MANUAL DC2405A
DC2405A CONNECTION DIAGRAM
DC2405A JUMPERS
Figure 1. DC2405A Setup
DEFINITIONS
JP1 – GND2, Isolated ground connection
JP2 – VCC, 5V Power supply input connection
JP3 – GND, Power supply return connection
JP4 – CFG, Default 0, when CFG = 1 a secondary image in U10 is selected, currently not implemented.
JP5 – OE, Output enable for U10, default ON. When OE is ON, U10 drives the signals to U1 (for use with the DC890, DC590, and DC2026). When OE is OFF the signals to U1 are high impedance from U10 and the interface signals can be driven externally.
JP6 – JTAG, header for factory use only
JP7 – EEPROM, is for factory use only, default WP.
100MHz CLK IN
5V GND
DC890
ANALOGINPUT
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DEMO MANUAL DC2405A
Figure 2. PScope Display Capturing 2kHz Input Tone
DC890 QUICK START PROCEDURECheck to make sure that all switches and jumpers are set to their default settings as described in the DC2405A Jumpers section and Figure 1 of this manual. The demo board is designed to use the onboard isolated power sup-ply to generate all the required bias voltages. The analog input is DC coupled.
1. Connect the DC2405A to a DC890 USB High Speed Data Collection Board using the edge connector J4.
2. Connect the DC890 to a host PC with a standard USB A/B cable.
3. Apply +5V and ground to the VCC and GND terminals.
4. Apply a low jitter signal source to J1. Observe the rec-ommended input voltage range for the analog input.
5. Connect a low jitter 100MHz 2.5VP-P sine wave or square wave to connector J2. Note that J2 has a 50Ω termination resistor to ground. Alternatively, a DC1216A 100MHz fixed frequency clock source board can be used.
6. Run the PScope software (Pscope.exe version K83 or later), which can be downloaded from www.linear.com/ designtools/software. The PScope software should rec-ognize the DC2405A and configure itself automatically.
7. Click the Collect button (see Figure 2) to begin acquiring data. The Collect button then changes to Pause, which can be clicked to stop data acquisition.
Complete PScope software documentation is available from the Help menu. Updates can be downloaded from the Tools menu. Check for updates periodically as new features may be added.
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DEMO MANUAL DC2405A
DC590/DC2026 QUICK START PROCEDUREIMPORTANT! To avoid damage to the DC2405A, make sure that VCCIO (JP6 of the DC590, JP3 of the DC2026) of the DC590/DC2026 is set to 3.3V before connecting the DC590/DC2026 to the DC2405A.
1. To use the DC590/DC2026 with the DC2405A, it is necessary to apply 5V and ground to the VCC and GND terminals of the DC2405A.
2. Connect the DC590/DC2026 to a host PC with a standard USB A/B cable.
3. Connect the DC2405A to a DC590/DC2026 USB serial controller using the supplied 14-conductor ribbon cable.
4. Apply a signal source to J1. A clock source on J2 is not necessary.
5. Run the QuikEval software (QuikEval.exe version K107 or later), which is available from www.linear.com/designtools/software. The correct control panel will be loaded automatically.
6. Click the COLLECT button (Figure 3) to begin reading the ADC.
Figure 3. QuikEval Screenshot Captured with a 50Ω Terminator on AIN
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DEMO MANUAL DC2405A
DC2405A SETUPDC POWER
The DC2405A requires +5VDC and draws ~265mA. This current is split between the isolated side and the logic side. The isolated side current consumption is through the DC/DC power converter supplying the LT1468, input buffer, LTC2328-18 ADC, and the isolated side of the LTM2893. The logic side current supplies the FPGA, clock input path, and the LTM2893.
CLOCK SOURCE
You must provide a low jitter 2.5VP-P sine or square wave to the clock input J2 for data collection with the DC890. The clock input is AC-coupled so the DC level of the clock signal is not important. A generator, such as the Rohde & Schwarz SMB100A high speed clock source, is recom-mended to drive the clock input. Drive J2 with a 100MHz clock frequency. The ratio between the clock source and the sampling frequency is 100:1. A 100MHz clock source results in a 1Msps sampling rate.
DATA OUTPUT
If not connected to a DC890, parallel data output from this board (0V to 2.5V by default), can be acquired by a logic analyzer, and subsequently imported into a spreadsheet, or mathematical package depending on what form of digital signal processing is desired. Alternatively, the data can be fed directly into an application circuit. Use pin 50 of
J4, edge connector, to latch the data. The data should be latched using the negative edge of this signal.
ANALOG INPUTS
The DC2405A analog input AIN is a single-ended input referenced to GND2. AIN has a high input impedance buffer (LT1468) before the LTC2328-18 ADC. The default setup for the DC2405A requires that AIN be driven with a low noise, low distortion generator for SINAD, THD, or SNR testing. Use an analog source such as the Stanford Research DS360 or SR1. Synchronize the clock source to the analog source through an external reference input to generate SNR and SINAD results similar to Figure 2 without windowing.
LTM2893 DIGITAL INTERFACE
The demo board has an unpopulated header placeholder in-between U10 and U1. All interface signals between the FPGA (U10) and the logic interface of the LTM2893 (U1) are exposed. An external interface may be connected to this header location by setting the OE jumper JP5 off. When JP5 is low, all signals to the LTM2893 will be high impedance from the FPGA. The header placeholder pin pitch is on 0.100-inch centers.
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DEMO MANUAL DC2405A
This demo board is tested in-house by attempting to duplicate the FFT plot shown in Figure 2. This involves a 100MHz clock source synchronized with a reference clock to an SR1 sinusoidal generator. The SR1 sinusoidal generator is set at a frequency of 2.01416kHz. The input signal level is approximately –1dBFS. A typical FFT obtained with DC2405A is shown in Figure 2. Note that to calculate the real SNR, the signal level (F1 amplitude = –1.006dB) has to be added back to the SNR that PScope displays. With the example shown in Figure 2, this means that the actual SNR would be 94.76dB instead of the 93.76dB that PScope displays.
There are a number of scenarios that can produce mislead-ing results when evaluating an ADC. One that is common
is feeding the converter with an input frequency that is a sub-multiple of the sample rate and will only exercise a small subset of the possible output codes. The proper method is to pick an M/N frequency for the input sine wave frequency. N is the number of samples in the FFT. M is a prime number between one and N/2. Multiply M/N by the sample rate to obtain the input sine wave frequency. Another scenario that can yield poor results is if you do not have a signal generator capable of ppm frequency ac-curacy or if it cannot be locked to the clock frequency. You can use an FFT with windowing to reduce the “leakage” or spreading of the fundamental, to get a close approximation of the ADC performance. If an amplifier or clock source with poor phase noise is used, the windowing will not improve the SNR.
DC2405A DATA COLLECTION
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DEMO MANUAL DC2405A
Due to the relatively low and somewhat unpredictable sample rate of the DC590/DC2026, its usefulness is lim-ited to noise measurement and data collection of slowly moving signals.
To observe measurements from QuikEval, use a DC590 or program a DC2026 with a DC590 sketch from an Arduino IDE. Then launch QuikEval, a typical data capture and histogram are shown in Figure 3.
DC590/DC2026 DATA COLLECTION
To observe measurements and see example code for read-ing and configuring the LTM2893 from the DC2026, run an Arduino IDE and select File > Sketchbook > Part Number > 2000 > 2800 > 2893 >DC2405A. Upload the program to the DC2026 and launch the Serial Monitor from the tools menu. A brief menu will display on the serial monitor output. Selecting 1 and sending to the DC2026 will result in a single conversion and the result will be displayed in the Serial Monitor window.
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DEMO MANUAL DC2405A
PARTS LISTITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
1 1 C1 CAPACITOR, CERAMIC, 3.3nF 5% 1206 250V NPO TDK/C3216C0G2E332J085AA
2 40 C2, C8, C15, C17, C18, C20, C23-C28, C34, C45-46, C48-71, C73
CAPACITOR, CERAMIC, 100nF 10% 0402 50V X7R TDK/C1005X7R1H104K050BB
3 9 C3, C7, C10-13, C43, C47, C72 CAPACITOR, CERAMIC, 1μF 10% 0603 35V X7R TDK/C1608X7R1V105K080AC
4 4 C4-5, C29, C36 CAPACITOR, CERAMIC, 10μF 10% 1206 35V X7R TDK/C3216X7R1V106K160AC
5 0 C6, C9 OPTIONAL
6 1 C14 CAPACITOR, CERAMIC, 47μF 20% 1210 6.3V X7S TDK/C3225X7S0J476M250AC
7 1 C16 CAPACITOR, CERAMIC, 2.2μF 10% 0603 10V X7R TDK/C1608X7R1A225K080AC
8 4 C19, C38, C40, C44 CAPACITOR, CERAMIC, 10μF 10% 0805 16V X6S TDK/C2012X6S1C106K085AC
2 C21-22 CAPACITOR, CERAMIC, 150pF 10% 1808 250V X7R MURATA/GA342QR7GF151KW01L
9 7 C30-32, C35, C37, C39, C41 CAPACITOR, CERAMIC, 10nF 10% 0402 50V X7R TDK/C1005X7R1H103K050BB
10 1 C33 CAPACITOR, CERAMIC, 1μF 10% 1206 100V X7R TDK/C3216X7R2A105K160AA
11 1 C42 CAPACITOR, TANTALUM, 47μF 10% 2413 16V KEMET/T494C476K016AT
12 2 D1-2 DIODE, ARRAY, 75V 215mA SOT363 DIODES INC/BAV99DW-7-F
13 2 J1-2 CONNECTOR, BNC JACK, EDGE MOUNT TE CONNECTIVITY/1274727-1
14 1 J3 HEADER, 2 × 7 2mm SHROUDED MOLEX/87831-1420
15 3 JP1-3 HEADER, LOOP 1 × 2, 0.2mm AAVID/125700D00000G
16 3 JP4-5, JP7 HEADER, 1 × 3, 2mm WURTH/62000311121
17 3 JP4-5, JP7 SHUNT, 1 × 2, 2mm WURTH/60800213421
18 1 JP6 HEADER, 2 ×5, 0.1mm WURTH/61301021121
19 2 L1-2 INDUCTOR, COUPLED, 22μH 3 × 3mm 1.9Ω 0.44A COILCRAFT/LPD3015-223MRB
20 6 MH1-6 STANDOFF, NYLON 0.25" KEYSTONE, 8831 (SNAP ON)
21 2 R3-4 RESISTOR, 0Ω 1% 0603 VISHAY/CRCW06030000Z0EA
22 1 R2 OPTIONAL
23 3 R9-10, R35 RESISTOR, 1kΩ 1% 0603 VISHAY/CRCW06031K00FKEA
24 4 R7-8, R12, R25 RESISTOR, 33Ω 1% 0402 VISHAY/CRCW040233R0FKED
25 1 R11 RESISTOR, 49.9Ω 1% 1206 VISHAY/CRCW120649R9FKEA
26 1 R6 RESISTOR, 28kΩ 1% 0603 VISHAY/CRCW060328K0FKEA
27 1 R5 RESISTOR, 49.9kΩ 1% 0603 VISHAY/CRCW060349K9FKEA
28 7 R13, R16, R22, R36-38, R40 RESISTOR, 4.99kΩ 1% 0603 VISHAY/CRCW06034K99FKEA
29 14 R14-15, R17-21, R24, R26, R28, R31-33, R34
RESISTOR, 10kΩ 1% 0402 VISHAY/CRCW040210K0FKED
30 2 R1, R23 RESISTOR, 100kΩ 1% 0603 VISHAY/CRCW0603100RFKEA
31 3 R27, R29-30 RESISTOR, 100kΩ 1% 0402 VISHAY/CRCW0402100KFKED
32 1 R39 RESISTOR, 2kΩ 1% 0603 VISHAY/CRCW06032K00FKEA
33 11 RA1-11 RESISTOR ARRAY, 33kΩ 4 RES 1206 PANASONIC/EXB-38V330JV
34 1 TR1 TRANSFORMER, 5kV 2:1 WURTH/750313626
35 1 U1 IC, 100MHz ADC-SPI ISOLATOR LINEAR TECH/LTM2893CY#PBF
36 1 U2 IC, OPAMP LINEAR TECH/LT1468CS8#PBF
37 1 U3 IC, ADC, 1MSPS, 18-BIT, BIPOLAR, ±10.24V LINEAR TECH/LTC2328CMS-18#PBF
38 1 U4 IC, PUSH-PULL DC/DC DRIVER, 1A, 1MHz LINEAR TECH/LT3999EMSE#PBF
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DEMO MANUAL DC2405A
PARTS LISTITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
39 1 U5 IC, BUS SWITCH, SPST, SC70-5 FAIRCHILD SEMI/NC7SZ66P5X
40 1 U6 IC, INVERTER, SC70-5 FAIRCHILD SEMI/NC7SZ04P5X
41 1 U7 IC, D-TYPE POS TRG, MSOP8 ON SEMI/NL17SZ74USG
42 2 U8-9 IC, UNBUFFERED INVERTER, SC70-5 FAIRCHILD SEMI/NC7SVU04P5X
43 1 U10 IC, FPGA/CPLD 130 I/O 169UBGA ALTERA/10M08SAU169C8GES
44 2 U11-12 IC, LDO, 15V, 100mA LINEAR TECH/LT3060ETS8-15#PBF
45 2 U13-14 IC, LDO, 5V, 100mA LINEAR TECH/LT1761ES5-5#PBF
46 1 U15 IC, LDO, 3.3V, 500mA LINEAR TECH/LT1763CDE-3.3#PBF
47 1 U16 IC, BUFFER, TRI-STATE, QUAD, 14TSSOP NXP/74LVT126PW,118
48 2 U17-18 IC, BUS TRANSCEIVER, TRI-STATE, SOT-563 TI/SN74LVC1T45DRLR
49 1 U19 IC, EEPROM, 2-KBIT, I2C, 8TSSOP MICROCHIP/24LC024-I/ST
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DEMO MANUAL DC2405A
SCHEMATIC DIAGRAM
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110
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0
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U13
LT17
61-5
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C38
10uF
C37
10nF
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100n
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100n
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A1
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1
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SWB 10
SYNC 8ILIM/SS 9
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99
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28k
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C34
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C33
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11dc2405af
DEMO MANUAL DC2405A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAM
SD
AS
CL
TMS
TCK
TDO
TDI
2 4 6 8 10 12 14
1 3 5 7 9 11 13
J3Q
EV
AL
47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99454341393735333129272523211917151311975312 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
J4
AB
CD
EF
GH
AB
CD
EF
GH
4 5 6 7 8 9 10
4 5 6 7 8 9 10
IJ
KL
IJ
KL
1 2 3
1 2 3
R38
4.99
k
3V3
R39
2k
SC
L6
SD
A5
WP
7A
01
A1
2
A2
3
VC
C8
VS
S4
U19
24LC
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364.
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4.99
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N
Q_S
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Q_S
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Q_C
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D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
CLK
OU
T
BA
NK
1A
, 1B IO
E5
E5
IOD
1D
1
IOG
1G
1
IOH
1H
1
IOG
2G
2
IOC
2C
2
IOE
3E
3
IOE
4E
4
IOF5
F5
IOF4
F4
IOH
2H
2
IOG
4G
4
IOF6
F6
IOH
3H
3
IOF1
F1
IOB
1B
1
IOC
1C
1
IOE
1E
1
U10
:A
10M
08S
AU
169C
8GES
BA
NK
2
ION
2N
2IO
G5
G5
IOL1
L1
ION
3N
3
IOL2
L2
IOJ1
J1
IOH
6H
6
IOJ2
J2
IOM
3M
3
IOL3
L3
IOK
2K
2
IOK
1K
1
IOH
4H
4
IOM
1M
1
IOH
5H
5
IOM
2M
2
U10
:B
10M
08S
AU
169C
8GES
BA
NK
3
IOM
9M
9IO
L5L5
IOJ7
J7
ION
11N
11
IOK
7K
7
IOM
4M
4
IOL4
L4
IOM
5M
5
ION
12N
12
ION
10N
10
IOM
12M
12
IOM
13M
13
IOJ5
J5
ION
4N
4
IOK
5K
5
ION
5N
5
ION
6N
6
ION
7N
7
IOM
7M
7
IOM
8M
8
IOJ6
J6
ION
8N
8
IOK
6K
6
ION
9N
9
IOM
11M
11
IOL1
1L1
1
IOJ8
J8
IOM
10M
10
IOL1
0L1
0
IOK
8K
8
U10
:C
10M
08S
AU
169C
8GES
BA
NK
5
IOJ9
J9IO
K10
K10
IOJ1
3J1
3
IOH
10H
10
IOH
13H
13
IOK
11K
11
IOJ1
0J1
0
IOL1
2L1
2
IOH
9H
9
IOH
8H
8
IOG
12G
12
IOG
13G
13
IOJ1
2J1
2
IOL1
3L1
3
IOK
12K
12
IOK
13K
13
U10
:D
10M
08S
AU
169C
8GES
BA
NK
6 IOB
12B
12IO
G9
G9
IOE
9E
9
IOB
11B
11
IOC
12C
12
IOG
10G
10
IOF1
3F1
3
IOE
13E
13
IOB
13B
13
IOA
12A
12
IOE
10E
10
IOC
11C
11
IOF9
F9
IOE
12E
12
IOF1
2F1
2
IOD
13D
13
IOF1
0F1
0
IOC
13C
13
IOF8
F8
IOD
9D
9
IOD
12D
12
IOD
11D
11
U10
:E
10M
08S
AU
169C
8GES
BA
NK
8
IOA
6A
6IO
C10
C10
IOB
6B
6
IOA
4A
4
IOB
5B
5
IOA
8A
8
IOC
9C
9
IOA
9A
9
IOA
3A
3
IOB
3B
3
IOD
6D
6
IOE
6E
6
IOB
9B
9
IOA
10A
10
IOB
10B
10
IOA
11A
11
IOD
8D
8
IOE
8E
8
IOB
7B
7
IOE
7E
7
IOA
7A
7
IOD
7D
7
IOB
4B
4
IOC
4C
4
IOA
5A
5
IOC
5C
5
IOB
2B
2
IOA
2A
2
U10
:F
10M
08S
AU
169C
8GES
PW
R/G
ND
AD
C_V
REF
D3
GN
DA
1V
CC
_ON
EF7
GN
DA
13
GN
DB
8
VC
CIO
1AF2
GN
DC
3
VC
C_O
NE
G6
VC
C_O
NE
G8
VC
C_O
NE
H7
VC
CIO
3L6
GN
DD
5
VC
CIO
2K
3G
ND
N13
GN
DN
1V
CC
IO1B
G3
GN
DF3
VC
CIO
2J3
GN
DH
12G
ND
G7
RE
FGN
DE
2
GN
DE
11
GN
DJ4
GN
DL9
GN
DM
6
AN
AIN
1D
2
VC
CA
3D
4V
CC
A2
D10
VC
CA
1K
4
VC
CA
4K
9
VC
CIO
3L7
VC
CIO
3L8
VC
CIO
5H
11
VC
CIO
5J1
1
VC
CIO
6F1
1
VC
CIO
6G
11
VC
CIO
8C
6
VC
CIO
8C
7
VC
CIO
8C
8
U10
:G
10M
08S
AU
169C
8GES
C67
100n
F
C63
100n
F
C55
100n
F
C70
100n
F
C59
100n
F
C62
100n
F
C69
100n
F
C66
100n
F
C60
100n
F
C61
100n
F
C57
100n
F
C56
100n
F
C54
100n
F
C53
100n
F
C65
100n
F
C50
100n
F
C51
100n
F
C49
100n
F
C48
100n
F
C46
100n
F
C68
100n
F
C58
100n
F
3V3
Q_E
N
12
34
56
78
910
JP6
R31
10k
3V3
R28
10k
JTA
GEN
R35
1k
3V3
CN
VS
T_33
CLK
D1
D0
D5
D2
D4
D6
C72
1uF
D3
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
CLK
OU
T
SA
SB
SC
SC
K
CS
SD
I
CS
C
CN
V
SD
OA
SD
OB
FAU
LT
BU
SY
Q_S
DI
Q_S
CK
Q_C
S
Q_S
DO
Q_S
CK
R24
10k
R14
10k
R18
10k
R21
10k
R19
10k
R17
10k
R15
10k
3V3
3V3
CFGD
CRC
3V3
CLRCFG
3V3
3V3
3V3
STAT
3V3
SC
LS
DA
QSDO
QSDIQSCKQCS
QSPR
EC
OR
EV
AP
PR
OV
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DA
TED
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CR
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ON
CLK
2
CLK
2
QEN
Q_D
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JP4
CO
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G
10
JP5
OE O
N
OFF
Q_S
PA
RE
231
564
9810
121113
U16
74LV
T126
R20
10k
3V3
Q_S
PA
RE
Q_S
PA
RE
_DIR
34
1
6
5
2
U17
LVC
1T45
34
1
6
5
2
U18
LVC
1T45
Q_S
PA
RE
_DIR
3V3
R33
10k
R22
4.99
k
C45 10
0nF
R3410k
3V33V3
C52
100n
F
C64
100n
F
C71
100n
F
3V3
-2
2ND
PR
OTO
TYP
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B11
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5
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KWB
Wed
nesd
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th, 2
015
22
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DE
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TER
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R23 100
C47 1u
F
R3210k
QDIR
RA
5:B
33
RA
5:A
33R
A5:
C33
RA
5:D
33
RA
11:A
33RA
11:B
33
RA
11:C
33 RA
11:D
33
RA
10:A
33
RA
10:B
33
RA
10:C
33
RA
10:D
33
RA
9:A
33
RA
9:B
33
RA
9:C
33
RA
9:D
33
RA
8:A
33 RA
8:B
33RA
8:C
33
RA
8:D
33
RA
7:A
33
RA
7:B
33
RA
7:C
33
RA
7:D
33
RA
6:B
33
RA
6:A
33
RA
6:C
33RA
6:D
33
RA
4:D
33 RA
4:B
33
RA
4:A
33
RA
4:C
33
RA
1:B
33
RA
1:A
33
RA
1:D
33 RA
1:C
33
RA
2:A
33
RA
2:B
33
RA
2:C
33
RA
2:D
33 RA
3:A
33 RA
3:B
33
RA
3:C
33
RA
3:D
33
R27
100k
R30
100k
R29
100k
R26
10k
3V3
12dc2405af
DEMO MANUAL DC2405A
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2016
LT 0516 • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
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