comparison of high power non-isolated multilevel dc-dc

Laboratory for High Power Electronic Systems

Comparison of High Power Non-Isolated Multilevel DC-DCConverters for Medium-Voltage Battery Storage Applications

Optimization Results

Abstract

Module Design & ConclusionOptimal Design of 4L-FC for Nominal Load

Multi-Level Converter Topologies

sccermobilitySwiss Competence Center for Energy ResearchEfficient Technologies and Systems for Mobility

High currents flowing through capacitors C1 and C2.

VC1 > Vin for proper operation.

Diodes DC1− DC6 are low current devices used forclamping only.

Two level operation identical to basic buck-boostoperation.

Milos Stojadinovic, Jürgen BielaLaboratory for High Power Electronic SystemsPhysikstrasse 38092 Zürich, Switzerlandstojadinovic@hpe.ee.ethz.ch

Frequency multiplication of the inductor current ripple(i.e. lower inductance compared to NPC topology).

In this paper 4-level neutral-point-clamped (4L-NPC), 4-level flying-capacitor (4L-FC) and 4-level neutral-point clamped Cuk (4L-NPC-Cuk) converter topologies for multilevel DC-DC buck-boost converter for medium-voltage battery storage applications are compared with respect to effi-ciency and power density. The comprehensive comparison is performed with multi domain models and optimization procedures. For the converters, pareto-fronts are calculated for differ-ent operating frequencies in order to find the optimal design with respect to the specifiedminimum efficiency.

Optimal Inductor Design for the 4L-FC Circuit. Resulting System with 8 Interleaved Modules.

Core Material METGLAS2605SA1115 µH95.000 x 0.36 mm 1.8 A/mm2

357 W

InductanceNumber of TurnsHF Litz WireCurrent DensityTotal Losses

75 KTemperature Rise25 °CAmbient Temperature

Battery Voltage Vin 530 ... 890 V2800 V4 MW

DC Link Voltage Vout

System PowerEfficiency > 95 %

Specifications

Core

Capacitor BankSemiconductors

Heat Sink

Gate Driver /Control Board

Winding

+-

L

S1

S2

S4

S3

C1C2

S5

S6

Vin

C3D1

D2

D4

D3

D5

D6

RVC1VC2 Vout

L

S1

S2

S4

S3

C1

S5

S6

D1

D2

D4

D3

D5

D6

Vin

VR

L

S1

S2

S4

S3

C1 C2

S5

S6

C3

D1

D2

D4

D3

D5

D6

+-

· · ·

· · ·

· · ·

· · ·

out

BidirectionalDC-DC

Converter

Battery Storage

AC-DCMultilevelRectifier

Wind TurbineMVDC

DC-DCConverter

PV Plant

DC-ACMultilevel

Inverter

Utility

4 MW

438 dm3

9.13 kW/dm3

Power (8 Modules Interleaved)

VolumePower Density

45 °CAmbient Temperature

97.4 %Maximum Efficiency

25 °CCooling Water Temperature

500 kWModule Power5000 HzFrequency

LFCLNPC

13= 2Vin

Vout - Vin(. 1 - )

+-

Auxiliary diodes

L

S1

S2

S4

S3

S5

S6

Vin

D1

D2

D4

D3

D5

D6

R Vout

DC1

DC2

DC3

DC4

DC5

DC6

C1

C2

C3

Heat Sink

IGBT M

odules

Capacitor Bank

Inductor Volume

160

140

120

100

80

60

40

20

0

Volu

me

[dm

³]

Heat Sink

IGBT M

odules

Capacitor Bank

Inductor Volume

Heat Sink

IGBT M

odules

Capacitor Bank

Inductor Volume

fS = 6kHzL = 1.38mH

fS = 6kHz fS = 5kHzL = 108µH

139.5

0.9 4.2 3

25.4

9.74.2 3

16.88.4 4.2 3

4L NPC CUK4L NPC 4L FC

Component volume comparison.

Example circuit schematic of the modular systemwith 4L-FC topology (8 interleaved modules).

Specification of the ParametersVin / Vout / Pout / Dmax

TT,max / Tcore,max / TA / Rth,IGBT

Electrical Model of the ConverterCurrents / Voltages / Flux Density

Initial ValueSwitching Frequency fsw

Winding & Core Lossesin the Inductor

as Function of Geometry

Minimization of Ind. LossesConstraints: BBmax

VolVolmax // JJmax

Losses in Semiconductors

Heat SinkScaling : RthRth,max

Global Optimization AlgorithmMinimization of Losses and Volume of the System

Optimal Design

Modification of the Values

InnerOptimization

Loop

Inductor Thermal ModelT<Tmax

Mod

ifica

tion

of th

e Va

lues

Optimization procedure with an inner loop for inductoroptimization.

0 2 4 6 8 10 12 14 16 1894.5

95

95.5

96

96.5

97

97.5

98

98.5

Power Density [kW/dm3]

Syst

em E

ffic

ienc

y [%

]

3kHz

4kHz

5kHz

2kHz270mH

3kHz180mH

4kHz135mH

5kHz108mH

2kHz4.14mH

3kHz2.76mH

4kHz2.07mH5kHz1.66mH

6kHz1.38mH

1000Hz6.2mH

Buck-Boost

4L-NPC

4L-FC4L-NPC-Cuk

6kHz

Pareto-fronts.

2800V, 500kWTamb=45ºC, Twater=25ºC

1400V, 25kWTamb=45ºC, Twater=25ºC

2800V, 100kWTamb=45ºC, Twater=25ºC

1400V, 100kWTamb=45ºC, Twater=25ºC

1400V, 500kWTamb=45ºC, Twater=25ºC

10 11 12 13 14 15 16 17 18 1994.5

95

95.5

96

96.5

97

97.5

98

Power Density [kW/dm 3]

Syst

em E

ffic

ienc

y [%

]

2800V, 25kWTamb=45ºC, Twater=25ºC

6 8 10 12 14 16 18

3kHz191mH

4kHz143mH

5kHz115mH

500Hz1.15mH 1kHz

574mH 1.5kHz382mH 2kHz

287mH2.5kHz230mH

Power Density [kW/dm3]

Syst

em E

ffic

ienc

y [%

]

5kHz, 115mHSwitching Losses 1/2nTamb=Twater=60ºC

2.5kHz, 230mHConvection Coef. 2nTamb=Twater=60ºC

2.5kHz, 230mHCore Losses 1/2nTamb=Twater=60ºC

2.5kHz, 230mHThermal Conductivityof Winding Isolation 2nTamb=Twater=60ºC

2.5kHz, 230mHThermal Conductivityof Core Material 2nTamb=Twater=60ºC

No ModificationsTamb=Twater=60ºC

Ambient and Water Temp.Tamb=45ºC, Twater=25ºC

4kHz, 143mHConduction Losses 1/2nTamb=Twater=60ºC

94.5

95

95.5

96

96.5

97

97.5

98

98.5

System pareto-fronts for the 4L-FC converter withscaled operating points.

Pareto front with the added points resulting from thetechnology value modifications for the 4L-FC converter

+-

C1

Auxiliary diodes

L1

S1

S2

S4

S3

S5

S6

Vin

D1

D2

D4

D3

D5

D6

RVout

DC1

DC2

DC3

DC4

DC5

DC6

L2

C2

C3

C4

C5

Reduced inductor size due to coupling compared toregular NPC topology.

Current ripple reduction sensitive to magneticcomponent parameter change.

Larger volume of the capacitor bank compared toregular NPC topology.

Heat Transfer Coefficient 2x increase2x increase2x increase2x decrease

2x decreaseT=60 °C → 45 °C

Thermal Conductivity of Core MaterialThermal Conductivity of WindingCore Losses

Semiconductor Switching LossesTemperature of the Ambientand Cooling Water

2x decreaseSemiconductor Conduction Losses

T=60 °C → 25 °C

Modified Technologies for the Sensitivity Analysis.

77 cm

79 cm

72 cm

12.8 cm

25.7 cm

35.6

cm

4-Level Neutral-Point Clamped Topology (4L-NPC) 4-Level Neutral Point Clamped Cuk Topology (4L-NPC Cuk) 4-Level Flying-Capacitor Topology (4L-FC)

Simplified Mechanical Drawing of a Single Moduleof the 4L-FC Interleaved System

In this paper, 4L-NPC, 4L-FC and 4L-NPC-Cuk converters are evaluated with respect to power density and efficiency for medium-voltage battery storage applications.

4L-FC topology results in the most compact system.

From the sensitivity analysis, biggest increase of the power density is achieved by investing in a better colling system and more efficient switching compo-nents.

From the scalability analysis, further volume reduc-tions can be achieved by properly selecting the module power level.

System Design

Sensitivity Analysis Scalability AnalysisResults for Nominal ConditionsOptimization Algorithm

Semiconductors

METGLAS2605SA1Cornell Dubilier 944U

AavFin Liquid Cold Plates

CapacitorsCore MaterialHeat Sink

Infineon FZ1600R17HP4Components

Output Power 4 MW530 V2800 V

Input VoltageOutput Voltage

Nominal Conditions

Sensitivity Analysis: Modification of the technology values and the influence it has on power density of the system.

Scalability Analysis: Reduction in the module power and output voltage values and the influence it has on power density of the system.