altera de2 board and quartus ii software ece 3450 m. a. jupina, vu, 2014
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Altera DE2 Board and
Quartus II Software
ECE 3450 M. A. Jupina, VU, 2014
Lecture Objective
An overview of the Altera DE2 board and the Quartus II software. Course projects will use the Altera FPLD boards as a platform to implement complicated digital systems. With the Quartus II software, you will use a system design approach to create your designs.
References:1. Fundamentals of Digital Logic, Sections 2.9, 2.10, 3.5 – 3.7, and Appendices A-E.2. Document files at the course web site
ECE 3450 M. A. Jupina, VU, 2012
The Altera DE2 Development Board
ECE 3450 M. A. Jupina, VU, 2012
In-System Programming of the Altera Development Board
ECE 3450 M. A. Jupina, VU, 2012
Connections Between the Pushbuttons, the LEDs, and the Altera FPGA
Figure 1.6 FPGA I/O connections to Pushbuttons (PBx) and LED: Right of center, active LOW LED
output (i.e., UP1 and UP2 boards) or on far right active HIGH LED output (i.e., DE1, DE2, and UP3
boards). Note that a depressed pushbutton input will be LOW.
ECE 3450 M. A. Jupina, VU, 2012
9V DC PowerSupply
Connector
27Mhz Oscillator24-bit Audio CODEC
TV Decoder(NTSC/PAL)
PowerON/OFFSwitch USB
Host/SlaveController
Altera USB BlasterController Chipset
Altera EPCS 16Configuration Device
RUN/PROGSwitch forJTAG/AS
Modes
LCD 16x2 Module
7-SEG Display Module
18 Red LEDs
18 Toggle Switches
1MB FlashMemory
(upgradable to4MB)
PS/2 Port
XSGA10-bit DAC
Ethernet 10/100MController
SD Card Connector
IrDATransceiver8 Green LEDs
SMAExtClk
4 Push-button Switches
90nmCyclone IIFPGA with35K LEs
RS-232Port
Ethernet10/100M Port
XSGAVideo Port
VideoIn
USBHost
LineIn
MicOut
MicInUSB
Device
USBBlaster
Port
50Mhz Oscillator
8MB SDRAM
512KB SRAM
88888888
Figure 1.16 Altera DE2 board showing the Pushbutton and LED locations used in design (enclosed
in dashed ellipses seen in bottom right).
ECE 3450 M. A. Jupina, VU, 2012
Examples of Dedicated Pin-Outs on the DE2 Cyclone II Chip
Table 1.2 Hardwired I/O connections on the various FPGA boards in the design example.
I/O Device DE1 Pin DE2 Pin UP3 Pin UP2 & 1 Pin
PB1 R21 (Key1) N23 (Key1) 62 (SW7) 28 (FLEX PB1)
PB2 T22 (Key2) P23 (Key2) 48 (SW4) 29 (FLEX PB2)
LED R20(LEDR0) AE23(LEDR0) 56 (D3) 14 (7Seg Dec. pt.)
ECE 3450 M. A. Jupina, VU, 2012
Required Installation of Quartus II on Laptops Go to the ECE3450 folder on the K:\ Drive.
Download the executable file 91_quartus_free to your laptop’s hard drive. Install the Quartus II software.
After Installation, run the Quartus II software. Go to the menu Tools, License Setup, and in the box for License File put the following 5282@153.104.45.65 so that your laptop can find the license on the ECE server.
ECE 3450 M. A. Jupina, VU, 2014
Design Process for Schematic or VHDL Entry
ECE 3450 M. A. Jupina, VU, 2014
Create/Edit Schematic/VHDL
Compilerrepeat until no errors
Create Simulation Waveforms
SimulatorRun simulation until functionally correct
Timing Analysis?Modify design until timing specs are met
Program Device
Design Implementation Methodology
ECE 3450 M. A. Jupina, VU, 2014
Creating a New Quartus II Project
ECE 3450 M. A. Jupina, VU, 2014
Setting the FPGA Device Type
The Cyclone II Chip resides on the DE2 Board.
Figure 1.9 Setting the FPGA Device Type. Settings shown are for the DE1 board.
DE2
Cyclone II
EP2C35F672C6
ECE 3450 M. A. Jupina, VU, 2014
Creating the Top-Level Project Schematic Design File
ECE 3450 M. A. Jupina, VU, 2014
Selecting a New Symbol with the Symbol Tool
ECE 3450 M. A. Jupina, VU, 2014
Active Low OR-Gate Schematic Example with I/O Pins Connected
ECE 3450 M. A. Jupina, VU, 2014
Assigning Pins with the Assignment Editor
ECE 3450 M. A. Jupina, VU, 2014
Active Low OR-Gate Timing Simulation with Time Delays
ECE 3450 M. A. Jupina, VU, 2014
VHDL Entity Declaration Text
ECE 3450 M. A. Jupina, VU, 2014
VHDL OR-Gate Model (with Syntax Error)
ECE 3450 M. A. Jupina, VU, 2014
VHDL Compilation with a Syntax Error
ECE 3450 M. A. Jupina, VU, 2014
Timing Analyzer Showing Input to Output Timing Delays
ECE 3450 M. A. Jupina, VU, 2014
Floorplan View Showing Internal FPGA Placement of OR-
Gate in LE and I/O Pins
ECE 3450 M. A. Jupina, VU, 2014
ORgate Design Symbol
orgate
inst
PB1PB1
PB2PB2
LEDLED
ECE 3450 M. A. Jupina, VU, 2014
Implementation of a Simple Processor
Data
IEA IEB IECClock
RA RB RC IEX RX
Multiplexer
SY
SDATA
SA
SC SB
ALU
IEY RY
StateMachine
IEA IEB IEC
SC
SDATA
SA
SB
Done
IEX IEY
AddSub SY
Bus
AddSub
Start
ECE 3450 M. A. Jupina, VU, 2014
Altera Implementation of Simple Processor
ECE 3450 M. A. Jupina, VU, 2014
An Example Design Illustrating the Mapping of Multi-Bit Connections
ECE 3450 M. A. Jupina, VU, 2014
An Example with a LPM Device
ECE 3450 M. A. Jupina, VU, 2014
Lpm_counter0 MegaWizard Edit Window
ECE 3450 M. A. Jupina, VU, 2014
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