a system-level stochastic benchmark circuit generator for fpga architecture research

A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture ResearchCindy Mark

Prof. Steve WiltonUniversity of British ColumbiaSupported by Altera and NSERC

Introduction: Overview FPGA architecture studies require benchmark circuits

Realistic, big, and varied Current circuits are small

MCNC: 24 LE to 7694 LE Stratix III: 19,000 LE to 135,200 LE Alternatives

ASIC: requires conversion Synthetic: designed for sizes similar to MCNC circuits

Contribution: SOC synthetic circuit generator Glues modules into realistic, big netlists Allows customization of the circuit content

Research Approach

Survey of Circuit Designs

Generator Development

Circuit Characterization: Survey 66 Block Diagrams

24 industrial 42 academic

Applications: Communication Multimedia Processor

Circuit Model Leaf Modules

Processor Interface Controller Cores

Networks Bus Dataflow Star

Leaf modules connected by networks Networks are hierarchical, and arranged in a tree

Circuit Model: Example

BUS

BUS CPU

CORE CORE CORE

CORE

0 1 2 30

10

20

30

40

50

Hierarchy Depth

Num

ber o

f Circ

uits

Circuit Characterization: Trends

Hierarchy Depth Distribution

1 2 3 4

1 2 3 4 5 60

4

8

12

16

20

Number of Networks

Num

ber o

f Circ

uits

Circuit Characterization: Trends

Max Hier. Depth

Average # Networks

1 1

2 1.81

3 1.75

4 2.16

Network # Distribution on Level 2

2 3 4 5 7 130

1

2

3

4

5

Num

ber o

f Net

wor

ks

Number of Blocks

0 1 2 3 4 5 6 7 9 101112 170

5

10

15

20

Num

ber o

f Net

wor

ks

Number of Blocks

Circuit Characterization: Trends

Number of Modules per Bus

Number of Modules per Dataflow

Number of Modules per Star

0 5 10 150

3

6

9

12

Num

ber o

f Net

wor

ks

Number of Blocks

Generation

Circuit Generator: Overview

Constraints file: # hierarchy levels, # blocks, # networks, bus width Can specify any combination

One BLIF library directory per module type

BLIF libraries

Complete Circuit

Definition

InterfaceGenerator

BLIF CircuitGenerator

Constraints

Circuit Generation: Example

0 1 2 30

10

20

30

40

50

Hierarchy Depth

Num

ber o

f Circ

uits

Pro

babi

lity

0

0.2

0.4

0.6

0.8

1

1 2 3 4

Circuit Generator: Implementation Modules

MCNC OpenCores Synthetic

Networks Bus: AMBA single master Dataflow: with feedback Star: no feedback

Circuit Generator: Implementation

Reset Interrupt

Where are the fine grained connections? Some generated through the network process

Comparison: Overview

Evaluation of SOC circuits as they scale

Comparison to other synthetic generators GEN: purely combinational GNL: FFs and IOs

Characteristics Post-Routing: channel width, wirelength, crit. path

Results: Locality

GNL New

Results: Average Wirelength

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Wire

leng

th

NEW GEN GNL

Results: Channel Width

0

20

40

60

80

100

120

140

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Cha

nnel

Wid

th

NEW GEN GNL

Results: Critical Path Delay

0.00

20.00

40.00

60.00

80.00

100.00

120.00

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Crit

ical

Pat

h (n

s)

NEW GEN GNL

Conclusion: Limitations

High number of IO pins Caused by star networks Mismatch between bus width and module IO pins Head and tail of dataflow networks

Conclusion: Ongoing work

Add different block types (memory) Add different network types Improve the modeling of reset, interrupt Improve the modeling of blocks

Conclusion: Status

Can generate circuits 150k LE and up Works on Linux / Windows

Works better on Linux Manual Available for download:

www.ece.ubc.ca/~cindym/

Conclusion: Summary

We have developed a synthetic SOC circuit generator suitable for architectural research Based on an analysis of published block diagrams Assumes a tree-like network hierarchy that

connects existing BLIF blocks Resulting circuits, in general, display slower

growth in complexity and post-routing characteristics relative to GEN and GNL.

Thank You!

Results: Rent Parameter

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Ren

t Par

amet

er

NEW GEN GNL

Results: Nets (post-clustering)

0

10000

20000

30000

40000

50000

60000

70000

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Net

s

NEW GEN GNL