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A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research Cindy Mark Prof. Steve Wilton University of British Columbia Supported by Altera and NSERC

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A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research. Cindy Mark Prof. Steve Wilton University of British Columbia Supported by Altera and NSERC. Introduction: Overview. FPGA architecture studies require benchmark circuits Realistic, big, and varied - PowerPoint PPT Presentation

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Page 1: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture ResearchCindy Mark

Prof. Steve WiltonUniversity of British ColumbiaSupported by Altera and NSERC

Page 2: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Introduction: Overview FPGA architecture studies require benchmark circuits

Realistic, big, and varied Current circuits are small

MCNC: 24 LE to 7694 LE Stratix III: 19,000 LE to 135,200 LE Alternatives

ASIC: requires conversion Synthetic: designed for sizes similar to MCNC circuits

Contribution: SOC synthetic circuit generator Glues modules into realistic, big netlists Allows customization of the circuit content

Page 3: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Research Approach

Survey of Circuit Designs

Generator Development

Page 4: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Circuit Characterization: Survey 66 Block Diagrams

24 industrial 42 academic

Applications: Communication Multimedia Processor

Page 5: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Circuit Model Leaf Modules

Processor Interface Controller Cores

Networks Bus Dataflow Star

Leaf modules connected by networks Networks are hierarchical, and arranged in a tree

Page 6: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Circuit Model: Example

BUS

BUS CPU

CORE CORE CORE

CORE

Page 7: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

0 1 2 30

10

20

30

40

50

Hierarchy Depth

Num

ber o

f Circ

uits

Circuit Characterization: Trends

Hierarchy Depth Distribution

1 2 3 4

Page 8: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

1 2 3 4 5 60

4

8

12

16

20

Number of Networks

Num

ber o

f Circ

uits

Circuit Characterization: Trends

Max Hier. Depth

Average # Networks

1 1

2 1.81

3 1.75

4 2.16

Network # Distribution on Level 2

Page 9: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

2 3 4 5 7 130

1

2

3

4

5

Num

ber o

f Net

wor

ks

Number of Blocks

0 1 2 3 4 5 6 7 9 101112 170

5

10

15

20

Num

ber o

f Net

wor

ks

Number of Blocks

Circuit Characterization: Trends

Number of Modules per Bus

Number of Modules per Dataflow

Number of Modules per Star

0 5 10 150

3

6

9

12

Num

ber o

f Net

wor

ks

Number of Blocks

Page 10: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Generation

Page 11: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Circuit Generator: Overview

Constraints file: # hierarchy levels, # blocks, # networks, bus width Can specify any combination

One BLIF library directory per module type

BLIF libraries

Complete Circuit

Definition

InterfaceGenerator

BLIF CircuitGenerator

Constraints

Page 12: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Circuit Generation: Example

0 1 2 30

10

20

30

40

50

Hierarchy Depth

Num

ber o

f Circ

uits

Pro

babi

lity

0

0.2

0.4

0.6

0.8

1

1 2 3 4

Page 13: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Circuit Generator: Implementation Modules

MCNC OpenCores Synthetic

Networks Bus: AMBA single master Dataflow: with feedback Star: no feedback

Page 14: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Circuit Generator: Implementation

Reset Interrupt

Where are the fine grained connections? Some generated through the network process

Page 15: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Comparison: Overview

Evaluation of SOC circuits as they scale

Comparison to other synthetic generators GEN: purely combinational GNL: FFs and IOs

Characteristics Post-Routing: channel width, wirelength, crit. path

Page 16: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Results: Locality

GNL New

Page 17: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Results: Average Wirelength

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Wire

leng

th

NEW GEN GNL

Page 18: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Results: Channel Width

0

20

40

60

80

100

120

140

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Cha

nnel

Wid

th

NEW GEN GNL

Page 19: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Results: Critical Path Delay

0.00

20.00

40.00

60.00

80.00

100.00

120.00

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Crit

ical

Pat

h (n

s)

NEW GEN GNL

Page 20: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Conclusion: Limitations

High number of IO pins Caused by star networks Mismatch between bus width and module IO pins Head and tail of dataflow networks

Page 21: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Conclusion: Ongoing work

Add different block types (memory) Add different network types Improve the modeling of reset, interrupt Improve the modeling of blocks

Page 22: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Conclusion: Status

Can generate circuits 150k LE and up Works on Linux / Windows

Works better on Linux Manual Available for download:

www.ece.ubc.ca/~cindym/

Page 23: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Conclusion: Summary

We have developed a synthetic SOC circuit generator suitable for architectural research Based on an analysis of published block diagrams Assumes a tree-like network hierarchy that

connects existing BLIF blocks Resulting circuits, in general, display slower

growth in complexity and post-routing characteristics relative to GEN and GNL.

Page 24: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Thank You!

Page 25: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Results: Rent Parameter

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Ren

t Par

amet

er

NEW GEN GNL

Page 26: A System-Level Stochastic Benchmark Circuit Generator for FPGA Architecture Research

Results: Nets (post-clustering)

0

10000

20000

30000

40000

50000

60000

70000

0 10000 20000 30000 40000 50000 60000

Size of Circuit

Net

s

NEW GEN GNL


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