5 09-40 hstse581-11 - Промэлектроника · service manual cassette deck receiver...
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HST-SE581AEP Model
E ModelAustralian Model
SERVICE MANUAL
CASSETTE DECK RECEIVER
MICROFILM
Manufactured under license from Dolby LaboratoriesLicensing Corporation.“DOLBY” and the double-D symbol a and “PROLOGIC” are trademarks of Dolby LaboratoriesLicensing Corporation.
• This set is the tuner deck and amplifiersection in SEN-T481.
SPECIFICATIONS
Tape deck Model Name Using Similar Mechanism HST-471
Section Tape Transport Mechanism Type TCM-220WR2
— Continued on next page —
Tuner section
FM stereo, FM / AM superheterodyne tuner
FM tuner sectionTuning range 87.5 – 108.0 MHzAntenna FM leadantenaAntenna terminals 75 Ω unbalancedIntermediate frequency 10.7 MHz
AM tuner sectionTuningrange European model: 531 – 1,602 kHz Other models: 531 – 1,602 kHz (with the interval set at
9 kHz)530 – 1,710 kHz (with the interval set at10kHz)
Antenna AM loop antenna, outdoor antennaterminals
Intermediate frequency450 kHz
Amplifier section
European models:(FRONT)DIN power output 90 + 90 W
(at rear / center / woofer off at 1 kHz, 8 Ω)
Continuous RMS power output110 + 110 W(at rear / center / woofer off at 1 kHz, 10% THD, 8 Ω)70 W / ch(at SURROUND ON at 1 kHz,10% THD, 8 Ω)
(REAR) 40 W(at front / center / woofer off at 1 kHz, 8 Ω)
(CENTER) 40 W(at front / rear / woofer off at 1 kHz, 8 Ω)
(WOOFER) 70 W(at front / rear / center off at 40 Hz, 4 Ω)
Other models:Peak music power output
1,600 W (total)(FRONT)Continuous RMS power output
90 + 90 W(at rear / center / woofer off at 1 kHz,10% THD, 8 Ω)
(REAR) 40 W(at front / center / woofer off at 1 kHz, 8 Ω)
(CENTER) 40 W(at front / rear woofer off at 1 kHz, 8 Ω)
(WOOFER) 70 W(at front /rear/ center off at 40 Hz, 4 Ω)
Inputs PHONO (phono jacks):
sensitivity 2.5 mV, impedance 50 kΩ CD (phono jacks): sensitivity 400 mV, impedance 50 kΩ VIDEO1, 2 (phono jacks):
sensitivity 250 mV, impedance 50 kΩ
HST-SE581
— 13 — — 14 —
5-3. SCHEMATIC DIAGRAM — MAIN SECTION (1/2) — • See page 10 for Waveforms. • See page 39 for IC Block Diagrams.
HST-SE581
— 15 — — 16 —
5-4. SCHEMATIC DIAGRAM — MAIN SECTION (2/2) — • See page 39 for IC Block Diagrams.
HST-SE581
— 21 — — 22 —
5-7. SCHEMATIC DIAGRAM — DISPLAY SECTION — • See page 10 for Waveforms. • See page 41 for IC Pin Function.
HST-SE581
— 25 — — 26 —
5-9. SCHEMATIC DIAGRAM — SW SECTION —
DOLBY NR
1/u
HST-SE581
— 29 — — 30 —
5-11. SCHEMATIC DIAGRAM — POWER AMP SECTION — • See page 39 for IC Block Diagrams.
HST-SE581
— 33 — — 34 —
5-13. SCHEMATIC DIAGRAM — DECK SECTION — • See page 39 for IC Block Diagrams.
HST-SE581
— 37 — — 38 —
5-15. SCHEMATIC DIAGRAM — POWER TRANSFORMER SECTION —
EXCEPTE MODEL
EXCEPTE MODEL
HST-SE581
— 39 — — 40 —
5-16. IC BLOCK DIAGRAMS
IC300 LV1041M (MAIN BOARD)
IC302 LC7822 (MAIN BOARD)
IC401 LC75373ED (MAIN BOARD)
IC502 LB1641 (MAIN BOARD)
12
20
1
2
3456
78
9
10
11
12
13
14
15
16
19
17
18
20
21
3231302928272625
24
23
22
33
44
43
42
41
40393837363534
7374757677787980 72 65666768697071
52
51
5049
48
47
46
45
53
54
55
56575859
60
61
62
63
64
STRIM
OSC
VOL
VOL
VCA VCAP
B
P
B
VCA VCA
VCA VCA VCA VCA
IEVNOISEGEN
NOISEFILTER
BPFCONTROL
CHCONTROL
BPF
V REF
STRIM
SMODE
RECT
RECT
DCCUT
B NR
OUTFILTER
DATADECODERVOL/
MUTE
BPF
RECT
LOGICFF
LOGICFF RECT
C MODE
LOGIC LOGIC
MASTERVOL
NFSW
S
S
S
P P B
B
B B
P
B
CD
R
L
C S
LR
P P
P
B
P
B
P
BP
B
P
B
S
MASTER VOL
VDDPCM
PCMCONTROL
SRAM
INFILTER
R
L
C
S
R
P
B
P
B
PB
PBL
L
R
L
R
R BPF2
R BPF1
S DC OUTC DC OUTR DC OUTL DC OUT
V REFVCC
C OUT
S OUT
R OUT
L OUT
GND
L IN
R IN
S IN
DELAY OUT
C VOL IN
DET
IREF
R OUT
R NF
L NF
L OUT
L BPF2
L BPF1
RT IN
LT IN
DC CUT
C MODE
GNDNS BPF1
OSC
NS BPF2
ENABLE
DATA
CLK
DATA
CLK
ENABLE2
VSS
OSC
OSC
VDD
A/D
NS
D/A
DC CUT
VCC
C VO
L OU
T
C OP
IN
GND
C OP
NF
C OP
OUT
VOL
REF
S OP
OUT
S OP
NF
S OP
IN
S VO
L OU
T
L RECT
DC CUT4
R RECT
DC CUT3
L BPF3
VLR TH
VLR 1
VLR 2
VCS 2
VCS 1
VCS TH
L+R RECT
DC CUT2
L-R RECT
DC CUT1
R DET3
OP V
REF
S VO
L IN
S OU
T
DC C
UT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CONT
ROL LATCH
SHIFT RESISTOR
LEVEL SHIFT
CL
DI
CE
VEE
OUT
IN
OUT
IN
OUT
IN
VSS
S
RESET
VDD
OUT
ININ
OUT
IN
OUT
IN
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
DECODER LATCH SHIFTREGISTER CONTROL
–+
+–
1 2 3 4 5 6 7 8 9 10
20
19
1817161514
13
12
11
21
22
2324252627282930313233
3435363738
39
4041424344
LSELOL4L3L2L1
VDD
R1R2R3R4
RSELO
RVRI
N
RCOM RT
1RT
2
RT3
RTOU
TRS
INRS
1
RS2
RS3
RSOU
T
RFIN
RFOUT
RROUTVSSCLDICE
VREF
LROUT
LFOUT
LFIN
LSOU
T
LS3
LS2
LS1
LSIN
LTOU
T
LT3
LT2
LT1
LCOM
LVRI
N
1 2 3 4 5 6 7 8 9 10
GND
MOT
ORDR
IVE
NOIS
EFI
LTER
CLAM
P
FWD.
IN
REV.
IN
VCC
1
VCC
2
NOIS
EFI
LTER
MOT
ORDR
IVE
MOTORDRIVE
MOTORDRIVE
T.S.D O.C.P
FWD/REV/STOPCONTROL LOGIC
1
2
3
4
5
6
7
8
9
TR3 R1
R2TR4
TR6TR7
R4
R9
TR5
TR1
TR2
R6
D4 D3
R7R8
TR8
D1 D2 R5
R3
INPUT
NF
-VEOUT
+VEOUT
VSS
GND
VCC
SUB
1 2 3 4 5 6 7 8 9
INVERTER
COMPARATER
SW R1 GND SW P1 CONT GND VCC SW P2 GND SW R2
2 3 54 6 7 981
MUT
E
+ VO
UT1
– VO
UT1
COM
P1
MF1 IN1
GND
IN2
NF2
COM
P2
– VO
UT2
+ VO
UT2
VCC1
VCC2 VE
E
PROTECTOR
BIAS CIRCUIT
REG DRIVE PREDRIVE
1110 12 13 1514
DRIVEPREDRIVE
IC602 UPC1330HA (AUDIO BOARD)
IC151 UPC2581V (POWER BOARD)
IC651 STK350-230 (POWER BOARD)
— 39 —
5-16. IC BLOCK DIAGRAMS
IC300 LV1041M (MAIN BOARD)
12
20
1
2
3456
78
9
10
11
12
13
14
15
16
19
17
18
20
21
3231302928272625
24
23
22
33
44
43
42
41
40393837363534
7374757677787980 72 65666768697071
52
51
5049
48
47
46
45
53
54
55
56575859
60
61
62
63
64
STRIM
OSC
VOL
VOL
VCA VCAP
B
P
B
VCA VCA
VCA VCA VCA VCA
IEVNOISEGEN
NOISEFILTER
BPFCONTROL
CHCONTROL
BPF
V REF
STRIM
SMODE
RECT
RECT
DCCUT
B NR
OUTFILTER
DATADECODERVOL/
MUTE
BPF
RECT
LOGICFF
LOGICFF RECT
C MODE
LOGIC LOGIC
MASTERVOL
NFSW
S
S
S
P P B
B
B B
P
B
CD
R
L
C S
LR
P P
P
B
P
B
P
BP
B
P
B
S
MASTER VOL
VDDPCM
PCMCONTROL
SRAM
INFILTER
R
L
C
S
R
P
B
P
B
PB
PBL
L
R
L
R
R BPF2
R BPF1
S DC OUTC DC OUTR DC OUTL DC OUT
V REFVCC
C OUT
S OUT
R OUT
L OUT
GND
L IN
R IN
S IN
DELAY OUT
C VOL IN
DET
IREF
R OUT
R NF
L NF
L OUT
L BPF2
L BPF1
RT IN
LT IN
DC CUT
C MODE
GNDNS BPF1
OSC
NS BPF2
ENABLE
DATA
CLK
DATA
CLK
ENABLE2
VSS
OSC
OSC
VDD
A/D
NS
D/A
DC CUT
VCC
C VO
L OU
T
C OP
IN
GND
C OP
NF
C OP
OUT
VOL
REF
S OP
OUT
S OP
NF
S OP
IN
S VO
L OU
T
L RECT
DC CUT4
R RECT
DC CUT3
L BPF3
VLR TH
VLR 1
VLR 2
VCS 2
VCS 1
VCS TH
L+R RECT
DC CUT2
L-R RECT
DC CUT1
R DET3
OP V
REF
S VO
L IN
S OU
T
DC C
UT
— 40 —
IC302 LC7822 (MAIN BOARD)
IC401 LC75373ED (MAIN BOARD)
IC502 LB1641 (MAIN BOARD)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CONT
ROL LATCH
SHIFT RESISTOR
LEVEL SHIFT
CL
DI
CE
VEE
OUT
IN
OUT
IN
OUT
IN
VSS
S
RESET
VDD
OUT
ININ
OUT
IN
OUT
IN
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
+–
DECODER LATCH SHIFTREGISTER CONTROL
–+
+–
1 2 3 4 5 6 7 8 9 10
20
19
1817161514
13
12
11
21
22
2324252627282930313233
3435363738
39
4041424344
LSELOL4L3L2L1
VDD
R1R2R3R4
RSELO
RVRI
N
RCOM RT
1RT
2
RT3
RTOU
TRS
INRS
1
RS2
RS3
RSOU
T
RFIN
RFOUT
RROUTVSSCLDICE
VREF
LROUT
LFOUT
LFIN
LSOU
T
LS3
LS2
LS1
LSIN
LTOU
T
LT3
LT2
LT1
LCOM
LVRI
N
1 2 3 4 5 6 7 8 9 10
GND
MOT
ORDR
IVE
NOIS
EFI
LTER
CLAM
P
FWD.
IN
REV.
IN
VCC
1
VCC
2
NOIS
EFI
LTER
MOT
ORDR
IVE
MOTORDRIVE
MOTORDRIVE
T.S.D O.C.P
FWD/REV/STOPCONTROL LOGIC
1
2
3
4
5
6
7
8
9
TR3 R1
R2TR4
TR6TR7
R4
R9
TR5
TR1
TR2
R6
D4 D3
R7R8
TR8
D1 D2 R5
R3
INPUT
NF
-VEOUT
+VEOUT
VSS
GND
VCC
SUB
1 2 3 4 5 6 7 8 9
INVERTER
COMPARATER
SW R1 GND SW P1 CONT GND VCC SW P2 GND SW R2
2 3 54 6 7 981
MUT
E
+ VO
UT1
– VO
UT1
COM
P1
MF1 IN1
GND
IN2
NF2
COM
P2
– VO
UT2
+ VO
UT2
VCC1
VCC2 VE
E
PROTECTOR
BIAS CIRCUIT
REG DRIVE PREDRIVE
1110 12 13 1514
DRIVEPREDRIVE
IC602 UPC1330HA (AUDIO BOARD)
IC151 UPC2581V (POWER BOARD)
IC651 STK350-230 (POWER BOARD)
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