241-440 @ w.s. 24-440 computer system design lecture 7 wannarat suntiamorntut

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241-440 @ W.S.

2 -4 440 Computer Syste

mDesign Lecture 7

Wannarat Suntiamorntut

241-440 @ W.S.

PIPELINE

241-440 @ W.S.

Pipeline in the R eal world

30Washer takes minutes 33 333333330 33 333333330 33 333333330

241-440 @ W.S.

Sequential Laundry

8 4take hours for loads

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Pipeline laundr y

333 3 333333.5 4

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Datapath opera tion in MIP

333333 / 3333 333 33

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Apply Pipeline

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Pipeline Executio n Representation

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Pipeline give us If we would like to execute 100 instructi

333 33:45/ 11 00= 4 500 Multiple cycle : 10ns/cycle x 4.6 CPI x 10

0 = 4600 ns Pipeline (Ideal) : 10ns/cycle x (1 CPI x 10

0 + 4 cycle drain) = 1040 ns

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Comparison : singl e, multiple, pipeline

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Pipeline Hazard Structure Hazard

Same resources at the same time Data Hazard

Instruction depend on result of priorinstruction

Control Hazard Br anch I nst r uct i on

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Single Memory ( Structure H.)

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Control H. Solution

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Control H. Solut ion (Predict)

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Control H. Solut ion (Delay)

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Data H. 333 r1 , 2, 3 333 2 r1 336 and 7r , r1 , 5 33 4r , r1 338

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Data H. on R1

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Data H. (By pas sing) with Load

Must Solve by Delay / Stall

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Pipelined Processor

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Control and Datapath

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-Load and R type

Pipeline Conflict or Structural Hazar3

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Observation Each unit can only be used by one instruction

Each unit must be used at the same stage for all instructions

3333 33 33333 3333 33333332

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1. Insert Bubble into pipeline

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-2. Delay R type

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Modifies Contro l & Datapath

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Datapath + Control

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Try it 10 lw 1 2 35r , r ( )14 addl 2 2 3r , r ,20 sub 3 4 5r , r , r24 beq 6 7 100r , r ,30 333 8, 9, 17r r34 add 10 11 12r , r , r

100 and 13 14 15r , r ,33333 333333

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10Fetch :

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Fetch1 4 / Deco de 10

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3 3332 0

de 14, Execute10

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24Fetch , Dec 20 14, Exec ,

Mem10

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F3 0 ,Dc 2 4 , E 20 14, Mem ,

10WB

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334 3 0

24 20, Mem , 14

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100F , 3 4 3, 30 24, Mem ,

20

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104 10F , Dc 0,34 , Mem30,

24

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110 10F , Dc 4 100, E , Mem

34 30

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114 110F , Dc 104 100, E , Mem ,33 34

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8Next on Lecture

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