1 کلاس جبراني پنجشنبه 26 فروردين: ساعت 8:00 صبح ميان ترم ...
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کالس جبراني• 8:00 فروردين: ساعت 26پنجشنبه
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ميان ترم • 9:30 ارديبهشت: ساعت 3سه شنبه
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Programmable Logic
PAL, PLA
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Integration
• SSI Small-Scale Integration
− Several gates in a package
• MSI Medium-Scale Integration
− Tens of gates in a package
• LSI Large-Scale Integration
− Hundreds to hundred thousands of gates in a package
• VLSI Very Large-Scale Integration
− More than above− E.g. Microprocessors.
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SSI (7400 Series)
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DIP
Dual in-line Packages
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PLAs
Programmable Logic Array
Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making/ breaking connections among the gates.
General purpose logic building blocks.
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PLA
Inputs
Dense array of AND gates Product
terms
Dense array of OR gates
Outputs
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PLA
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PLA
• A 3×2 PLA with 4 product terms.
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Design for PLA:Example
Implement the following functions using PLAF0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A
Personality Matrix
1 = asserted in term0 = negated in term- = does not participate
Input Side:
1 = term connected to output0 = no connection to output
Output Side:Outputs Inputs Product
t erm
Reuse of
t erms
A 1 - 1 - 1
B 1 0 - 0 -
C - 1 0 0 -
F 0 0 0 0 1 1
F 1 1 0 1 0 0
F 2 1 0 0 1 0
F 3 0 1 0 0 1
A B B C A C B C A
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Example: Continued
F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A
Personality Matrix
Outputs Inputs Product t erm
Reuse of
t erms
A 1 - 1 - 1
B 1 0 - 0 -
C - 1 0 0 -
F 0 0 0 0 1 1
F 1 1 0 1 0 0
F 2 1 0 0 1 0
F 3 0 1 0 0 1
A B B C A C B C A
A B C
F0 F1 F2 F3
AB
B’C
AC’
B’C’
A
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Constants Sometimes a PLA output
must be programmed to be a constant 1 or a constant 0.− P1 is always 1
because its product line is connected to no inputs and is therefore always pulled HIGH;
− this constant-1 term drives the O1 output.
No product term drives the O2 output, which is therefore always 0.
Another method of obtaining a constant-0 output is shown for O3.
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BCD to Gray Code Converter
W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'
Minimized Functions:
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
W 0 0 0 0 0 1 1 1 1 1 X X X X X X
X 0 0 0 0 1 1 0 0 0 0 X X X X X X
Y 0 0 1 1 1 1 1 1 0 0 X X X X X X
Z 0 1 1 0 0 0 0 1 1 0 X X X X X X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
K-map for W
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
K-map for X
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
K-map for Y
AB
CD 00 01 11 10
00
01
11
10
D
B
C
A
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
K-map for Z
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4 product terms per each OR gate
A B C D
0
0
0
0
0
0
A B C D
A
BD
BC
W X Y Z
BC’
B
C
BCD
AD’
BCD’
Product terms cannot be shared !
PLA achieves higher flexibility at the cost of lower speed!
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PALs
• Programmable Array Logic a fixed OR array.
Inputs
Dense array of AND gates Product
terms
Dense array of OR gates
Outputs
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PALinputs
1st output section
2nd output section
3rd output section
4th output section
Only functions withat most four products can be implemented
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PAL
W = ABC + CDX = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD
x
x
x
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Tri-State (Output Enable) Gate
• Tri-State (Three-State) Inverter: The output in NOT of input if the Enable input is HIGH Else Hi-Impedance (Hi-Z)
− Unconnected.Enable
input output
outputinput
Enable• Tri-State (Three-State) Buffer:
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Active Low Input
• Tri-State Buffer with Active Low Enable:
• Tri-State Inverter with Active Low Enable:
in out
EN
in out
EN
3-state BUF, EN low
3-state INV, EN low
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Helper Terms If an I/O pin’s output-
control gate produces a constant 1, the output is always enabled, but the pin may still be used as an input too.
outputs can be used to generate first-pass “helper terms” for logic functions that cannot be performed in a single pass with the limited number of AND terms available for a single output.
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