amd barts(radeon hd 68xx) overview 一部推定ultra-threaded dispatch processor simd array setup...
TRANSCRIPT
Ultra-Threaded Dispatch Processor
SIMD Array
Setup Engine
AMD Barts(Radeon HD 68xx) Overview (一部推定)
Copyright (c) 2010 Hiroshige Goto All rights reserved.
GeometryAssembler
Ultra-Threaded Dispatch Processor
Tessellator(Gen7)
Command ProcessorRISC based Micro-Coded engine
Hierarchical Z
Data Share
Data Share
Data Share
Data Share
Data Share
Data Share
Data Share
L1 Texture Cache 8KB
(read only)
Global Data Share 64KB (read&write)
Instruction Cache Constant Cache
L2
Te
xtu
re C
ach
e1
28
KB
(rea
d o
nly
)
Z/S
ten
cil
Ca
ch
e
Color Cache
Hu
b
UV
D3
(Un
ive
rsa
l Vid
eo
D
eco
de
r)
Cro
ss
Fire
XC
om
po
sito
r
VerticesGeometry
Command Queue
L1 TC 8KB
L1 TC 8KB
L1 TC 8KB
L1 TC 8KB
L1 TC 8KB
L1 TC 8KB
256-bit GDDR5 Interface
RenderBack--End
Z/S
ten
cil
Ca
ch
e
Color Cache
RenderBack--End
GDDR5
Memory Controller
DRAM Controller
DRAM Controller
GDDR5
32-bit32-bit
L2
Te
xtu
re C
ach
e1
28
KB
(rea
d o
nly
)
Z/S
ten
cil
Ca
ch
e
Color Cache
RenderBack--End
Z/S
ten
cil
Ca
ch
e
Color Cache
RenderBack--End
GDDR5
Memory Controller
DRAM Controller
DRAM Controller
GDDR5
32-bit32-bit
L2
Te
xtu
re C
ach
e1
28
KB
(rea
d o
nly
)
Z/S
ten
cil
Ca
ch
e
Color Cache
RenderBack--End
Z/S
ten
cil
Ca
ch
e
Color Cache
RenderBack--End
GDDR5
Memory Controller
DRAM Controller
DRAM Controller
GDDR5
32-bit32-bit
SIMD ArrayData Share
Data Share
Data Share
Data Share
Data Share
Data Share
Data Share
L1 Texture Cache 8KB
(read only)
L1 TC 8KB
L1 TC 8KB
L1 TC 8KB
L1 TC 8KB
L1 TC 8KB
L1 TC 8KB
Cro
ss
ba
r (up
)
L2
Te
xtu
re C
ach
e1
28
KB
(rea
d o
nly
)
Z/S
ten
cil
Ca
ch
e
Color Cache
RenderBack--End
Z/S
ten
cil
Ca
ch
eColor Cache
RenderBack--End
GDDR5
Memory Controller
DRAM Controller
DRAM Controller
GDDR5
32-bit32-bit
Crossbar (Down) = Shader Export
Scan Converter /Rasterizer
VertexAssembler
Pixelｓ
Hierarchical ZScan Converter /Rasterizer
Pixelｓ
PC
I Ex
pre
ss
G
en
2.1
Crossbar (Down) = Shader Export
Ey
efin
ity D
isp
lay
Co
ntro
llers
Instruction Cache Constant Cache
GeometryVertices
Command Queue Command Queue Command QueueCommand QueueCommand Queue