AM335x ARM Cortex-A8 Microprocessors (MPUs)

Technical Reference Manual

Literature Number: SPRUH73F October 2011 Revised June 2012

ContentsPreface 1

2

3

4 5

6

.................................................................................................................................... Introduction .................................................................................................................... 1.1 AM335x Family ........................................................................................................... 1.1.1 Device Features ................................................................................................. 1.1.2 Device Identification ............................................................................................ 1.1.3 Feature Identification ........................................................................................... Memory Map ................................................................................................................... 2.1 ARM Cortex-A8 Memory Map .......................................................................................... 2.2 ARM Cortex-M3 Memory Map ......................................................................................... ARM MPU Subsystem ....................................................................................................... 3.1 ARM Cortex-A8 MPU Subsystem ...................................................................................... 3.1.1 Features .......................................................................................................... 3.1.2 MPU Subsystem Integration ................................................................................... 3.1.3 MPU Subsystem Clock and Reset Distribution ............................................................. 3.1.4 ARM Subchip .................................................................................................... 3.1.5 Interrupt Controller .............................................................................................. 3.1.6 Power Management ............................................................................................ 3.1.7 ARM Programming Model ..................................................................................... Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) ............. 4.1 Introduction ............................................................................................................... Graphics Accelerator (SGX) .............................................................................................. 5.1 Introduction ............................................................................................................... 5.1.1 POWERVR SGX Main Features .............................................................................. 5.1.2 SGX 3D Features ............................................................................................... 5.1.3 Universal Scalable Shader Engine (USSE) Key Features .............................................. 5.1.4 Unsupported Features .......................................................................................... 5.2 Integration ................................................................................................................. 5.2.1 SGX530 Connectivity Attributes ............................................................................... 5.2.2 SGX530 Clock and Reset Management ..................................................................... 5.2.3 SGX530 Pin List ................................................................................................. 5.3 Functional Description ................................................................................................... 5.3.1 SGX Block Diagram ............................................................................................ 5.3.2 SGX Elements Description .................................................................................... Interrupts ........................................................................................................................ 6.1 Functional Description ................................................................................................... 6.1.1 Interrupt Processing ............................................................................................ 6.1.2 Register Protection ............................................................................................. 6.1.3 Module Power Saving .......................................................................................... 6.1.4 Error Handling .................................................................................................. 6.1.5 Interrupt Handling ............................................................................................... 6.2 Basic Programming Model .............................................................................................. 6.2.1 Initialization Sequence ......................................................................................... 6.2.2 INTC Processing Sequence ................................................................................... 6.2.3 INTC Preemptive Processing Sequence .....................................................................Contents

153 154154 154 155 156

158158 167

169170 171 171 172 175 176 176 179

181182

183184 184 184 185 186 187 187 187 188 189 189 189

191192 193 194 194 194 194 195 195 195 199

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6.3 6.4 6.5 6.6

6.2.4 Interrupt Preemption ............................................................................................ 6.2.5 ARM A8 INTC Spurious Interrupt Handling ................................................................. ARM Cortex-A8 Interrupts .............................................................................................. ARM Cortex-M3 Interrupts .............................................................................................. PWM Events .............................................................................................................. Interrupt Controller Registers ........................................................................................... 6.6.1 INTC Registers .................................................................................................. GPMC ..................................................................................................................... 7.1.1 Introduction ...................................................................................................... 7.1.2 Integration ........................................................................................................ 7.1.3 Functional Description .......................................................................................... 7.1.4 Use Cases ....................................................................................................... 7.1.5 Registers ......................................................................................................... OCMC-RAM .............................................................................................................. 7.2.1 Introduction ...................................................................................................... 7.2.2 Integration ........................................................................................................ EMIF ....................................................................................................................... 7.3.1 Introduction ...................................................................................................... 7.3.2 Integration ........................................................................................................ 7.3.3 Functional Description .......................................................................................... 7.3.4 Use Cases ....................................................................................................... 7.3.5 EMIF4D Registers .............................................................................................. 7.3.6 DDR2/3/mDDR PHY Registers ............................................................................... ELM ........................................................................................................................ 7.4.1 Introduction ...................................................................................................... 7.4.2 Integration ........................................................................................................ 7.4.3 Functional Description .......................................................................................... 7.4.4 Basic Programming Model ..................................................................................... 7.4.5 ELM Registers ................................................................................................... Power, Reset, and Clock Management ............................................................................... 8.1.1 Introduction ...................................................................................................... 8.1.2 Device Power-Management Architecture Building Blocks ................................................. 8.1.3 Clock Management ............................................................................................. 8.1.4 Power Management ............................................................................................ 8.1.5 PRCM Module Overview ....................................................................................... 8.1.6 Clock Generation and Management .......................................................................... 8.1.7 Reset Management ............................................................................................. 8.1.8 Power-Up/Down Sequence .................................................................................... 8.1.9 IO State ........................................................................................................... 8.1.10 Voltage and Power Domains ................................................................................. 8.1.11 Device Modules and Power Management Attributes List ................................................. 8.1.12 Clock Module Registers ....................................................................................... 8.1.13 Power Management Registers ............................................................................... Introduction ............................................................................................................... Functional Description ................................................................................................... 9.2.1 Control Module Initialization ................................................................................... 9.2.2 Pad Control Registers .......................................................................................... 9.2.3 EDMA Event Multiplexing ...................................................................................... 9.2.4 Device Control and Status ..................................................................................... 9.2.5 DDR PHY ........................................................................................................Contents

203 203 204 208 210 211 211 387 387 390 392 491 502 535 535 536 537 537 539 541 559 559 600 609 609 610 611 614 620 633 633 633 633 639 647 648 664 673 673 673 674 677 834 876 876 876 876 877 878 8853

7

Memory Subsystem7.1

......................................................................................................... 386

7.2

7.3

7.4

8

Power, Reset, and Clock Management (PRCM)8.1

.................................................................... 632

9

Control Module9.1 9.2

................................................................................................................ 875

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9.3

CONTROL_MODULE Registers ....................................................................................... 9.3.1 control_revision Register (offset = 0h) [reset = 0h] ......................................................... 9.3.2 device_id Register (offset = 600h) [reset = 0x] ............................................................. 9.3.3 control_hwinfo Register (offset = 4h) [reset = 0h] .......................................................... 9.3.4 control_sysconfig Register (offset = 10h) [reset = 0h] ..................................................... 9.3.5 control_status Register (offset = 40h) [reset = 0h] ......................................................... 9.3.6 cortex_vbbldo_ctrl Register (offset = 41Ch) [reset = 0h] .................................................. 9.3.7 core_sldo_ctrl Register (offset = 428h) [reset = 0h] ........................................................ 9.3.8 mpu_sldo_ctrl Register (offset = 42Ch) [reset = 0h] ....................................................... 9.3.9 clk32kdivratio_ctrl Register (offset = 444h) [reset = 0h] ................................................... 9.3.10 bandgap_ctrl Register (offset = 448h) [reset = 0h] ........................................................ 9.3.11 bandgap_trim Register (offset = 44Ch) [reset = 0h] ....................................................... 9.3.12 pll_clkinpulow_ctrl Register (offset = 458h) [reset = 0h] .................................................. 9.3.13 mosc_ctrl Register (offset = 468h) [reset = 0h] ............................................................ 9.3.14 rcosc_ctrl Register (offset = 46Ch) [reset = 0h] ............................................................ 9.3.15 deepsleep_ctrl Register (offset = 470h) [reset = 0h] ...................................................... 9.3.16 dev_feature Register (offset = 604h) [reset = 0h] ......................................................... 9.3.17 init_priority_0 Register (offset = 608h) [reset = 0h] ........................................................ 9.3.18 init_priority_1 Register (offset = 60Ch) [reset = 0h] ....................................................... 9.3.19 mmu_cfg Register (offset = 610h) [reset = 0h] ............................................................. 9.3.20 tptc_cfg Register (offset = 614h) [reset = 0h] .............................................................. 9.3.21 usb_ctrl0 Register (offset = 620h) [reset = 0h] ............................................................. 9.3.22 usb_sts0 Register (offset = 624h) [reset = 0h] ............................................................. 9.3.23 usb_ctrl1 Register (offset = 628h) [reset = 0h] ............................................................. 9.3.24 usb_sts1 Register (offset = 62Ch) [reset = 0h] ............................................................ 9.3.25 mac_id0_lo Register (offset = 630h) [reset = 0h] .......................................................... 9.3.26 mac_id0_hi Register (offset = 634h) [reset = 0h] .......................................................... 9.3.27 mac_id1_lo Register (offset = 638h) [reset = 0h] .......................................................... 9.3.28 mac_id1_hi Register (offset = 63Ch) [reset = 0h] ......................................................... 9.3.29 dcan_raminit Register (offset = 644h) [reset = 0h] ........................................................ 9.3.30 usb_wkup_ctrl Register (offset = 648h) [reset = 0h] ...................................................... 9.3.31 gmii_sel Register (offset = 650h) [reset = 0h] .............................................................. 9.3.32 pwmss_ctrl Register (offset = 664h) [reset = 0h] .......................................................... 9.3.33 mreqprio_0 Register (offset = 670h) [reset = 0h] .......................................................... 9.3.34 mreqprio_1 Register (offset = 674h) [reset = 0h] .......................................................... 9.3.35 hw_event_sel_grp1 Register (offset = 690h) [reset = 0h] ................................................ 9.3.36 hw_event_sel_grp2 Register (offset = 694h) [reset = 0h] ................................................ 9.3.37 hw_event_sel_grp3 Register (offset = 698h) [reset = 0h] ................................................ 9.3.38 hw_event_sel_grp4 Register (offset = 69Ch) [reset = 0h] ................................................ 9.3.39 smrt_ctrl Register (offset = 6A0h) [reset = 0h] ............................................................. 9.3.40 mpuss_hw_debug_sel Register (offset = 6A4h) [reset = 0h] ............................................ 9.3.41 mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h] ............................................... 9.3.42 vdd_mpu_opp_050 Register (offset = 770h) [reset = 0h] ................................................. 9.3.43 vdd_mpu_opp_100 Register (offset = 774h) [reset = 0h] ................................................. 9.3.44 vdd_mpu_opp_120 Register (offset = 778h) [reset = 0h] ................................................. 9.3.45 vdd_mpu_opp_turbo Register (offset = 77Ch) [reset = 0h] .............................................. 9.3.46 vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h] ................................................ 9.3.47 vdd_core_opp_100 Register (offset = 7BCh) [reset = 0h] ................................................ 9.3.48 bb_scale Register (offset = 7D0h) [reset = 0h] ............................................................ 9.3.49 usb_vid_pid Register (offset = 7F4h) [reset = 4516141h] ................................................ 9.3.50 conf__ Register (offset = 800h) ........................................................... 9.3.51 cqdetect_status Register (offset = E00h) [reset = 0h] .................................................... 9.3.52 ddr_io_ctrl Register (offset = E04h) [reset = 0h] ...........................................................

886 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 914 915 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945

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9.3.53 9.3.54 9.3.55 9.3.56 9.3.57 9.3.58 9.3.59 9.3.60 9.3.61 9.3.62 9.3.63 9.3.64 9.3.65 9.3.66 9.3.67 9.3.68 9.3.69 9.3.70 9.3.71 9.3.72 9.3.73 9.3.74 9.3.75 9.3.76 9.3.77 9.3.78 9.3.79 9.3.80 9.3.81 9.3.82 9.3.83 9.3.84 9.3.85 9.3.86 9.3.87 9.3.88 9.3.89 9.3.90

vtp_ctrl Register (offset = E0Ch) [reset = 0h] .............................................................. vref_ctrl Register (offset = E14h) [reset = 0h] .............................................................. tpcc_evt_mux_0_3 Register (offset = F90h) [reset = 0h] ................................................. tpcc_evt_mux_4_7 Register (offset = F94h) [reset = 0h] ................................................. tpcc_evt_mux_8_11 Register (offset = F98h) [reset = 0h] ............................................... tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h] ............................................. tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h] .............................................. tpcc_evt_mux_20_23 Register (offset = FA4h) [reset = 0h] .............................................. tpcc_evt_mux_24_27 Register (offset = FA8h) [reset = 0h] .............................................. tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h] ............................................. tpcc_evt_mux_32_35 Register (offset = FB0h) [reset = 0h] .............................................. tpcc_evt_mux_36_39 Register (offset = FB4h) [reset = 0h] .............................................. tpcc_evt_mux_40_43 Register (offset = FB8h) [reset = 0h] .............................................. tpcc_evt_mux_44_47 Register (offset = FBCh) [reset = 0h] ............................................. tpcc_evt_mux_48_51 Register (offset = FC0h) [reset = 0h] ............................................. tpcc_evt_mux_52_55 Register (offset = FC4h) [reset = 0h] ............................................. tpcc_evt_mux_56_59 Register (offset = FC8h) [reset = 0h] ............................................. tpcc_evt_mux_60_63 Register (offset = FCCh) [reset = 0h] ............................................. timer_evt_capt Register (offset = FD0h) [reset = 0h] ..................................................... ecap_evt_capt Register (offset = FD4h) [reset = 0h] ..................................................... adc_evt_capt Register (offset = FD8h) [reset = 0h] ....................................................... reset_iso Register (offset = 1000h) [reset = 0h] ........................................................... ddr_cke_ctrl Register (offset = 131Ch) [reset = 0h] ....................................................... sma2 Register (offset = 1320h) [reset = 0h] ................................................................ m3_txev_eoi Register (offset = 1324h) [reset = 0h] ....................................................... ipc_msg_reg0 Register (offset = 1328h) [reset = 0h] ..................................................... ipc_msg_reg1 Register (offset = 132Ch) [reset = 0h] ..................................................... ipc_msg_reg2 Register (offset = 1330h) [reset = 0h] ..................................................... ipc_msg_reg3 Register (offset = 1334h) [reset = 0h] ..................................................... ipc_msg_reg4 Register (offset = 1338h) [reset = 0h] ..................................................... ipc_msg_reg5 Register (offset = 133Ch) [reset = 0h] ..................................................... ipc_msg_reg6 Register (offset = 1340h) [reset = 0h] ..................................................... ipc_msg_reg7 Register (offset = 1344h) [reset = 0h] ..................................................... ddr_cmd0_ioctrl Register (offset = 1404h) [reset = 0h] ................................................... ddr_cmd1_ioctrl Register (offset = 1408h) [reset = 0h] ................................................... ddr_cmd2_ioctrl Register (offset = 140Ch) [reset = 0h] .................................................. ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h] ................................................... ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h] ...................................................

946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 981 983 985 987 990 990 990 993

10

Interconnects10.1

.................................................................................................................. 989

Introduction ............................................................................................................... 10.1.1 Terminology ..................................................................................................... 10.1.2 L3 Interconnect ................................................................................................. 10.1.3 L4 Interconnect .................................................................................................

11

Enhanced Direct Memory Access (EDMA)11.1

........................................................................... 995

11.2

11.3

Introduction ............................................................................................................... 996 11.1.1 EDMA3 Controller Block Diagram ........................................................................... 996 11.1.2 Third-Party Channel Controller (TPCC) Overview ......................................................... 996 11.1.3 Third-Party Transfer Controller (TPTC) Overview ......................................................... 997 Integration ................................................................................................................. 999 11.2.1 Third-Party Channel Controller (TPCC) Integration ....................................................... 999 11.2.2 Third-Party Transfer Controller (TPTC) Integration ...................................................... 1000 Functional Description ................................................................................................. 1002 11.3.1 Functional Overview ......................................................................................... 1002Contents 5

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11.4

11.5

11.3.2 Types of EDMA3 Transfers ................................................................................. 11.3.3 Parameter RAM (PaRAM) ................................................................................... 11.3.4 Initiating a DMA Transfer .................................................................................... 11.3.5 Completion of a DMA Transfer ............................................................................. 11.3.6 Event, Channel, and PaRAM Mapping .................................................................... 11.3.7 EDMA3 Channel Controller Regions ....................................................................... 11.3.8 Chaining EDMA3 Channels ................................................................................. 11.3.9 EDMA3 Interrupts ............................................................................................ 11.3.10 Memory Protection .......................................................................................... 11.3.11 Event Queue(s) ............................................................................................. 11.3.12 EDMA3 Transfer Controller (EDMA3TC) ................................................................ 11.3.13 Event Dataflow .............................................................................................. 11.3.14 EDMA3 Prioritization ....................................................................................... 11.3.15 EDMA3 Operating Frequency (Clock Control) .......................................................... 11.3.16 Reset Considerations ....................................................................................... 11.3.17 Power Management ........................................................................................ 11.3.18 Emulation Considerations .................................................................................. 11.3.19 EDMA Transfer Examples ................................................................................. 11.3.20 EDMA Events ................................................................................................ EDMA3 Registers ...................................................................................................... 11.4.1 EDMA3 Channel Controller Registers ..................................................................... 11.4.2 EDMA3 Transfer Controller Registers ..................................................................... Appendix A .............................................................................................................. 11.5.1 Debug Checklist .............................................................................................. 11.5.2 Miscellaneous Programming/Debug Tips ................................................................. 11.5.3 Setting Up a Transfer ........................................................................................ Introduction .............................................................................................................. 12.1.1 TSC_ADC Features .......................................................................................... 12.1.2 Unsupported TSC_ADC_SS Features .................................................................... Integration ............................................................................................................... 12.2.1 TSC_ADC Connectivity Attributes .......................................................................... 12.2.2 TSC_ADC Clock and Reset Management ................................................................ 12.2.3 TSC_ADC Pin List ............................................................................................ Functional Description ................................................................................................. 12.3.1 HW Synchronized or SW Channels ........................................................................ 12.3.2 Open Delay and Sample Delay ............................................................................. 12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................ 12.3.4 One-Shot (Single) or Continuous Mode ................................................................... 12.3.5 Interrupts ...................................................................................................... 12.3.6 DMA Requests ................................................................................................ 12.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... Operational Modes ..................................................................................................... 12.4.1 PenCtrl and PenIRQ ......................................................................................... Touchscreen Controller Registers .................................................................................... 12.5.1 TSC_ADC_SS Registers .................................................................................... Introduction .............................................................................................................. 13.1.1 Purpose of the Peripheral ................................................................................... 13.1.2 Features ....................................................................................................... Integration ............................................................................................................... 13.2.1 LCD Controller Connectivity Attributes .................................................................... 13.2.2 LCD Controller Clock and Reset Management ...........................................................

1005 1007 1019 1022 1023 1025 1027 1028 1034 1038 1040 1043 1043 1044 1044 1044 1044 1046 1062 1065 1065 1119 1143 1143 1144 1145 1148 1148 1148 1149 1149 1150 1150 1151 1151 1151 1151 1151 1151 1151 1152 1153 1154 1157 1157 1222 1222 1223 1224 1224 1225

12

Touchscreen Controller12.1

.................................................................................................. 1147

12.2

12.3

12.4 12.5

13

LCD Controller13.1

............................................................................................................... 1221

13.2

6

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13.3

13.4

13.5

13.2.3 LCD Controller Pin List ...................................................................................... Functional Description ................................................................................................. 13.3.1 Clocking ........................................................................................................ 13.3.2 LCD External I/O Signals .................................................................................... 13.3.3 DMA Engine ................................................................................................... 13.3.4 LIDD Controller ............................................................................................... 13.3.5 Raster Controller ............................................................................................. 13.3.6 Interrupt Conditions .......................................................................................... 13.3.7 DMA ............................................................................................................ 13.3.8 Power Management .......................................................................................... Programming Model .................................................................................................... 13.4.1 LCD Character Displays ..................................................................................... 13.4.2 Active Matrix Displays ....................................................................................... 13.4.3 System Interaction ........................................................................................... 13.4.4 Palette Lookup ................................................................................................ 13.4.5 Test Logic ..................................................................................................... 13.4.6 Disable and Software Reset Sequence ................................................................... 13.4.7 Precedence Order for Determining Frame Buffer Type ................................................. LCD Registers .......................................................................................................... 13.5.1 PID Register (offset = 0h) [reset = 0h] ..................................................................... 13.5.2 CTRL Register (offset = 4h) [reset = 0h] .................................................................. 13.5.3 LIDD_CTRL Register (offset = Ch) [reset = 0h] .......................................................... 13.5.4 LIDD_CS0_CONF Register (offset = 10h) [reset = 0h] .................................................. 13.5.5 LIDD_CS0_ADDR Register (offset = 14h) [reset = 0h] .................................................. 13.5.6 LIDD_CS0_DATA Register (offset = 18h) [reset = 0h] .................................................. 13.5.7 LIDD_CS1_CONF Register (offset = 1Ch) [reset = 0h] ................................................. 13.5.8 LIDD_CS1_ADDR Register (offset = 20h) [reset = 0h] .................................................. 13.5.9 LIDD_CS1_DATA Register (offset = 24h) [reset = 0h] .................................................. 13.5.10 RASTER_CTRL Register (offset = 28h) [reset = 0h] ................................................... 13.5.11 RASTER_TIMING_0 Register (offset = 2Ch) [reset = 0h] ............................................. 13.5.12 RASTER_TIMING_1 Register (offset = 30h) [reset = 0h] ............................................. 13.5.13 RASTER_TIMING_2 Register (offset = 34h) [reset = 0h] ............................................. 13.5.14 RASTER_SUBPANEL Register (offset = 38h) [reset = 0h] ........................................... 13.5.15 RASTER_SUBPANEL2 Register (offset = 3Ch) [reset = 0h] ......................................... 13.5.16 LCDDMA_CTRL Register (offset = 40h) [reset = 0h] .................................................. 13.5.17 LCDDMA_FB0_BASE Register (offset = 44h) [reset = 0h] ............................................ 13.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h] ........................................ 13.5.19 LCDDMA_FB1_BASE Register (offset = 4Ch) [reset = 0h] ........................................... 13.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h] ........................................ 13.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h] ...................................................... 13.5.22 IRQSTATUS_RAW Register (offset = 58h) [reset = 0h] ............................................... 13.5.23 IRQSTATUS Register (offset = 5Ch) [reset = 0h] ...................................................... 13.5.24 IRQENABLE_SET Register (offset = 60h) [reset = 0h] ................................................ 13.5.25 IRQENABLE_CLEAR Register (offset = 64h) [reset = 0h] ............................................ 13.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h] .................................................. 13.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h] .................................................... Introduction .............................................................................................................. 14.1.1 Features ....................................................................................................... 14.1.2 Unsupported Features ....................................................................................... Integration ............................................................................................................... 14.2.1 Ethernet Switch Connectivity Attributes ................................................................... 14.2.2 Ethernet Switch Clock and Reset Management ..........................................................Contents

1225 1226 1226 1228 1229 1230 1232 1243 1245 1245 1246 1246 1249 1249 1249 1251 1251 1252 1252 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1266 1267 1268 1270 1271 1272 1274 1275 1276 1277 1278 1280 1282 1284 1286 1288 1289 1291 1291 1292 1293 1293 12957

14

Ethernet Subsystem14.1

....................................................................................................... 1290

14.2

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14.3

14.4

14.5

14.2.3 Ethernet Switch Pin List ..................................................................................... 14.2.4 Ethernet Switch RMII Clocking Details .................................................................... 14.2.5 GMII Interface Signal Connections and Descriptions .................................................... 14.2.6 RMII Signal Connections and Descriptions ............................................................... 14.2.7 RGMII Signal Connections and Descriptions ............................................................. Functional Description ................................................................................................. 14.3.1 CPSW_3G Subsystem ....................................................................................... 14.3.2 CPSW_3G ..................................................................................................... 14.3.3 Ethernet Mac Sliver (CPGMAC_SL) ....................................................................... 14.3.4 Command IDLE ............................................................................................... 14.3.5 RMII Interface ................................................................................................. 14.3.6 RGMII Interface ............................................................................................... 14.3.7 Common Platform Time Sync (CPTS) ..................................................................... 14.3.8 MDIO ........................................................................................................... Software Operation ..................................................................................................... 14.4.1 Transmit Operation ........................................................................................... 14.4.2 Receive Operation ........................................................................................... 14.4.3 Initializing the MDIO Module ................................................................................ 14.4.4 Writing Data to a PHY Register ............................................................................ 14.4.5 Reading Data from a PHY Register ........................................................................ 14.4.6 Initialization and Configuration of CPSW .................................................................. Ethernet Subsystem Registers ....................................................................................... 14.5.1 CPSW_ALE Registers ....................................................................................... 14.5.2 CPSW_CPDMA Registers .................................................................................. 14.5.3 CPSW_CPTS Registers ..................................................................................... 14.5.4 CPSW_STATS Registers ................................................................................... 14.5.5 CPDMA_STATERAM Registers ............................................................................ 14.5.6 CPSW_PORT Registers ..................................................................................... 14.5.7 CPSW_SL Registers ......................................................................................... 14.5.8 CPSW_SS Registers ........................................................................................ 14.5.9 CPSW_WR Registers ........................................................................................ 14.5.10 Management Data Input/Output (MDIO) Registers ..................................................... Pulse-Width Modulation Subsystem (PWMSS) .................................................................... 15.1.1 Introduction .................................................................................................... 15.1.2 Integration ..................................................................................................... 15.1.3 PWMSS Registers ........................................................................................... Enhanced PWM (ePWM) Module .................................................................................... 15.2.1 Introduction .................................................................................................... 15.2.2 Functional Description ....................................................................................... 15.2.3 Use Cases ..................................................................................................... 15.2.4 Registers ...................................................................................................... Enhanced Capture (eCAP) Module .................................................................................. 15.3.1 Introduction .................................................................................................... 15.3.2 Functional Description ....................................................................................... 15.3.3 Use Cases ..................................................................................................... 15.3.4 Registers ...................................................................................................... Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................... 15.4.1 Introduction .................................................................................................... 15.4.2 Functional Description ....................................................................................... 15.4.3 eQEP Registers .............................................................................................. Introduction

1296 1296 1297 1300 1301 1303 1303 1308 1350 1352 1353 1353 1356 1361 1363 1363 1365 1366 1366 1367 1367 1368 1368 1383 1436 1449 1449 1483 1539 1553 1566 1602 1614 1614 1616 1617 1623 1623 1627 1686 1710 1736 1736 1737 1747 1763 1775 1775 1778 1796

15

Pulse-Width Modulation Subsystem (PWMSS)15.1

................................................................... 1613

15.2

15.3

15.4

16

Universal Serial Bus (USB)16.1

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16.2

16.3

16.4 16.5

16.1.1 Acronyms, Abbreviations, and Definitions ................................................................. 16.1.2 USB Features ................................................................................................. 16.1.3 Unsupported USB OTG and PHY Features .............................................................. Integration ............................................................................................................... 16.2.1 USB Connectivity Attributes ................................................................................. 16.2.2 USB Clock and Reset Management ....................................................................... 16.2.3 USB Pin List ................................................................................................... 16.2.4 USB GPIO Details ............................................................................................ 16.2.5 USB Unbonded PHY Pads .................................................................................. Functional Description ................................................................................................. 16.3.1 VBUS Voltage Sourcing Control ............................................................................ 16.3.2 Pull-up/Pull-Down Resistors ................................................................................ 16.3.3 Role Assuming Method ...................................................................................... 16.3.4 Clock, PLL, and PHY Initialization ......................................................................... 16.3.5 Indexed and Non-Indexed Register Spaces .............................................................. 16.3.6 Dynamic FIFO Sizing ........................................................................................ 16.3.7 USB Controller Host and Peripheral Modes Operation .................................................. 16.3.8 Protocol Description(s) ....................................................................................... 16.3.9 Communications Port Programming Interface (CPPI) 4.1 DMA ....................................... 16.3.10 USB 2.0 Test Modes ....................................................................................... Supported Use Cases ................................................................................................. USB Registers .......................................................................................................... 16.5.1 USBSS Registers ............................................................................................. 16.5.2 USB0_CTRL Registers ...................................................................................... 16.5.3 USB1_CTRL Registers ...................................................................................... 16.5.4 USB2PHY Registers ......................................................................................... 16.5.5 CPPI_DMA Registers ........................................................................................ 16.5.6 CPPI_DMA_SCHEDULER Registers ...................................................................... 16.5.7 QUEUE_MGR Registers .................................................................................... Mailbox ................................................................................................................... 17.1.1 Introduction .................................................................................................... 17.1.2 Integration ..................................................................................................... 17.1.3 Functional Description ....................................................................................... 17.1.4 Programming Guide .......................................................................................... 17.1.5 MAILBOX Registers .......................................................................................... Spinlock .................................................................................................................. 17.2.1 SPINLOCK Registers ........................................................................................ Introduction .............................................................................................................. 18.1.1 MMCHS Features ............................................................................................ 18.1.2 Unsupported MMCHS Features ............................................................................ Integration ............................................................................................................... 18.2.1 MMCHS Connectivity Attributes ............................................................................ 18.2.2 MMCHS Clock and Reset Management .................................................................. 18.2.3 MMCHS Pin List .............................................................................................. Functional Description ................................................................................................. 18.3.1 MMC/SD/SDIO Functional Modes ......................................................................... 18.3.2 Resets ......................................................................................................... 18.3.3 Power Management .......................................................................................... 18.3.4 Interrupt Requests ............................................................................................ 18.3.5 DMA Modes ................................................................................................... 18.3.6 Mode Selection ...............................................................................................Contents

1815 1816 1817 1818 1818 1819 1819 1819 1820 1821 1821 1821 1822 1822 1823 1823 1824 1825 1858 1883 1884 1885 1885 1928 1978 2026 2053 2209 2274 3426 3426 3427 3428 3432 3435 3496 3496 3535 3535 3535 3536 3537 3538 3538 3540 3540 3547 3548 3551 3553 35569

17

Interprocessor Communication17.1

........................................................................................ 3425

17.2

18

Multimedia Card (MMC)18.1

................................................................................................... 3534

18.2

18.3

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18.4

18.5

18.3.7 Buffer Management .......................................................................................... 18.3.8 Transfer Process ............................................................................................. 18.3.9 Transfer or Command Status and Error Reporting ...................................................... 18.3.10 Auto Command 12 Timings ................................................................................ 18.3.11 Transfer Stop ................................................................................................ 18.3.12 Output Signals Generation ................................................................................ 18.3.13 Card Boot Mode Management ............................................................................ 18.3.14 CE-ATA Command Completion Disable Management ................................................ 18.3.15 Test Registers ............................................................................................... 18.3.16 MMC/SD/SDIO Hardware Status Features .............................................................. Low-Level Programming Models ..................................................................................... 18.4.1 Surrounding Modules Global Initialization ................................................................. 18.4.2 MMC/SD/SDIO Controller Initialization Flow .............................................................. 18.4.3 Operational Modes Configuration .......................................................................... Multimedia Card Registers ............................................................................................ 18.5.1 MULTIMEDIA_CARD Registers ............................................................................ Introduction .............................................................................................................. 19.1.1 UART Mode Features ........................................................................................ 19.1.2 IrDA Mode Features ......................................................................................... 19.1.3 CIR Mode Features .......................................................................................... 19.1.4 Unsupported UART Features ............................................................................... Integration ............................................................................................................... 19.2.1 UART Connectivity Attributes ............................................................................... 19.2.2 UART Clock and Reset Management ..................................................................... 19.2.3 UART Pin List ................................................................................................. Functional Description ................................................................................................. 19.3.1 Block Diagram ................................................................................................ 19.3.2 Clock Configuration .......................................................................................... 19.3.3 Software Reset ............................................................................................... 19.3.4 Power Management .......................................................................................... 19.3.5 Interrupt Requests ............................................................................................ 19.3.6 FIFO Management ........................................................................................... 19.3.7 Mode Selection ............................................................................................... 19.3.8 Protocol Formatting .......................................................................................... UART/IrDA/CIR Basic Programming Model ......................................................................... 19.4.1 UART Programming Model ................................................................................. 19.4.2 IrDA Programming Model ................................................................................... UART Registers ........................................................................................................ 19.5.1 UART Registers .............................................................................................. DMTimer ................................................................................................................. 20.1.1 Introduction .................................................................................................... 20.1.2 Integration ..................................................................................................... 20.1.3 Functional Description ....................................................................................... 20.1.4 Use Cases ..................................................................................................... 20.1.5 TIMER Registers ............................................................................................. DMTimer 1ms ........................................................................................................... 20.2.1 Introduction .................................................................................................... 20.2.2 Integration ..................................................................................................... 20.2.3 Functional Description ....................................................................................... 20.2.4 Use Cases ..................................................................................................... 20.2.5 DMTIMER_1MS Registers ..................................................................................

3556 3559 3560 3565 3567 3568 3570 3572 3572 3573 3574 3574 3574 3577 3579 3579 3637 3637 3637 3637 3637 3639 3639 3640 3642 3643 3643 3644 3644 3644 3646 3649 3657 3663 3686 3686 3692 3695 3695 3741 3741 3743 3745 3754 3754 3772 3772 3774 3776 3784 3784

19

Universal Asynchronous Receiver/Transmitter (UART)19.1

....................................................... 3636

19.2

19.3

19.4

19.5

20

Timers20.1

.......................................................................................................................... 3740

20.2

10

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20.3

20.4

RTC_SS ................................................................................................................. 20.3.1 Introduction .................................................................................................... 20.3.2 Integration ..................................................................................................... 20.3.3 Functional Description ....................................................................................... 20.3.4 Use Cases ..................................................................................................... 20.3.5 RTC Registers ................................................................................................ WATCHDOG ............................................................................................................ 20.4.1 Introduction .................................................................................................... 20.4.2 Integration ..................................................................................................... 20.4.3 Functional Description ....................................................................................... 20.4.4 Watchdog Registers .......................................................................................... Introduction .............................................................................................................. 21.1.1 I2C Features .................................................................................................. 21.1.2 Unsupported I2C Features .................................................................................. Integration ............................................................................................................... 21.2.1 I2C Connectivity Attributes .................................................................................. 21.2.2 I2C Clock and Reset Management ........................................................................ 21.2.3 I2C Pin List .................................................................................................... Functional Description ................................................................................................. 21.3.1 Functional Block Diagram ................................................................................... 21.3.2 I2C Master/Slave Contoller Signals ........................................................................ 21.3.3 I2C Reset ...................................................................................................... 21.3.4 Data Validity ................................................................................................... 21.3.5 START & STOP Conditions ................................................................................. 21.3.6 I2C Operation ................................................................................................. 21.3.7 Arbitration ...................................................................................................... 21.3.8 I2C Clock Generation and I2C Clock Synchronization .................................................. 21.3.9 Prescaler (SCLK/ICLK) ...................................................................................... 21.3.10 Noise Filter ................................................................................................... 21.3.11 I2C Interrupts ................................................................................................ 21.3.12 DMA Events ................................................................................................. 21.3.13 Interrupt and DMA Events ................................................................................. 21.3.14 FIFO Management .......................................................................................... 21.3.15 How to Program I2C ........................................................................................ Registers ................................................................................................................. 21.4.1 I2C Registers ................................................................................................. Introduction .............................................................................................................. 22.1.1 Purpose of the Peripheral ................................................................................... 22.1.2 Features ....................................................................................................... 22.1.3 Protocols Supported ......................................................................................... 22.1.4 Unsupported McASP Features ............................................................................. Integration ............................................................................................................... 22.2.1 McASP Connectivity Attributes ............................................................................. 22.2.2 McASP Clock and Reset Management .................................................................... 22.2.3 McASP Pin List ............................................................................................... Functional Description ................................................................................................. 22.3.1 Overview ....................................................................................................... 22.3.2 Functional Block Diagram ................................................................................... 22.3.3 Industry Standard Compliance Statement ................................................................ 22.3.4 Definition of Terms ........................................................................................... 22.3.5 Clock and Frame Sync Generators ........................................................................Contents

3808 3808 3809 3810 3818 3818 3858 3858 3859 3860 3867 3886 3886 3886 3887 3887 3888 3888 3889 3889 3889 3890 3890 3892 3892 3894 3894 3895 3895 3895 3896 3896 3896 3901 3903 3903 3947 3947 3947 3947 3948 3949 3949 3950 3950 3951 3951 3952 3955 3959 396111

21

I2C ................................................................................................................................ 388521.1

21.2

21.3

21.4

22

Multichannel Audio Serial Port (McASP)22.1

........................................................................... 3946

22.2

22.3

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22.4

22.3.6 Signal Descriptions ........................................................................................... 22.3.7 Pin Multiplexing ............................................................................................... 22.3.8 Transfer Modes ............................................................................................... 22.3.9 General Architecture ......................................................................................... 22.3.10 Operation ..................................................................................................... 22.3.11 Reset Considerations ....................................................................................... 22.3.12 Setup and Initialization ..................................................................................... 22.3.13 Interrupts ..................................................................................................... 22.3.14 EDMA Event Support ....................................................................................... 22.3.15 Power Management ........................................................................................ 22.3.16 Emulation Considerations .................................................................................. McASP Registers ....................................................................................................... 22.4.1 McASP CFG Registers ...................................................................................... 22.4.2 McASP Data Port Registers ................................................................................

3965 3965 3966 3973 3977 3994 3994 3999 4001 4003 4003 4004 4004 4057

23

24

........................................................................................ 4058 23.1 Introduction .............................................................................................................. 4059 23.1.1 DCAN Features ............................................................................................... 4059 23.1.2 Unsupported DCAN Features ............................................................................... 4059 23.2 Integration ............................................................................................................... 4060 23.2.1 DCAN Connectivity Attributes ............................................................................... 4060 23.2.2 DCAN Clock and Reset Management ..................................................................... 4061 23.2.3 DCAN Pin List ................................................................................................. 4061 23.3 Functional Description ................................................................................................. 4062 23.3.1 CAN Core ...................................................................................................... 4062 23.3.2 Message Handler ............................................................................................. 4063 23.3.3 Message RAM ................................................................................................ 4063 23.3.4 Message RAM Interface ..................................................................................... 4063 23.3.5 Registers and Message Object Access ................................................................... 4063 23.3.6 Module Interface .............................................................................................. 4063 23.3.7 Dual Clock Source ........................................................................................... 4063 23.3.8 CAN Operation ................................................................................................ 4064 23.3.9 Dual Clock Source ........................................................................................... 4070 23.3.10 Interrupt Functionality ...................................................................................... 4071 23.3.11 Local Power-Down Mode .................................................................................. 4073 23.3.12 Parity Check Mechanism .................................................................................. 4075 23.3.13 Debug/Suspend Mode ..................................................................................... 4076 23.3.14 Configuration of Message Objects ........................................................................ 4076 23.3.15 Message Handling .......................................................................................... 4079 23.3.16 CAN Bit Timing .............................................................................................. 4084 23.3.17 Message Interface Register Sets ......................................................................... 4092 23.3.18 Message RAM ............................................................................................... 4094 23.3.19 GIO Support ................................................................................................. 4099 23.4 DCAN Registers ........................................................................................................ 4100 23.4.1 DCAN Control Registers ..................................................................................... 4100 Multichannel Serial Port Interface (McSPI) ......................................................................... 4141 24.1 Introduction .............................................................................................................. 4142 24.1.1 McSPI Features .............................................................................................. 4142 24.1.2 Unsupported McSPI Features .............................................................................. 4142 24.2 Integration ............................................................................................................... 4142 24.2.1 McSPI Connectivity Attributes .............................................................................. 4144 24.2.2 McSPI Clock and Reset Management ..................................................................... 4144 24.2.3 McSPI Pin List ................................................................................................ 4144 24.3 Functional Description ................................................................................................. 4145Controller Area Network (CAN)Contents SPRUH73F October 2011 Revised June 2012 Submit Documentation FeedbackCopyright 20112012, Texas Instruments Incorporated

12

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24.4

24.3.1 SPI Transmission ............................................................................................. 24.3.2 Master Mode .................................................................................................. 24.3.3 Slave Mode .................................................................................................... 24.3.4 Interrupts ...................................................................................................... 24.3.5 DMA Requests ................................................................................................ 24.3.6 Emulation Mode .............................................................................................. 24.3.7 Power Saving Management ................................................................................. 24.3.8 System Test Mode ........................................................................................... 24.3.9 Reset ........................................................................................................... 24.3.10 Access to Data Registers .................................................................................. 24.3.11 Programming Aid ........................................................................................... 24.3.12 Interrupt and DMA Events ................................................................................. McSPI Registers ........................................................................................................ 24.4.1 SPI Registers .................................................................................................

4145 4152 4170 4174 4175 4176 4177 4178 4178 4179 4179 4180 4180 4181

25

26

A

......................................................................................... 4204 25.1 Introduction .............................................................................................................. 4205 25.1.1 Purpose of the Peripheral ................................................................................... 4205 25.1.2 GPIO Features ................................................................................................ 4205 25.1.3 Unsupported GPIO Features ............................................................................... 4205 25.2 Integration ............................................................................................................... 4206 25.2.1 GPIO Connectivity Attributes ............................................................................... 4206 25.2.2 GPIO Clock and Reset Management ...................................................................... 4207 25.2.3 GPIO Pin List ................................................................................................. 4208 25.3 Functional Description ................................................................................................. 4209 25.3.1 Operating Modes ............................................................................................. 4209 25.3.2 Clocking and Reset Strategy ................................................................................ 4209 25.3.3 Interrupt Features ............................................................................................ 4210 25.3.4 General-Purpose Interface Basic Programming Model ................................................. 4212 25.4 GPIO Registers ......................................................................................................... 4215 25.4.1 GPIO Registers ............................................................................................... 4215 Initialization ................................................................................................................... 4242 26.1 Functional Description ................................................................................................. 4243 26.1.1 Architecture ................................................................................................... 4243 26.1.2 Functionality ................................................................................................... 4243 26.1.3 Memory Map .................................................................................................. 4244 26.1.4 Start-up and Configuration .................................................................................. 4248 26.1.5 Booting ......................................................................................................... 4250 26.1.6 Fast External Booting ........................................................................................ 4259 26.1.7 Memory Booting .............................................................................................. 4261 26.1.8 Peripheral Booting ............................................................................................ 4288 26.1.9 Image Format ................................................................................................. 4293 26.1.10 Code Execution ............................................................................................ 4294 26.1.11 Wakeup ...................................................................................................... 4295 26.1.12 Tracing ....................................................................................................... 4296 Revision History ............................................................................................................ 4300General-Purpose Input/Output

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Contents

13

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List of Figures3-1. 3-2. 3-3. 3-4. 3-5. 5-1. 5-2. 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 6-10. 6-11. 6-12. 6-13. 6-14. 6-15. 6-16. 6-17. 6-18. 6-19. 6-20. 6-21. 6-22. 6-23. 6-24. 6-25. 6-26. 6-27. 6-28. 6-29. 6-30. 6-31. 6-32. 6-33. 6-34. 6-35. 6-36. 6-37. 6-38. 6-39. 6-40.14

Microprocessor Unit (MPU) Subsystem ............................................................................... 170 Microprocessor Unit (MPU) Subsystem Signal Interface ........................................................... 172 MPU Subsystem Clocking Scheme

...................................................................................

173

Reset Scheme of the MPU Subsystem ............................................................................... 174 MPU Subsystem Power Domain Overview ........................................................................... 177 SGX530 Integration ...................................................................................................... 187

..................................................................................................... Interrupt Controller Block Diagram .................................................................................... IRQ/FIQ Processing Sequence ........................................................................................ Nested IRQ/FIQ Processing Sequence .............................................................................. INTC_REVISION Register .............................................................................................. INTC_SYSCONFIG Register ........................................................................................... INTC_SYSSTATUS Register ........................................................................................... INTC_SIR_IRQ Register ................................................................................................ INTC_SIR_FIQ Register ................................................................................................ INTC_CONTROL Register .............................................................................................. INTC_PROTECTION Register ......................................................................................... INTC_IDLE Register ..................................................................................................... INTC_IRQ_PRIORITY Register ........................................................................................ INTC_FIQ_PRIORITY Register ........................................................................................ INTC_THRESHOLD Register .......................................................................................... INTC_ITR0 Register ..................................................................................................... INTC_MIR0 Register .................................................................................................... INTC_MIR_CLEAR0 Register .......................................................................................... INTC_MIR_SET0 Register .............................................................................................. INTC_ISR_SET0 Register .............................................................................................. INTC_ISR_CLEAR0 Register .......................................................................................... INTC_PENDING_IRQ0 Register ....................................................................................... INTC_PENDING_FIQ0 Register ....................................................................................... INTC_ITR1 Register ..................................................................................................... INTC_MIR1 Register .................................................................................................... INTC_MIR_CLEAR1 Register .......................................................................................... INTC_MIR_SET1 Register .............................................................................................. INTC_ISR_SET1 Register .............................................................................................. INTC_ISR_CLEAR1 Register .......................................................................................... INTC_PENDING_IRQ1 Register ....................................................................................... INTC_PENDING_FIQ1 Register ....................................................................................... INTC_ITR2 Register ..................................................................................................... INTC_MIR2 Register .................................................................................................... INTC_MIR_CLEAR2 Register .......................................................................................... INTC_MIR_SET2 Register .............................................................................................. INTC_ISR_SET2 Register .............................................................................................. INTC_ISR_CLEAR2 Register .......................................................................................... INTC_PENDING_IRQ2 Register ....................................................................................... INTC_PENDING_FIQ2 Register ....................................................................................... INTC_ITR3 Register ..................................................................................................... INTC_MIR3 Register ....................................................................................................SGX Block Diagram

189 192 198 202 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251

List of Figures

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6-41. 6-42. 6-43. 6-44. 6-45. 6-46. 6-47. 6-48. 6-49. 6-50. 6-51. 6-52. 6-53. 6-54. 6-55. 6-56. 6-57. 6-58. 6-59. 6-60. 6-61. 6-62. 6-63. 6-64. 6-65. 6-66. 6-67. 6-68. 6-69. 6-70. 6-71. 6-72. 6-73. 6-74. 6-75. 6-76. 6-77. 6-78. 6-79. 6-80. 6-81. 6-82. 6-83. 6-84. 6-85. 6-86. 6-87. 6-88. 6-89.

INTC_MIR_CLEAR3 Register .......................................................................................... 252 INTC_MIR_SET3 Register .............................................................................................. 253 INTC_ISR_SET3 Register .............................................................................................. 254

.......................................................................................... INTC_PENDING_IRQ3 Register ....................................................................................... INTC_PENDING_FIQ3 Register ....................................................................................... INTC_ILR0 Register ..................................................................................................... INTC_ILR1 Register ..................................................................................................... INTC_ILR2 Register ..................................................................................................... INTC_ILR3 Register ..................................................................................................... INTC_ILR4 Register ..................................................................................................... INTC_ILR5 Register ..................................................................................................... INTC_ILR6 Register ..................................................................................................... INTC_ILR7 Register ..................................................................................................... INTC_ILR8 Register ..................................................................................................... INTC_ILR9 Register ..................................................................................................... INTC_ILR10 Register .................................................................................................... INTC_ILR11 Register .................................................................................................... INTC_ILR12 Register .................................................................................................... INTC_ILR13 Register .................................................................................................... INTC_ILR14 Register .................................................................................................... INTC_ILR15 Register .................................................................................................... INTC_ILR16 Register .................................................................................................... INTC_ILR17 Register .................................................................................................... INTC_ILR18 Register .................................................................................................... INTC_ILR19 Register .................................................................................................... INTC_ILR20 Register .................................................................................................... INTC_ILR21 Register .................................................................................................... INTC_ILR22 Register .................................................................................................... INTC_ILR23 Register .................................................................................................... INTC_ILR24 Register .................................................................................................... INTC_ILR25 Register .................................................................................................... INTC_ILR26 Register .................................................................................................... INTC_ILR27 Register .................................................................................................... INTC_ILR28 Register .................................................................................................... INTC_ILR29 Register .................................................................................................... INTC_ILR30 Register .................................................................................................... INTC_ILR31 Register .................................................................................................... INTC_ILR32 Register .................................................................................................... INTC_ILR33 Register .................................................................................................... INTC_ILR34 Register .................................................................................................... INTC_ILR35 Register .................................................................................................... INTC_ILR36 Register .................................................................................................... I