alu design assignment
DESCRIPTION
Verilog code for ALUTRANSCRIPT
Arithmetic and Logic Unit
Logic Unit Status Register Output Register2 x 1 MUX
D-Flip flop based
Arithmetic Unit
4x 1 MUX
2 x 1 MUX
8 bit adder
1 bit adder
Logic gates
4 x 1 MUX
Logic gates
ALU Design
Hierarchical View
Verilog Code
module ALU (A,B,S,St,T,clk,set,clr); //Top module ALU
input clk,set,clr;
input[7:0] A,B;
input[3:0] S;
output [3:0] St;
output [7:0] T;
wire [7:0] G,Y,Tin;
wire [3:0] F;
arithmetic_unit au(A,B,S[0],S[2:1],G,F); //Instantiation of sub-units namely arithmetic and logic units,multiplexer,status and output register
logic_unit lu(A,B,S[2:1],Y);
mux2_1 mux1(Y,G,S[3],Tin);
output_register d1(Tin,clk,set,clr,T);
status d2(F,clk,set,clr,St);
endmodule
module arithmetic_unit (A,B,Co,S,G,F); //Arithmetic unit
input [7:0] A,B;
input Co;
input [1:0] S;
output [7:0] G;
output [3:0] F;
wire [7:0] A1,X,B1,Y;
wire w;
not(A1[0],A[0]),(A1[1],A[1]),(A1[2],A[2]),(A1[3],A[3]),(A1[4],A[4]),(A1[5],A[5]),(A1[6],A[6]),(A1[7],A[7]);
not(B1[0],B[0]),(B1[1],B[1]),(B1[2],B[2]),(B1[3],B[3]),(B1[4],B[4]),(B1[5],B[5]),(B1[6],B[6]),(B1[7],B[7]);
nand(w,S[0],S[1]);
mux2_1 m1 (A1,A,w,X);
mux4_1 m2(8'b0,B,B1,B,S,Y);
adder_8bit add1(X,Y,Co,G,F[0],F[1]);
nor(F[2],G[0],G[1],G[2],G[3],G[4],G[5],G[6],G[7]);
and(F[3],G[7],1'b1);
endmodule
module logic_unit(A,B,S,Y); //Logic Unit
input [7:0] A,B;
input [1:0] S;
output [7:0] Y;
wire [7:0] w1,w2,w3,w4;
and (w1[7],A[7],B[7]),(w1[6],A[6],B[6]),(w1[5],A[5],B[5]),(w1[4],A[4],B[4]),(w1[3],A[3],B[3]),(w1[2],A[2],B[2]),(w1[1],A[1],B[1]),(w1[0],A[0],B[0]);
or (w2[7],A[7],B[7]),(w2[6],A[6],B[6]),(w2[5],A[5],B[5]),(w2[4],A[4],B[4]),(w2[3],A[3],B[3]),(w2[2],A[2],B[2]),(w2[1],A[1],B[1]),(w2[0],A[0],B[0]);
xor (w3[7],A[7],B[7]),(w3[6],A[6],B[6]),(w3[5],A[5],B[5]),(w3[4],A[4],B[4]),(w3[3],A[3],B[3]),(w3[2],A[2],B[2]),(w3[1],A[1],B[1]),(w3[0],A[0],B[0]);
xnor(w4[7],A[7],B[7]),(w4[6],A[6],B[6]),(w4[5],A[5],B[5]),(w4[4],A[4],B[4]),(w4[3],A[3],B[3]),(w4[2],A[2],B[2]),(w4[1],A[1],B[1]),(w4[0],A[0],B[0]);
mux4_1 m1(w1,w2,w3,w4,S,Y);
endmodule
module adder (a,b,ci,s,co); //1-bit adder
input a,b,ci;
output s,co;
assign s= a^b^ci;
assign co= (a&b)|(b&ci)|(a&ci);
endmodule
module adder_8bit (A,B,Ci,S,Ov,Cout); //8-bit adder required in
arithmetic unit
input [7:0] A,B;
input Ci;
output [7:0] S;
output Ov,Cout;
wire [6:0] w;
adder ad0(A[0],B[0],Ci,S[0],w[0]);
adder ad1(A[1],B[1],w[0],S[1],w[1]);
adder ad2(A[2],B[2],w[1],S[2],w[2]);
adder ad3(A[3],B[3],w[2],S[3],w[3]);
adder ad4(A[4],B[4],w[3],S[4],w[4]);
adder ad5(A[5],B[5],w[4],S[5],w[5]);
adder ad6(A[6],B[6],w[5],S[6],w[6]);
adder ad7(A[7],B[7],w[6],S[7],Cout);
xor(Ov,Cout,w[6]);
endmodule
module mux4_1 (a,b,c,d,s,y); //4-is-to-1 multiplexer
input [7:0]a,b,c,d;
input [1:0] s;
output [7:0]y;
wire [7:0] w1,w2;
mux2_1 m1(a,b,s[0],w1);
mux2_1 m2(c,d,s[0],w2);
mux2_1 m3(w1,w2,s[1],y);
endmodule
module mux2_1 (a,b,s,y); //2-is-to-1 multiplexer
input [7:0] a,b;
input s;
output reg [7:0] y;
always @ (a or b or s)
begin
if(s==0)
y=a;
else
y=b;
end
endmodule
module status (d,clk,st,clr,q); //Status register
input [3:0]d;
input clk,st,clr;
output reg [3:0]q;
always@(negedge st,negedge clr,posedge clk)
begin
if(!clr)
q <= 0;
else if(!st)
q <= 1;
else q <= d;
end
endmodule
module output_register (d,clk,st,clr,q); //Output register
input [7:0]d;
input clk,st,clr;
output reg [7:0]q;
always@(negedge st,negedge clr,posedge clk)
begin
if(!clr)
q <= 0;
else if(!st)
q <= 1;
else q <= d;
end
endmodule
Output
I. Arithmetic Unit
Consider A=01010111 and B=11011010 and M=1
S1 S0 C0 Output 0 0 0 01010111
0 0 1 010110000 1 0 (1)001100010 1 1 (1)001100101 0 0 011111001 0 1 011111011 1 0 (1)100000101 1 1 (1)10000011
Output Waveforms
Arithmetic Unit
II. Logic Unit
S1 S0 C0 Function0 0 X 010100100 1 X (1)001100011 0 X 100011011 1 X 01110010
Output Waveforms
Logic Unit
Test Bench
module testalu;
wire [7:0]T;
wire [3:0]St;
reg [7:0] A,B;
reg [3:0] S;
reg clk,set,clr;
integer i;
ALU a1 (A,B,S,St,T,clk,set,clr);
initial
begin
clk =0;
S= 0000;
A=01010100;
B=11101100;
clr = 0;
set = 1;
end
always
begin
#5 clk = ~clk;
end
always @(posedge clk)
begin
clr = 1;
for (i=0;i<16;i=i+1)
begin
#20 S = i;
end
end
endmodule