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altdq & altdqs Megafunction

User Guide

Software Version: 6.0Document Version: 2.0 Document Date: September 2006

http://www.altera.com

Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-plication or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-formation and before placing orders for products or services.

ii MegaCore Version a.b.c variable Altera Corporationaltdq & altdqs Megafunction User Guide Preliminary September 2006

UG-MF9304-2.0

Altera Corporation iiiSeptember 2006 altdq & altdqs Megafunction User Guide

Contents

Chapter 1. About this MegafunctionDevice Family Support ......................................................................................................................... 1–1Introduction ............................................................................................................................................ 1–1Features ................................................................................................................................................... 1–1

altdq Megafunction .......................................................................................................................... 1–2altdqs Megafunction ........................................................................................................................ 1–2

General Description ............................................................................................................................... 1–3Stratix II Devices ......................................................................................................................... 1–3Stratix & Stratix GX ..................................................................................................................... 1–7Cyclone II Devices .................................................................................................................... 1–11

Common Applications .................................................................................................................. 1–12Resource Utilization & Performance ................................................................................................ 1–13

altdq Megafunction ........................................................................................................................ 1–13altdqs Megafunction ...................................................................................................................... 1–14

Chapter 2. Getting StartedSystem Requirements ............................................................................................................................ 2–1MegaWizard Plug-In Manager Customization ................................................................................. 2–1MegaWizard Page Descriptions .......................................................................................................... 2–1


Inferring Megafunctions from HDL Code ....................................................................................... 2–22Instantiating Megafunctions in HDL Code ..................................................................................... 2–22Identifying a Megafunction after Compilation ............................................................................... 2–22Simulation ............................................................................................................................................. 2–23

Quartus II Simulation .................................................................................................................... 2–23EDA Simulation .............................................................................................................................. 2–23

SignalTap II Embedded Logic Analyzer .......................................................................................... 2–24Design Example: Implement DDR I/O Interface ........................................................................... 2–24

Design Files ..................................................................................................................................... 2–24Example ................................................................................................................................................. 2–24

Create an altdq Megafunction ...................................................................................................... 2–24Combine the altdq & altdqs Modules to Create a DDR I/O Interface ................................... 2–35Implement the DDR I/O Interface Design ................................................................................. 2–37Functional Results—Simulate DDR I/O Interface Design in the Quartus II Simulator ...... 2–39Functional Results—Simulate the DDR I/O Interface Design in ModelSim-Altera Tool ... 2–41

Chapter 3. SpecificationsPorts & Parameters ................................................................................................................................ 3–1


iv Altera Corporationaltdq & altdqs Megafunction User Guide September 2006

Contents altdq & altdqs Megafunction

Altera Corporation MegaCore Version a.b.c variable vSeptember 2006 altdq & altdqs Megafunction User Guide

About this User Guide

Revision History The table below displays the revision history for the chapters in this User Guide.

How to Contact Altera

For the most up-to-date information about Altera® products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below.

Chapter Date Document Version Changes Made

All August 2006 2.0 ● Updated screen shots ● Added ModelSim-Altera simulation procedure

● Minor text edits for the Quartus® II software version 6.0 release

2 April 2005 1.1 Minor corrections to tables 2-2 and 2-8.

All March 2005 1.0 Initial release.

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ altera.com/mysupport/

(800) 800-EPLD (3753)(7:00 a.m. to 5:00 p.m. Pacific Time)

(408) 544-7000 (1)(7:00 a.m. to 5:00 p.m. Pacific Time)

Product literature www.altera.com www.altera.com

Altera literature services [email protected] (1) [email protected] (1)

Non-technical customer service

(800) 767-3753(7:00 a.m. to 5:00 p.m. Pacific Time)

(408) 544-7000 (7:30 a.m. to 5:30 p.m. Pacific Time)

FTP site ftp.altera.com ftp.altera.com

Note to table:(1) You can also contact your local Altera sales office or sales representative.

http://www.altera.com/mysupport/

http://www.altera.com/mysupport/



mailto:[email protected]

mailto:[email protected]

ftp://ftp.altera.com

ftp://ftp.altera.com


http://www.altera.com/mysupport

vi MegaCore Version a.b.c variable Altera Corporationaltdq & altdqs Megafunction User Guide September 2006

Typographic Conventions

Typographic Conventions

This document uses the typographic conventions shown below.

Visual Cue Meaning

Bold Type with Initial Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.

Italic Type with Initial Capital Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design.

Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.

Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu.

“Subheading Title” References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: “Typographic Conventions.”

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.

1., 2., 3., anda., b., c., etc.

Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.

■ ● • Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only.

1 The hand points to information that requires special attention.

cThe caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process.

w The warning indicates information that should be read prior to starting or continuing the procedure or processes.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information about a particular topic.

Altera Corporation MegaCore Version a.b.c variable 1–1September 2006 altdq & altdqs Megafunction User Guide

1. About this Megafunction

Device Family Support

Megafunctions provide either full or preliminary support for target Altera® device families, as described below:

■ Full support means the megafunction meets all functional and timing requirements for the device family and may be used in production designs.

■ Preliminary support means the megafunction meets all functional requirements, but may still be undergoing timing analysis for the device family; it may be used in production designs with caution.

Table 1–1 shows the level of support offered by the altdq and altdqs megafunctions for each Altera device family.

Introduction As design complexities increase, use of vendor-specific intellectual property (IP) blocks has become a common design methodology. Altera provides parameterizable megafunctions that are optimized for Altera device architectures. Using megafunctions instead of coding your own logic saves valuable design time.

Features The Altera-provided functions offer efficient logic synthesis and device implementation. You can scale the megafunction's size by simply setting parameters.

Table 1–1. Device Family Support

Device Family Support

Stratix® II GX Full

Stratix II Full

Stratix Full

Stratix GX Full

HardCopy® Stratix Full

Cyclone™ II Full

HardCopy II Full

1–2 MegaCore Version a.b.c variable Altera Corporationaltdq & altdqs Megafunction User Guide September 2006

Features

altdq Megafunction

The altdq megafunction allows you to easily configure the double data rate (DDR) I/O elements in Stratix series and Cyclone II devices. The altdq megafunction is a variation of the altddio_bidir megafunction modified for use with the altdqs megafunction.

The altdq megafunction implements a DDR Interface and offers many additional features, which include:

■ Transmission and reception of data on both edges of the reference clock

■ Clock input for the negative-edge input register that is ddioinclk (available for Stratix II devices only)

■ Active high asynchronous clear and clock-enable control inputs■ Registered or unregistered output enable input

altdqs Megafunction

The altdqs megafunction allows you to easily configure the I/O elements of data (DQ) and data strobe (DQS) in the Stratix series and Cyclone II devices.

The altdqs megafunction is typically used with the altdq megafunction and offers many additional features, which include:

■ A group of DQS pins used to strobe read/write data in external DDR memory interfaces using a common DLL to phase shift the read strobe

■ Implementing one DLL and a number of user-specified DQS pins (the maximum number of DQS supported by a DLL depends on the device)

■ Clocks generated for the DQ negative-edge input registers from the DQSn pins that is dqddioinclk[] (available for Stratix II devices only)

■ Delay buffer setting output option■ Frequency settings of DQS inputs and system reference clock■ Active high asynchronous clear and clock enable control inputs■ Registered or unregistered output enable input.■ DQS outputs configurable as open drain mode■ Speed setting of the DQS and delay buffers either LOW or HIGH

(available for Stratix II devices only)


About this Megafunction

General Description

The altdq and altdqs megafunctions are provided in the Quartus® II software MegaWizard® Plug-In Manager.

The altdq and altdqs megafunctions are closely related to functionality of the DDR I/O pins for each of the device families. Most of the features of the megafunction map directly into features of the IOE for each device family. For Cyclone II devices that do not have DDR I/O registers in the IOE, the features are created in logic cells.

The DQ and DQS pins must be configured as bidirectional DDR pins on all the I/O banks of the device. Both DQ and DQS are bidirectional (the same signals are used for both writes and reads). A group of DQ pins is associated with one DQS pin. Use the altdq and altdqs megafunctions to configure the DQ and DQS paths, respectively.

Stratix II Devices

Stratix II devices have DQS logic blocks with each DQS pin that helps with fine-tuning the phase shift. The DQS delay settings are routed from the DLL into the logic array. Bypass the DLL and send the DQS delay settings from the logic array to the DQS logic block.

The Stratix II DDR IOE structure requires you to invert the incoming DQS signal to ensure proper data transfer. The altdq megafunctions automatically adds the inverter to the inclock port when it generates the DQ signals. In a DDR memory read operation, the last data coincides with DQS being low. If you do not invert the DQS pin, you will not get this last data as the latch does not open until the next rising edge of the DQS signal.

Figure 1–1 shows the IOE structure in Stratix II devices for DQ configuration, and Figure 1–2 shows the IOE structure in Stratix II devices for DQS configuration.


General Description

Figure 1–1. DQ Configuration in Stratix II IOE Note (1)

Notes to Figure 1–1:(1) Use the altdq megafunction to generate the DQ signals.(2) The oe signal is active low, but the Quartus II software implements this as active high and automatically adds an

inverter before OE register AOE during compilation.(3) The outclock signal is –90° phase-shifted from the system clock.(4) The shifted DQS or DQSn signal can clock this register. Only use the DQSn signal for QDRII SDRAM interfaces.(5) The shifted DQS signal must be inverted before going to the DQ IOE. The inversion is automatic if you use the

altdq megafunction to generate the DQ signals. Connect this port to the combout port in the altdqs megafunction.

DQ

DFF

DQ

LATCH

ENA

DQ

DFF

Input Register AI

Input Register BILatch C

D Q

DFF

D Q

DFF

0

1

D Q

DFF

TRI

DQ Pin

OE Register AOE

Output Register AO

Output Register BO

Logic Array

Latch

dataout_l

dataout_h

outclock (3)

datain_h

datain_l

OE

inclock (from DQS bus)

neg_reg_out

I

(5)

(4)

(2)



Figure 1–2. DQS Configuration in Stratix II IOE Notes (1), (6), (8)

Notes to Figure 1–2:(1) Use the altdqs megafunction to generate the DQS signals.(2) The oe signal is active low, but the Quartus II software implements this as active high and automatically adds an

inverter before OE register AOE during compilation.(3) The select line can be chosen in the altdqs megafunction.(4) The datain_l and datain_h pins are usually connected to ground and VCC, respectively.(5) DQS post-amble circuitry and handling is not shown in this diagram. For more information, refer to AN 327:

Interfacing DDR SDRAM with Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II Devices.(6) DQS logic blocks are only available with DQS and DQSn pins.(7) Invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq

megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction.(8) The altdqs megafunction labels system clock as outclk, combout as dqinclk, datain_h as

dqs_datain_h, datain_l as dqs_datain_l, and the undelayed DQS as dqsundelayedout. The DQS phase shift circuitry (DLL) requires a clock to operate; altdqs labels that port as the inclk.

D Q

DFF

D Q

DFF

0

1

Output Register BO

Output Register AO

OE Register BOE

OE Register AOE

D Q

DFF

D Q

DFF

OR2

TRI DQS Pin (5)

Logic Array

system clock

datain_l (4)

datain_h (4)

OE

(3)

combout (7)

(2)

0

1

DQS Phase Shift Circuitry

(8)

undelayed DQS (6)


General Description

The first set of waveforms (Figure 1–3) shows the edge-aligned relationship between the DQ and DQS signals at the Stratix II device pins. The second set of waveforms in the figure shows what happens if the shifted DQS signal is not inverted. The last data, Dn, does not get latched into the logic array, as DQS goes to a tristate after the read post-amble time. The third set of waveforms in the figure shows a proper read operation with the DQS signal inverted after the 90° shift; the last data, Dn, does get latched. In this case, the outputs of register AI and latch CI, which correspond to the dataout_h and dataout_l ports, are switched because of the DQS inversion.

Figure 1–3. Timing Waveforms

DQ at the pin

DQS shiftedby 90˚

Output of register A1(dataout_h)

Output of latch C1(dataout_l)

Output of register B1

DQS inverted andshifted by 90˚




DQS at the pin

Shifted DQS Signal is Not Inverted

Shifted DQS Signal is Inverted

DQ & DQS Signals

Dn − 1

Dn − 2

Dn − 2

Dn − 2

Dn − 1

Dn

Dn

Dn − 3 Dn − 1

Dn − 1 Dn



DQS phase-shift circuitry and DQS logic blocks within the device allow you to fine-tune the phase-shifts for the input clocks or strobes to properly align clock edges as needed to capture data.

Stratix & Stratix GX

Stratix and Stratix GX data pins for the DDR memory interfaces are called DQ pins. Stratix and Stratix GX devices support either bidirectional data strobes or unidirectional read clocks. Depending on the external memory interface, either the memory device's read data strobes or read clocks feed the DQS pins. Each group consists of one DQS pin and a set of eight DQ pins. The device contains dedicated circuitry to shift the incoming DQS signals by 0° , 72° , and 90° . The DQS phase-shift circuitry uses a frequency reference to dynamically generate control signals for the delay chains in each of the DQS pins, allowing it to compensate for process, minimum voltage, and maximum temperature (PVT) variations. In addition to the DQS dedicated phase-shift circuitry, every IOE in Stratix and Stratix GX devices contains six registers and one latch to achieve DDR operation (Figure 1–4). A programmable delay chain is available in the IOE to help reduce contention when interfacing with ZBT SRAM devices.


General Description

Figure 1–4. DQ Configuration in Stratix & Stratix GX IOE Note (1)

Notes to Figure 1–4:(1) Use the altdq megafunction to generate the DQ signals.(2) The oe signal is active low, but the Quartus II software implements this as active high and automatically adds an

inverter before the OE register AOE during compilation.(3) The outclock signal is –90° phase-shifted from the system clock.(4) The shifted DQS signal must be inverted before going to the IOE. The inversion is automatic if you use the altdq

megafunction to generate the DQ signals.

DQ

DFF

DQ

LATCH

ENA

DQ

DFF

Input Register AI

Input Register BILatch C

D Q

DFF

D Q

DFF

0

1

D Q

DFF

TRI

DQ Pin

OE Register AOE

Output Register AO

Output Register BO

Logic Array

Latch

dataout_l

dataout_h

outclock (3)

datain_h

datain_l

OE

inclock (from DQS bus)

neg_reg_out

I

(4)

(2)



Figure 1–5. DQS Configuration in Stratix & Stratix GX IOE

Notes to Figure 1–5:(1) Use the altdqs megafunction to generate the DQS signals.(2) The oe signal is active low, but the Quartus II software implements this as active high and automatically adds an

inverter before OE register AOE during compilation.(3) The select line can be chosen in the altdqs megafunction.(4) The datain_l and datain_h pins are usually connected to ground and VCC, respectively.(5) DQS post-amble circuitry and handling is not shown in this diagram. For more information, refer to AN 342:

Interfacing DDR SDRAM with Stratix & Stratix GX Devices.(6) This undelayed DQS signal goes to the LE for the soft post-amble circuitry.(7) Invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq

megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction.(8) DQS phase-shift circuitry is only available on DQS pins.

D Q

DFF

D Q

DFF

0

1

Output Register BO

Output Register AO

OE Register BOE

OE Register AOE

D Q

DFF

D Q

DFF

OR2

TRI DQS Pin (5)

Logic Array

system clock

datain_l (4)

datain_h (4)

OE

(3)

combout (7)

(2)

0

1

DQS Phase Shift Circuitry

(8)

undelayed DQS (6)


General Description

Figure 1–6 shows waveforms of the circuit shown in Figure 1–4 on page 1–8. The second set of waveforms in the figure shows what happens if the shifted DQS signal is not inverted; the last data, Dn, does not get latched into the logic array as DQS goes to tristate after the read post-amble time. The third set of waveforms shows a proper read operation with the DQS signal inverted after the 90° shift; the last data Dn does get latched. In this case the outputs of register AI and latch CI, which correspond to dataout_h and dataout_lports, are now switched because of the DQS inversion.

Phase-shift circuitry in the Stratix and Stratix GX devices allows designers to ensure that clock edges are properly aligned.

Figure 1–6. Timing Waveforms

DQ at the pin

DQS shiftedby 90˚




DQS inverted andshifted by 90˚




DQS at the pin

Shifted DQS Signal is Not Inverted

Shifted DQS Signal is Inverted

DQ & DQS Signals

Dn − 1

Dn − 2

Dn − 2

Dn − 2

Dn − 1

Dn

Dn

Dn − 3 Dn − 1

Dn − 1 Dn



Cyclone II Devices

Dedicated clock delay control circuitry allows Cyclone II devices to interface with an external memory device at clock speeds up to 167 MHz/333 Mbps for DDR and DDR2 SDRAM devices, and 167 MHz/667 Mbps for QDRII SDRAM devices.

Cyclone II devices use DQ, DQS, and clock pins to interface with external memory. Cyclone II devices support the data strobe or read clock signals used in DDR and DDR2 SDRAM. The device can use either bidirectional data strobes or unidirectional read clocks. Figure 1–7 shows interfacing of DQ and DQS pins through the dedicated circuitry to the logic array in Cyclone II devices.

Figure 1–7. DDR SDRAM Interfacing from I/O Pins through Dedicated Circuitry of Logic Array

The clock delay control circuit on each DQS pin allows a phase shift that center-aligns the incoming DQS signals within the data window of corresponding DQ data signals. The phase-shifted DQS signals drive the global clock network and the global DQS signal, then clock the DQ signals on internal LE registers. The clock delay control circuitry is used during the read operations where the DQS signals are acting as input clocks or strobes.

The example in Figure 1–8 shows where the DQS signal is shifted by 90° . The DQS signal goes through the 90° shift-delay set by the clock delay control circuitry and global clock routing delay from the clock delay

DQS

OE

VCC

PLL

GND

clk

DQ

OE

DataA

DataB

Resynchronizingto System Clock

Global Clock

Clock DelayControl Circuitry

-90˚ Shifted clk

Adjacent LAB LEs

Clock ControlBlock

LERegister

LERegister

LERegister

LERegister

t

en/dis

Dynamic Enable/DisableCircuitry

ENOUT ena_register_mode

LERegister

LERegister

LERegister

LERegister

LERegister

LERegister

LERegister

LERegister

LERegister


General Description

control circuitry to the DQ LE registers. The DQ signals only go through routing delays from the DQ pin to the DQ LE registers. The delay from the DQS pin to the DQ LE register does not necessarily match the delay from the DQ pin to the DQ LE register. Adjust the clock delay control circuitry to compensate for this difference in delays.

Figure 1–8. DQS Signal Center-Aligned

Note to Figure 1–8:(1) The DQS and DQ pins to the register delay are not the same.

Common Applications

The altdq and altdqs megafunctions implement the bidirectional data pins and bidirectional data strobes respectively required in DDR external bus interfaces. The most common of these are external memory interfaces such as DDR SDRAM.

1 You should use the clear-text data path generated by the DDR SDRAM controller IP to implement all DDR SDRAM, DDR2 SDRAM, RLDRAM II, and QDRII systems. This data path has been validated by Altera and can be generated for many variations of these interfaces. To use the clear text data path, you need not purchase or instantiate the Altera DDR SDRAM Controller IP.

DQS at FPGA pin

DQ at FPGA pin

DQS at LE registers

DQ at LE registers

90˚ degree

DQ pin to register delay

DQS pin to register delay (1)

Preamble Postamble

(1)



f For more information, refer to the DDR & DDR2 SDRAM Controller Compiler User Guide.

The altdq and altdqs megafunctions implement proprietary interfaces and variations of the external memories that require features not supported by the Altera SDRAM controller.

Resource Utilization & Performance

This section details the resource utilization and performance of the altdq and the altdqs Megafunctions.

altdq Megafunction

The altdq megafunction is implemented in dedicated I/O circuitry in Stratix series devices. The altdq functionally is completely implemented within the IOE for these device families and no additional device resources are required.

f Refer to the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook, or the Stratix GX Architecture chapter in volume 1of the Stratix GX Device Handbook for details about the IOE circuitry for each device family.

For Cyclone II devices, the altdq circuitry is implemented in ALMs.

A Cyclone II implementation that does not use registered enable and registered OE signals uses 6 ALMs per pin. Each additional registered port adds an additional ALM register, although this may be packed into an existing ALM, which does not increase the overall ALM count.



Table 1–2 defines altdq resource usage.

altdqs Megafunction

The Stratix series device DQS implementation of the DQS functionality is implemented entirely within the I/O elements. Except for the I/O pins, altdqs requires no additional device resources.

Table 1–3 defines altdqs resource usage.

Table 1–2. altdq Megafunction Resource Usage

Device Family Optimization Width Logic Elements

Logic Array Blocks

Stratix II (1) (1) (1) (1)

Stratix (1) (1) (1) (1)

Stratix GX (1) (1) (1) (1)

HardCopy Stratix (1) (1) (1) (1)

Cyclone II Balanced (2) 8-bit 42 5

Notes for Table 1–2:(1) The altdq functionally is completely implemented within the IOE for these

device families and no additional device resources are required.(2) Choose a design implementation that balances high-performance with minimal

logic usage. This setting is available for Cyclone II devices only. You can set the balanced optimization logic option on the Assignments menu, then click Analysis and Synthesis settings.

Table 1–3. altdqs Megafunction Resource Usage (Part 1 of 2)

Device Family Optimization Width Logic Elements Logic Array Blocks

Stratix II (1) (1) (1) (1)

Stratix (1) (1) (1) (1)

Stratix GX (1) (1) (1) (1)

HardCopy Stratix (1) (1) (1) (1)

Cyclone II Balanced (2) 1-bit 4 2 (2 look-up tables (LUTs)

Cyclone II Balanced (2) 4-bit 16 2(5 LUTs)

Stratix II GX (1) (1) (1) (1)



The MegaWizard Plug-In Manager reports approximate resource utilization based on user specification and parameters, and is available in the lower left corner of the MegaWizard Plug-In Manager screen.

HardCopy II (1) (1) (1) (1)

Notes for Table 1–3:(1) The altdqs functionally is completely implemented within the IOE for these

device families. Except for the I/O pins, no additional device resources are required.

(2) Choose a design implementation that balances high-performance with minimal logic usage. Choose a design implementation that balances high-performance with minimal logic usage. This setting is available for Cyclone II devices only. You can set the balanced optimization logic option on the Assignments menu, then click Analysis and Synthesis settings.

Table 1–3. altdqs Megafunction Resource Usage (Part 2 of 2)

Device Family Optimization Width Logic Elements Logic Array Blocks


2. Getting Started

System Requirements

The instructions in this section require the following hardware and software:

■ A PC running Windows NT/2000/XP, Red Hat Linux 7.3 or 8.0, or Red Hat Linux Enterprise 3, or an HP workstation running the HP-UX 11.0 operating system, or a Sun workstation running the Solaris 8 or 9 operating system

■ Quartus® II software beginning with version 6.0

MegaWizard Plug-In Manager Customization

Use the MegaWizard® Plug-In Manager to specify the altdq and altdqs megafunction features in your design.

Start the MegaWizard Plug-In Manager in one of the following ways:

■ On the Tools menu, click MegaWizard Plug-In Manager.■ When working in the Block Editor, on the Edit menu, click Insert

Symbol as Block, or:● Right-click in the Block Editor, point to Insert, and click Symbol

as Block.● Then, in the Symbol dialog box, click MegaWizard Plug-In

Manager.■ Start the stand-alone version of the MegaWizard Plug-In Manager by

typing the following command at the command prompt:qmegawiz r

MegaWizard Page Descriptions

This section provides descriptions of the options available on the individual pages of the altdq and altdqs wizards.

altdq Megafunction

This section provides descriptions of the options available on the individual pages of the altdq MegaWizard Plug-In Manager.

In page 1 of the MegaWizard Plug-In Manager, you can create, edit, or copy a custom megafunction variation (Figure 2–1 on page 2–2).



Figure 2–1. Create, Edit, or Copy a Megafunction Variation

On page 2a, specify the family of device you want to use, type of output file to create, and the name of the output file. You also choose the ALTDQ megafunction from the I/O folder. Choose AHDL (.tdf), VHDL (.vhd), or Verilog HDL (.v) as the output file type (Figure 2–2).

Figure 2–2. MegaWizard Plug-In Manager


Getting Started

On page 3 of the altdq wizard, verify the device family you chose on page 2a, the number of data (DQ) pins, port options, and delay switch options (Figure 2–3).

Figure 2–3. altdq Wizard, Page 3



Table 2–1 describes the features and settings on page 3 of the altdq megafunction wizard.

Table 2–1. altdq MegaWizard Plug-in Manager Page 3 Options

Function Description

Currently selected device family Specifies the Altera® device family you are using.

How many DQ pins would you like? Specify the width of the data buses. If you are using a version of Quartus II below 6.0, this megafunction displays output ports as dataout_h[] and dataout_1[]; Quartus II version 6.0 and later displays output ports as dataout[] and dataout_ddio[].

Which asynchronous reset port would you like?

You can use the asynchronous clear (aclr) or the asynchronous preset (aset) as the asynchronous reset. If you do not use either clear option, you must specify whether the registers should power up high or low.

Create a clock enable port for each clock port

Creates an input clock enable port (inclken) and an output clock.

Create an output enable port Creates an output enable port (oe) for this instance of the altdq.

Register output enable Sets the OE_REGISTER_MODE parameter. When enabled, a register is placed in the OE path and the parameter is set to register. When disabled, parameter defaults to NONE.

Delay switch-on by a half clock cycle

Sets the EXTEND_OE_DISABLE parameter. When enabled, the pin will not drive out until the falling edge of the outclock. When enabled, the parameter is set to TRUE, otherwise it defaults to FALSE.

Invert Input Clock If enabled, the first bit of data is captured on the rising edge of the input clock; if not enabled, it will be captured on the falling edge of the input clock.

Use ddioinclk port (from DQSn bus) Creates a ddioinclk port. This port clocks the negative edge triggered input/capture register of the altdq instance.


Getting Started

On the final page of the wizard, specify the files you want to generate for your custom megafunction. The gray check marks indicate files that are always generated; the other files are optional (indicated by a red check mark) and are generated only if selected (Figure 2–4).

Figure 2–4. altdq Wizard, Summary

f For more information about the ports for the altdq megafunction, refer to Chapter 3, Specifications.



altdqs Megafunction

This section provides descriptions of the options available on the individual pages of the altdqs MegaWizard Plug-In Manager.

In page 1 of the MegaWizard Plug-In Manager, you can create, edit, or copy a custom megafunction variation (Figure 2–5).

Figure 2–5. Create, Edit, or Copy a Megafunction Variation


Getting Started

On page 2a, specify the family of device you want to use, type of output file to create, and the name of the output file. Also choose the ALTDQS megafunction from the I/O folder. Choose AHDL (.tdf), VHDL (.vhd), or Verilog HDL (.v) as the output file type (Figure 2–6).




On page 3 of the altdqs wizard, verify the device selected, specify the number of data strobe (DQS) pins and port options (Figure 2–7). (Note that if the Cyclone II family is selected, this page is slightly different.)

Figure 2–7. altdqs Wizard, Page 3 (HardCopy II, HardCopy Stratix, Stratix, Stratix GX, Stratix II, or Stratix II GX Device Selection)


Getting Started

Table 2–2 describes the options available on page 3 of the altdqs megafunction wizard when the Stratix® II device family is selected.

Table 2–2. altdqs MegaWizard Plug-in Manager Page 3 Options for HardCopy II, HardCopy Stratix, Stratix, Stratix GX, Stratix II, or Stratix II GX Device Selection


Currently selected device family

Displays the currently selected device family, Stratix II.

How many DQS pins would you like?

Defines width of DQS_padio bus, equivalent to setting number_of_dqs parameter.

Create an output enable for the DQS pins

Turn on this option to create an output enable for the DQS pins. If no output enable is port is used the DQS_padio will permanently drive out.

Register the output enable Turn on this option to register the output enable port with outclk.

What will control the DQS/nDQS delay chains? (1)

DLL feedback loop counter controls the DQS/nDQS delay chains● This is the default option. DLL inserts a delay equivalent to requested

phase-shift at input clock frequency. Input clock frequency and phase-shift are set on page 4.

No DLL is used● No DLL and no delay is added between DQS/nDQS and the dqinclk ports.

Note for Table 2–2:(1) Stratix and HardCopy® Stratix devices do not support this feature. This option is disabled in the wizard if the

Stratix, Stratix GX, or HardCopy Stratix device family is selected.



On page 3, specify the device family, the number of DQS pins, port options, and delay switch options (Figure 2–8).

Figure 2–8. altdqs Wizard, Page 3 (Cyclone II Device Family)


Getting Started

Table 2–3 describes the options available on page 3 of the altdqs megafunction wizard when the Cyclone® II device family is selected.

Table 2–3. altdqs MegaWizard Plug-in Manager Page 3 Options for Cyclone II Device Selection


Currently selected device family Displays the currently selected device family, Cyclone II.

How many DQS pins would you like? Defines width of the DQS_padio bus, equivalent to setting number_of_dqs parameter.

What is the frequency of the DQS input(s)?

Specify frequency of DQS input(s). This ranges from 66 MHz to 201 MHz.

Create an output enable for the DQS pins

Turn on this option to create an output enable for DQS pins. If no output enable port is used, DQS_padio permanently drives out.

Register the output enable Turn on this option to register output enable port with outclk.

How should the delay chain be specified?

Delay is specified either by number of delay buffers used or desired time delay. Time delay is converted to number of buffers during compilation. A typical buffer adds 28-38ps of delay. These buffers have a fixed delay, which is not dependent on input clock frequency.

Allow DQS to be disabled during read post-amble

Inhibits ddioinclk port during read post-amble (when DQS transitions from 0 to Z). Stops ddioinclk creating false clocks as DQS goes to tristate. If selected, adds an enable DQS input port to stop ddioinclk.

Invert dqs_padio port (when driving output)

When this is enabled, the dqs_padio port result is inverted if driven as an output.



On page 4 of the altdqs wizard, specify the DQS options.

1 This DQS options page is not available for Cyclone II devices.

Figure 2–9 shows page 4 of the altdqs wizard.

Figure 2–9. altdqs Wizard, Page 4 (HardCopy II, HardCopy Stratix, Stratix, Stratix GX, Stratix II, or Stratix II GX Device Selection)


Getting Started

Table 2–4 describes the options available on page 4 of the altdqs megafunction wizard.

Table 2–4. altdqs MegaWizard Plug-in Manager Page 4 Options (Part 1 of 2)


What is the frequency of the DQS inputs(s)?

The input clock frequency for inclk or outclk.

What is the frequency mode? (1) Controls internal set up of delay chains. Available options depend upon DQS frequency entered. (2) Each mode sets a different combination of delay buffer mode and DLL buffer chain length. (3)● Mode 0 – Delay buffer mode Low / DLL length 12 (4)● Mode 1 – Delay buffer mode High / DLL length 16 (5)● Mode 2 – Delay buffer mode High / DLL length 12 (6)● Mode 3 – Delay buffer mode High / DLL length 10 (7)● Custom Mode – Allows user to directly set delay buffer mode and DLL

buffer chain length.

What is the delay buffer mode? (1)

Only available in custom frequency mode. Delay buffers can be set for high or low delay modes.

What is the DLL delay chain length? (1)

Option only available in custom frequency mode. A delay chain length of 10, 12, or 16 buffers may be implemented.

How much phase shifting would you like to use for the DQS clock?

Select phase-shift with pull-down menu of 4 values. Values calculated from previously specified delay buffer mode and DLL delay chain setting.

Allow DQS to be disabled during read post-amble (1)

Inhibits ddioinclk port during read post-amble (when DQS transitions from 0 to Z). This stops ddioinclk creating false clocks as DQS goes into tristate. Device architecture cannot implement this option on DQSn port, so if this option is enabled, DQSn port may only be used as an output (or left used). ddioinclk is inhibited by a register clocked by DLL delayed DQS. dqs_areset and dqs_sreset ports control this register. User must wire dqs_sreset to GND due to architectural constraints and control ddioinclk using dqs_areset.

How many valid half cycles of the inclk input should pass before the DLL simulates a lock?

Only affects simulation, has no affect on actual device operation. Use to reduce number of clock cycles for which a simulation must be run before DLL locks. By setting this to 1, DLL immediately locks and simulation can begin transferring data.



How many invalid half clock cycles of the inclk input should pass before the DLL simulates a loss of lock? (8)

Only affects simulation, has no affect on actual device operation. Use to reduce number of clock cycles for which a simulation must be run before DLL locks. By setting this to 1, DLL immediately locks and simulation can begin transferring data.

Notes for Table 2–4:(1) Stratix, Stratix GX, and HardCopy Stratix devices do not support this feature. This option is disabled in the wizard

if the Stratix, Stratix GX, or HardCopy Stratix device family is selected.(2) Low/high refers to jitter mode. The DLL in Stratix II device DQS phase-shift circuitry can operate between 100 and

300 MHz in either fast lock mode or low jitter mode. The fast lock mode requires fewer clock cycles to calculate the input clock period, but the low jitter mode is more accurate. The DQS delay settings (the up/down counter output) are updated every eight clock cycles. If the low jitter mode is enabled, the phase comparator also issues a clock-enable signal to the up/down counter notifying the counter when to update the DQS settings. In low jitter mode, the enable signal is only active when the upndn signal is incremented or decremented by 4, otherwise the clock-enable is off and the DQS delay settings do not get updated. This enable signal is always active if the DLL is in the fast lock mode.

(3) Low Jitter mode (Mode 0) is typically used for <167 MHz. High Jitter mode is typically used for >167 MHz.(4) Use option 0 normally. This selection allows you to disable the DQS updates during a memory read cycle, making

the interface more reliable.(5) The 16 refers to the number of delay elements in the DLL equaling 360°. A setting of 16 means each element = 22.5°;

in other words, 4 elements equals 90°. You should set the length to 16 under medium-frequency operation, or 10 for very high-frequency operation.

(6) The 12 refers to the number of delay elements in the DLL equaling 360°. A setting of 12 means each element = 30°; in other words, 3 elements equals 90°. You should set the length to 12 under low- or high-frequency operation.

(7) The 10 refers to the number of delay elements in the DLL equaling 360°. You should set the length to 10 for very high-frequency operation.

(8) Stratix II devices do not support this feature, and the option is disabled in the wizard for these devices.




Getting Started

On page 5 of the altdqs wizard, specify the output register options (Figure 2–10).

Figure 2–10. altdqs Wizard, Page 5




What effect should the dqs_areset port have on output registers?

Use dqs_areset to asynchronously preset or clear output registers. If set to none, port is not instantiated and user has the option to specify the power-up state of the output registers.

What effect should the dqs_sreset port have on output registers? (1)

Use dqs_sreset port to synchronously preset or clear output registers. If set to none, port is not instantiated. (2)

How should the output registers power-up? (1)

If none option is selected on dqs_areset port, use this option to specify power up condition of output registers.



On page 6 of the altdqs wizard, specify the output enable register options (Figure 2–11).


Use clock enable for the output register (3)

Create outclkena port (if not implemented for the output registers). Use as a clock enable for output registers.

Notes for Table 2–5:(1) Cyclone II devices do not support this feature. Option is disabled when Cyclone II device family is selected.(2) This option is not available for Stratix II devices if the option Allow DQS to be disabled during read post-amble

has been selected on a previous page of the wizard. Refer to Table 2–4 on page 2–13.(3) This option is enabled only when Register the output enable option is turned on in page 3 of the wizard.




Getting Started


On page 7 of the altdqs wizard, set the jitter/lock speed and specify how you want to use the dqsn_padio port (Figure 2–12 on page 2–18).

1 This page is not available for Stratix, Stratix GX, and HardCopy Stratix device families. For Cyclone II devices, this page is available only if the Allow DQS to be disabled during read post-amble option has been selected on page 3 of the wizard.

Table 2–6. altdqs MegaWizard Plug-in Manager Page 6 Options


What effect should the dqs_areset port have on output enable registers?

Use dqs_areset port to asynchronously preset or clear output enable registers. If set to none, port is not instantiated and user has the option to specify the power-up state of output enable registers.

What effect should the dqs_sreset port have on output enable registers? (1)

Use dqs_areset port to synchronously preset or clear output enable registers. If set to none, port is not instantiated. (2)

How should the output enable registers power-up? (1)

If none is selected for dqs_areset port, use this option to specify power-up condition of output enable registers.

Hold output drive at high impedance for an extra half-clock cycle when output enable goes high

Use to delay DQS write mode by half a clock cycle. The DQS transitions from Z to 0, providing a cleaner start to sequence than a Z to 1 transition.

Use clock enable for the output enable register

Create outclkena port (if not implemented for output enable register). Use as a clock-enable for output enable register.

Notes for Table 2–6:(1) Cyclone II devices do not support this feature. Option is disabled when Cyclone II device family is selected.(2) This option is not available for Stratix II devices if the option Allow DQS to be disabled during read post-amble

has been selected on a previous page of the wizard. Refer to Table 2–4 on page 2–13.



Figure 2–12. altdqs Wizard, Page 7 (Stratix II Device Family)


Table 2–7. altdqs MegaWizard Plug-in Manager Page 7 Options Notes (1), (2)


How do you want to use the dqsn_padio port?

Use negative DQS pin as an input during read cycles, and output during write cycles or a bidirectional signal for read and write.

If the option Allow DQS to be disabled during read post amble was selected on page 3, only Not used and Output modes are available. If Allow DQS to be disabled during read post-amble was not selected on page 3, all modes are available.

What is the phase shift when used in timing analysis?

This is the phase shift amount (0° , 30° , 60° , 90° , 120° ) assumed during timing analysis. This is to compute the static delay during timing analysis.

This option is only available if the Stratix II, Stratix II GX, or HardCopy II device families are selected.

Notes for Table 2–7:(1) Cyclone II devices do not support this feature. This option is disabled if the Cyclone II device family is selected.(2) For jitter specifications, refer to the Stratix II Device Handbook.


Getting Started

On page 8 of the altdqs wizard, specify the DQS delay chain settings (Figure 2–13). Note that this page is only available when the DLL feedback loop counter is selected to control the DQS/nDQS delay chains.

Figure 2–13. altdqs Wizard, Page 8 (Stratix II Device Family)




Table 2–8. altdqs MegaWizard Plug-in Manager Page 8 Options (Stratix II Devices)(1)


Offset options for DQS/nDQS delay chain

Allow tuning of DQS delay chain. Depending on settings from page 4 of wizard, offset applies either a coarse or fine delay. (2)

When a static delay is added, value of delay is equivalent to offset value multiplied by coarse or fine offset buffer delay. If a dynamic delay is selected, a dll_offset port is added to the megafunction. Unsigned integer values on dll_offset may then be added, subtracted, or dynamically controlled with a dll_addsub port by selecting one of the options. For static offset, the value is added to the DLL feedback counter and output on the dll_delayctrlout output bus. Legal integer values are –63 to 63.

Enable the latches for the DQS delay chain setting

These latches ensure that the offset value is not changed while the DQS is transitioning and also ensures whether the DQS delay buffer control signals are latched or not.

Create reset for the DLL If enabled, a reset input is added to clear the DLL.

Notes for Table 2–8:(1) This page is available only for the Stratix II device family. This option is disabled if the Stratix, Stratix GX, or

Cyclone II device family is selected.(2) Refer to Table 2–4 on page 2–13 for more information.


Getting Started

On page 9 of the altdqs wizard, specify the files you wish to have generated for your custom megafunction. The gray check marks indicate files that are always generated; the other files are optional and are generated only if selected (indicated by a red check mark) (Figure 2–14).

Figure 2–14. altdqs Wizard, Page 9 Summary

f For port and parameter details, refer to Chapter 3, Specifications in this User Guide.


Inferring Megafunctions from HDL Code

Inferring Megafunctions from HDL Code

Synthesis tools, including the Quartus II integrated synthesis, recognize certain types of HDL code and automatically infer the appropriate megafunction when a megafunction will provide optimal results. That is, the Quartus II software uses the Altera megafunction code when compiling your design, even though you did not specifically instantiate the megafunction. The Quartus II software infers megafunctions because they are optimized for Altera devices, so the area, performance, or both may be better than generic HDL code. Additionally, you must use megafunctions to access certain Altera architecture-specific features such as memory, DSP blocks, and shift registers, that generally provide improved performance compared with basic logic elements.

f Refer to the Design Guidelines and Recommended HDL Coding Styles chapters in volume 1 of the Quartus II Handbook for more information.

Instantiating Megafunctions in HDL Code

When you use the MegaWizard Plug-In Manager to set up and parameterize a megafunction, it creates either a VHDL or Verilog HDL wrapper file that instantiates the megafunction (a black-box methodology). For some megafunctions, you can generate a fully synthesizable netlist for improved results with EDA synthesis tools such as Synplify and Precision RTL Synthesis (a clear-box methodology). As for this megafunction, the clear-box model is automatically selected and fixed prior to megafunction creation.

f Both clear- and black-box methodologies are described in the support chapters in the Synthesis section of volume 1 of the Quartus II Handbook.

Identifying a Megafunction after Compilation

During compilation with the Quartus II software, analysis and elaboration is performed to build the structure of your design. Locate your megafunction in the Project Navigator window by expanding the compilation hierarchy and locating the megafunction by its name.

Similarly, to search for node names within the megafunction (using the Node Finder), click Browse (…) in the Look in box and select the megafunction in the Hierarchy box.


Getting Started

Simulation The Quartus II Simulation tool provides an easy-to-use, integrated solution for performing simulations. The following sections describe the simulation options.

Quartus II Simulation

With the Quartus II Simulator, you can perform two types of simulations: functional and timing. A functional simulation in the Quartus II program enables you to verify the logical operation of your design without taking into consideration the timing delays in the FPGA. This simulation is performed using only your RTL code. When performing a functional simulation, you are able to view signals that exist before synthesis. You can find these signals with the Registers: pre-synthesis, Design Entry, or Pin filters in the Node Finder. The top-level ports of megafunctions are found using these three filters.

In contrast, timing simulation in the Quartus II software verifies the operation of your design with annotated timing information. This simulation is performed using the post place-and-route netlist. When performing a timing simulation, you are able to view signals that exist after place and route. These signals are found with the Post-Compilation filter of the Node Finder. During synthesis and place-and-route, the names of your RTL signals will change. Therefore, it might be difficult to find signals from your megafunction instantiation in the Post-Compilation filter. However, if you want to preserve the names of your signals during the synthesis and place-and-route stages, you must use the synthesis attributes keep or preserve. These are Verilog HDL and VHDL synthesis attributes that direct analysis & synthesis to keep a particular wire, register, or node intact. You can use these synthesis attributes to keep a combinational logic node so you can observe the node during simulation.

f For more information, refer to the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook.

EDA Simulation

Depending on which simulation tool you are using, refer to the appropriate chapter in the Simulation section in volume 3 of the Quartus II Handbook. These tool-specific chapters show you how to perform functional and gate-level timing simulations that include the megafunctions, including the necessary files and directories where the files are located. Also the clear-box models for this Megafunction can be used during functional simulation.


SignalTap II Embedded Logic Analyzer

SignalTap II Embedded Logic Analyzer

The SignalTap® II embedded logic analyzer provides you with a method of debugging all of the Altera megafunctions within your design. With the SignalTap II embedded logic analyzer, you can capture and analyze data samples for the top-level ports of the Altera megafunctions in your design while your system is running at full speed.

To monitor signals from your Altera megafunctions, you must first configure the SignalTap II embedded logic analyzer in the Quartus II software, and then include the analyzer as part of your Quartus II project. The Quartus II software will then seamlessly embed the analyzer along with your design in the selected device.

f For more information about using the SignalTap II embedded logic analyzer, refer to the Design Debugging Using the SignalTap II Embedded Logic Analyzer and the In-System Debugging Using External Logic Analyzers chapters in the volume 3 of the Quartus II Handbook.

Design Example: Implement DDR I/O Interface

This design example uses the altdq and altdqs megafunction to implement DDR I/O interface. This example uses the MegaWizard Plug-In Manager in the Quartus II software. As you go through the wizard, each page is described in detail.

Design Files

The design files are available in the Quartus II Projects section on the Design Examples page of the Altera web site, www.altera.com.

Select the “Examples for altdq & altdqs Megafunction User Guide” link from the examples page to download the design files.

Example In this example, you perform the following tasks:

■ Create DDR I/O interface using the altdq and altdqs megafunctions and the MegaWizard Plug-in Manager

■ Implement the design and assign EP2C5T144C6 device to the project■ Compile and simulate the design

Create an altdq Megafunction

1. Unzip the altdq_dqs_DesignExample.zip to any working directory.

2. In the Quartus II software, open the dq_dqs_ex.qar project.

3. On the Tools menu, click MegaWizard Plug-In Manager.


Getting Started

4. Select Create a new custom megafunction variation, and click Next. The MegaWizard Plug-In Manager page appears (Figure 2–15).

Figure 2–15. MegaWizard Plug-In Manager (page 2a)

5. From the list of megafunctions in the I/O folder, select ALTDQ.

6. To answer Which device family will you be using?, select Cyclone II.

7. To answer Which type of output file do you want to create?, select Verilog HDL.

8. To answer What name do you want for the output file?, browse to the folder dq_dqs_ex_1.0_restored. Name the file dq. (If asked if it is okay to overwrite an existing file, click OK).

9. Click Next. Figure 2–16 appears.


Example

Figure 2–16. altdq Wizard, Page 3

10. To answer How many DQ pins would you like?, select 8.

11. To answer Which asynchronous reset port would you like?, select Asynchronous clear (aclr).

12. Turn off the Create a clock enable port for each clock port option.

13. Turn on the Create an output enable port option.

14. Turn off the Register output enable, Delay switch-on by a half clock cycle, Invert input clock and Use ‘ddioinclk’ port (from DQSn bus) options.



Getting Started

Figure 2–17. altdq Wizard, Page 4, Simulation Libraries

Page 4 of the wizard indicates the simulation model file needed to properly simulate the generated design files. No further input is needed. Click Next. Figure 2–18 appears.


Example

Figure 2–18. altdq Wizard, Page 5 Summary

The final page of the wizard shows the files that are generated for your custom megafunction variation. The gray check marks indicate files that are always generated; the other files are optional and are generated only if selected (indicated by a red check mark). Turn on the boxes to select the files that you want the wizard to generate.

16. Turn on the Instantiation template file and Verilog 'Black Box' declaration file options.

17. Turn off the AHDL Include file, VHDL Component declaration file, and Quartus symbol file options.

18. Click Finish.

The altdq module is now built.


Getting Started

Now create an altdqs megafunction.

1. On the Tools menu, click MegaWizard Plug-In Manager.

2. Select Create a new custom megafunction variation, and click Next. The MegaWizard Plug-In Manager page displays (Figure 2–19).


3. From the list of megafunctions in the I/O folder, select ALTDQS.

4. To answer Which device family will you be using?, select Cyclone II.

5. To answer Which type of output file do you want to create?, select Verilog HDL.

6. To answer What name do you want for the output file?, browse to the folder dq_dqs_ex_1.0_restored. Name the file dqs. (If asked if it is okay to overwrite an existing file, click OK).


Example



8. To answer How many DQS pins would you like?, select 1 from the drop-down menu.

9. To answer What is the frequency of the DQS input(s)?, select 133.333 MHz.

10. Turn on the Create an output enable port option.

11. Turn off the Register the output enable option.

12. To answer How should the delay chain be specified?, select As delay chain setting and select 50.

13. Turn off the Allow DQS to be disabled during read post-amble option.

14. Turn off the Invert ‘dqs_padio’ port (when driving output) option.


Getting Started



16. To answer What effect should the ‘dqs_areset’ port have on output registers?, select Clear.



Example


18. To answer How do you want to use the ‘dqsn_padio’ port?, select Not Used.



Getting Started

Figure 2–23. altdqs Wizard, Page 6, Simulation Libraries

Page 6 of the wizard indicates the simulation model file needed to properly simulate the generated design files. No further input is needed. Click Next. Figure 2–24 appears.


Example

Figure 2–24. altdqs Wizard, Page 7, Summary

20. Turn on the Instantiation template file and Verilog 'Black Box' declaration file options.

21. Turn off the AHDL Include file, VHDL Component declaration file, and Quartus symbol file options.

22. Click Finish.

The altdqs module is now built.


Getting Started

Combine the altdq & altdqs Modules to Create a DDR I/O Interface

This section describes how to create a new top-level Verilog HDL file.

1. With the dq_dqs_ex.qar project open, open the dq_dqs_ex.v file.

2. Ensure that all file names are named correctly in the Verilog code.

3. Instantiate the dq and dqs functions in the top level file dq_dqs_ex.v.

4. On the Project menu, click Add/Remove Files in Project. The Settings window appears.

5. In the Settings window, click (...) to browse to the dq_dqs_ex.v file in the project folder (Figure 2–25). Click Open, then Add to add the file to the project.


Example

Figure 2–25. Settings—Add File

6. Click OK.

The top-level file is now added to the project. You have now created the complete design file. The block diagram can be viewed after compiling the project via the RTL viewer. (Note that the schematic shown in Figure 2–26 is not included in the project file.)


Getting Started

Figure 2–26. DDR I/O Interface Using altdq & altdqs

Implement the DDR I/O Interface Design

This section describes how to assign the EP2C5T144C6 device to the project and compile the project.

1. With the dq_dqs_ex.qar project open, on the Assignments menu, click Settings. The Settings dialog box appears (Figure 2–27).


Example

Figure 2–27. Settings—Device Selection

2. In the Category list on the left, select Device.

3. In the Family list, select Cyclone II.

4. In the Target device list, select Specific device selected in ‘Available devices’ list.

5. In the Available devices list, select EP2C5T144C6.

6. Leave the other options on the Settings page in the default state and click OK.

7. On the Processing menu, click Start Compilation, or click the Start

Compilation button to compile the design.

8. When the Full compilation was successful box displays, click OK.


Getting Started

Functional Results—Simulate DDR I/O Interface Design in the Quartus II Simulator

This section describes how to verify the design example you just created by simulating the design using the Quartus II Simulator. To set up the Quartus II Simulator, perform the following steps:

1. On the Processing menu, click Generate Functional Simulation Netlist.

2. When the Functional Simulation Netlist Generation was successful box displays, click OK.

3. On the Assignments menu, click Simulator Settings. The Settings dialog box appears (Figure 2–28).

Figure 2–28. Functional Simulation Settings


Example

a. From the Category list, select Simulator Settings.

b. From the Simulation mode list, select Functional.

c. In the Simulation input box, type dq_dqs_ex_ip.vwf or click Browse (...) to select the file in the project folder.

d. Turn on Run simulation until all vector stimuli are used.

e. Turn on the Automatically add pins to simulation output waveforms and Simulation coverage reporting options.

f. Turn off Check outputs and Overwrite simulation input file with simulation results.

g. Click OK.

4. On the Processing menu, click Start Simulation or click the Start

Simulation button to run a simulation.

5. When the Simulation was successful box displays, click OK.

6. The Simulation Report window appears. Verify the simulation waveform results (Figure 2–29).


Getting Started

Figure 2–29. Simulation Waveform

Functional Results—Simulate the DDR I/O Interface Design in ModelSim-Altera Tool

Simulate the design in the ModelSim® tool to compare the results of both simulators.

This User Guide assumes that you are familiar with using the ModelSim-Altera tool before trying out the design example. If you are unfamiliar with this tool, refer to http://www.altera.com/support/ software/products/modelsim/mod-modelsim.html, which is a support page for the ModelSim-Altera tool. There are various links to topics such as installation, usage, and troubleshooting.

Set up the ModelSim-Altera simulator by performing the following steps.

1. Unzip the altdq_dqs_msim.zip file to any working directory on your PC.

2. Browse to the folder in which you unzipped the files and open the altdqdqs.do file in a text editor.


Example

3. In line 1 of the altdqdqs.do file, replace <insert_directory_path_here> with the directory path of the appropriate library files. For example, C:/Modeltech_ae/altera/verilog/cycloneii

4. On the File menu, click Save.

5. Start ModelSim-Altera.

6. On the File menu, click Change Directory.

7. Select the folder in which you unzipped the files. Click OK.

8. On the Tools menu, click Execute Macro.

9. Select the altdqdqs.do file and click Open. This is a script file for ModelSim that automates all the necessary settings for the simulation.

10. Verify the results shown in the Waveform Viewer window.

You may need to rearrange signals, remove redundant signals, and change the radix to suit the results in the Quartus II Simulator. Figure 2–30 shows the expected simulation results in ModelSim.

Figure 2–30. ModelSim Simulation Results


Getting Started

Conclusion The Quartus II software provides parameterizable megafunctions ranging from simple arithmetic units, such as adders and counters, to advanced phase-locked loop (PLL) blocks, multipliers, and memory structures. These megafunctions are performance-optimized for Altera devices and therefore provide more efficient logic synthesis and device implementation, because they automate the coding process and save valuable design time. You should use these functions during design implementation so you can consistently meet your design goals.


Example


Chapter 3. Specifications

Ports & Parameters

The options listed in this section describe all of the ports and parameters that are available for each device to customize the altdq and altdqs megafunctions according to your application.

f Refer to the latest version of the Quartus® II Help for the most current information about the ports and parameters for these megafunctions.

The parameter details are only relevant for users who by-pass the MegaWizard® Plug-In Manager interface and use the megafunction as a directly parameterized instantiation in their design. The details of these parameters are hidden from the user of the MegaWizard Plug-In Manager interface.

altdq Megafunction

Figure 3–1 shows the ports and parameters for the altdq megafunction.

Figure 3–1. altdq Port & Parameter Description


Ports & Parameters

Table 3–1 shows the input ports, Table 3–2 shows the output ports, Table 3–3 shows the bidirectional ports, and Table 3–4 shows the parameters for the altdq megafunction.

Table 3–1. altdq Megafunction Input Ports

Port Name

Requ

ired

Description Comments

aclr No Asynchronous clear input. If the aclr port is connected, the aset port cannot be used.

aset No Asynchronous set input. If the aset port is connected, the aclr port cannot be used.

datain_h[] Yes Input data to be output to the padio port at the rising edge of the outclock port.

Input port [NUMBER_OF_DQ-1..0] wide.

datain_l[] Yes Input data to be output to the padio port at the falling edge of the outclock port.

Input port [NUMBER_OF_DQ-1..0] wide.

ddioinclk No Clock input for the negative-edge input register.

If omitted, the default is GND. (1)

inclock Yes Clock input that drives the data strobe. —

inclocken No Clock enable for the inclock port —

oe No Output enable signal. The oe port defaults to VCC when enabled.

outclock Yes Clock signal for the output and oe registers. —

outclocken No Clock enable signal for each clock port. —

Note for Table 3–1:(1) Available for Stratix® II devices only.

Table 3–2. altdq Megafunction Output Ports

Port Name

Requ

ired


dataout[] Yes Data output from the input ports at the rising edge of the inclock signal.

Output port [NUMBER_OF_DQ-1..0] wide.

dataout_ddio[] Yes Data output from the input ports at the falling edge of the inclock signal.

Output port [NUMBER_OF_DQ-1..0] wide.


Specifications

Table 3–3. altdq Megafunction Bidirectional Ports

Port Name

Requ

ired


padio[] Yes Bidirectional double data rate (DDR) port that should directly feed a bidirectional pin in the top-level design.

Bidirectional port [NUMBER_OF_DQ-1..0] wide.

Table 3–4. altdq Megafunction Parameters

Parameter TypeRe

quire

dComments

DDIOINCLK_INPUT String No Specifies whether to feed the ddioinclk ports. Values are DQSB_BUS or NEGATED_INCLK. If omitted, the default is NEGATED_INCLK. The DQSB_BUS value can be used with Stratix II devices only.

EXTEND_OE_DISABLE String No Specifies whether to use the second OE register. Values are TRUE or FALSE. If omitted, the default is FALSE.

INVERT_INPUT_CLOCKS String No Specifies whether to invert the input clocks. The INVERT_INPUT_CLOCKS parameter should be used with DDR memory. When the input clock is inverted, the first bit of data is captured on a rising-edge clock; when the input clock in not inverted, the first bit of data is captured on a falling-edge clock.

NUMBER_OF_DQ Integer Yes Specifies the number of DQ pins.

OE_REG String No Specifies whether to register the oe port. Values are REGISTERED or UNREGISTERED.

POWER_UP_HIGH String No Specifies the power-up condition of the I/O registers. Values are ON or OFF. If omitted, the default is OFF.

LPM_HINT String No Allows you to specify Altera®-specific parameters in VHDL Design Files (.vhd). The default is UNUSED.

LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. Create the altdq megafunction with the MegaWizard Plug-in Manager to calculate the value for this parameter.


Ports & Parameters

altdqs Megafunction

Figure 3–2 shows the ports and parameters for the altdqs megafunction.

Figure 3–2. altdqs Port & Parameter Description

Table 3–5 shows the input ports, Table 3–6 shows the output ports, Table 3–7 shows the bidirectional ports, and Table 3–8 shows the parameters for the altdqs megafunction.

Table 3–5. altdqs Megafunction Input Ports (Part 1 of 2)

Port Name

Requ

ired


dqs_areset No Asynchronous set or reset signal for DQS output and output enable registers.

—

dqs_datain_h[] Yes Data input port for DQS output register which outputs on rising edge of outclk port.

Input port [NUMBER_OF_DQS-1..0] wide.

dqs_datain_l[] Yes Data input port for DQS output register which outputs on falling edge of outclk port.

Input port [NUMBER_OF_DQS-1..0] wide.

dqs_sreset No Synchronous set or reset signal for DQS output and output enable registers.

—

inclk Yes System reference clock port that drives DLL. —

oe No Output enable for DQS output registers. The oe port defaults to VCC when enabled.

outclk Yes Clock to DQS output and output enable registers.

—

outclkena No Clock enable port for DQS output and oe registers.

The oe port defaults to VCC when enabled.


Specifications

dll_addnsub No Bus for DLL delay setting offset that adds or subtracts.

If omitted, value is GND. (1)

dll_upndnin No Data input for DLL delay setting offset. If omitted, value is GND. (1)

dll_offset[] No Data input for DLL delay setting offset. Input port [5..0] wide. If omitted, value is GND. (1)

dqs_delayctrlin[] No Control input to DQS delay buffers. Input port [5..0] wide. If omitted, value is GND. (1)

dll_upndninclkena No Clock enable for DLL delay setting offset. If omitted, value is GND. (1)

enable_dqs No Specifies whether DQS is disabled during post-amble read.

enable_dqs port available only if GATED_DQS parameter is specified to TRUE. (2)

Note for Table 3–5:(1) Available for Stratix II devices only.(2) Available for Cyclone® II devices only.

Table 3–6. altdqs Megafunction Output Ports

Port Name

Requ

ired


dqinclk[] Yes Phase shifted DQS strobe generated for DQ input registers from the DQS input.

Width of bus is equal to number of DQS pins. Output port [NUMBER_OF_DQS-1..0] wide.

dll_delayctrlout[] No Delay buffer setting output. If omitted, value is GND. Output port [5..0] wide. (1)

dll_upndnout No Output for DLL phase comparator.

(1)

dqddioinclk[] No Clocks generated for DQ negative-edge input registers from DQSn pins.

The width of the bus is equal to the number of DQS pins. Output port [NUMBER_OF_DQS-1..0] wide. (1)

dqsundelayedout No Undelayed outputs from the DQS pins.

Width of bus is equal to number of DQS pins. Output port [NUMBER_OF_DQS-1..0] wide.

Note for Table 3–6:(1) Available for Stratix II devices only.

Table 3–5. altdqs Megafunction Input Ports (Part 2 of 2)

Port Name

Requ

ired



Ports & Parameters

Table 3–7. altdqs Megafunction Bidirectional Ports

Port Name

Requ

ired


dqs_padio[] Yes Bidirectional DQS pins. Width of bus is equal to number of DQS pins. Bidirectional port [NUMBER_OF_DQS-1..0] wide.

dqsn_padio[] No Bidirectional DQSn pins. Width of bus is equal to number of DQSn pins. Bidirectional port [NUMBER_OF_DQS-1..0] wide. (1)

Note for Table 3–7:(1) Available for Stratix II devices only.

Table 3–8. altdqs Megafunction Parameters (Part 1 of 4)

Parameter Type

Requ

ired

Comments

DLL_PHASE_SHIFT String Yes Specifies DLL phase shift. Values are 0, 72, or 90.

DQS_OE_ASYNC_RESET String No Specifies whether dqs_areset port clears, presets, or has no effect on the oe register. Values are CLEAR, PRESET, or NONE. If DQS_OE_ASYNC_RESET parameter is specified to CLEAR or PRESET, dqs_areset port is required. If omitted, default is NONE.

DQS_OE_POWER_UP String No Specifies power-up condition of oe registers. Values are HIGH or LOW. If omitted, default is LOW.

DQS_OE_REGISTER_MODE String No Specifies whether oe port is registered. Values are REGISTER or NONE. If omitted, default is NONE.

DQS_OE_SYNC_RESET String No Specifies whether dqs_sreset port clears, presets, or has no effect on oe register. Values are CLEAR, PRESET, or NONE. If DQS_OE_SYNC_RESET parameter is specified to CLEAR or PRESET, dqs_sreset port is required. If omitted, default is NONE.

DQS_OPEN_DRAIN_OUTPUT String No Specifies whether to use open drain mode. Values are TRUE or FALSE. If omitted, default is FALSE.

DQS_OUTPUT_ASYNC_RESET

String No Specifies whether dqs_areset port clears, presets, or has no effect on the DQS output registers. Values are CLEAR, PRESET, or NONE. If DQS_OUTPUT_ASYNC_RESET port is specified to CLEAR or PRESET, dqs_areset is required. If omitted, default is NONE.

DQS_OUTPUT_POWER_UP String No Specifies power-up condition of DQS output registers. Values are HIGH or LOW. If omitted, default is LOW.


Specifications

DQS_OUTPUT_SYNC_RESET String No Specifies whether the dqs_sreset port clears, presets, or has no effect on DQS output registers. Values are CLEAR, PRESET, or NONE. If DQS_OUTPUT_SYNC_RESET port is specified to CLEAR or PRESET, dqs_sreset is required. If omitted, default is NONE.

EXTEND_OE_DISABLE String No Specifies whether to use second oe register. Values are TRUE or FALSE. When EXTEND_OE_DISABLE is set to TRUE, output drive is held at high impedance for an extra half clock cycle when oe port goes high.

INPUT_FREQUENCY String No Specifies frequency of DQS inputs and system reference clock.

NUMBER_OF_DQS Integer Yes Specifies number of DQS pins that are implemented.

SIM_INVALID_LOCK Integer No Specifies number of half-cycles that DLL keeps signal locked after a bad clock is detected. The default is 32 half-cycles.

SIM_VALID_LOCK Integer No Specifies number of half-cycles required before the DLL locks onto signal. Default is 1.

TIE_OFF_DQS_OUTPUT_CLOCK_ENABLE

String No Specifies whether clock enable for output registers is tied-off (does not affect the output registers). Values are TRUE or FALSE. If omitted, default is FALSE.

TIE_OFF_DQS_OE_CLOCK_ENABLE

String No Specifies whether clock enable for oe registers that are controlled by outclkena port should be tied off. Values are TRUE or FALSE. If omitted, default is FALSE.

DELAY_BUFFER_MODE String No Specifies speed of DLL and DQS delay buffers. Values are LOW or HIGH. If omitted, default is LOW. (1)

DLL_DELAY_CHAIN_LENGTH

Integer No Specifies number of delay buffers used in DLL loop. Values are 0, 1, 2, 3, or 4. If omitted, default is 3. (1)

DLL_DELAYCTRL_MODE String No Specifies delay control mode used to feed DQS and DQSn delay buffers. Values are NORMAL, NORMAL_OFFSET, OFFSET_ONLY, or NONE. If omitted, default is NORMAL. (1)

DLL_JITTER_REDUCTION String No Enables or disables jitter reduction on dll_delayctrlout output ports. Values are TRUE or FALSE. If omitted, default is TRUE. (1)

DLL_OFFSETCTRL_MODE String No Specifies DLL phase offset mode used with DQS delay buffer control. Values are DYNAMIC_ADD, DYNAMIC_SUB, DYNAMIC_ADDNSUB, STATIC, or NONE. If omitted, default is NONE. (1)


Parameter Type

Requ

ired

Comments


Ports & Parameters

DLL_STATIC_OFFSET Integer No Adds a value to DLL feedback counter and output on dll_delayctrlout output bus. Legal integer values are -63 to 63. If omitted, default is 0. If DLL_OFFSETCTRL_MODE parameter is set to a value other than STATIC, the DLL_STATIC_OFFSET parameter is ignored. (1)

DLL_USE_UPNDNIN String No Specifies whether to use dll_upndnin port to update DLL counter. Values are TRUE or FALSE. If omitted, default is FALSE. If DLL_USE_UPNDNIN parameter is set to TRUE, DLL_JITTER_REDUCTION parameter must be set to FALSE. (1)

DLL_USE_UPNDNINCLKENA String No Specifies whether to use dll_upndninclkena port as a clock enable for DLL counter. Values are TRUE or FALSE. If omitted, default is FALSE. If DLL_USE_UPNDNINCLKENA parameter is set to TRUE, the DLL_USE_UPNDNINCLKENA parameter overrides DLL control of the clock enable for DLL counter. (1)

DQS_CTRL_LATCHES_ENABLE

String No Enables or disables latches for DQS delay buffer control signals. Values are TRUE or FALSE. If omitted, default is TRUE. If DLL_DELAYCTRL_MODE parameter is set to NONE, DQS_CTRL_LATCHES_ENABLE parameter cannot be set to TRUE. (1)

DQS_DELAY_CHAIN_LENGTH

Integer No Specifies number of delay buffers used in DQS delay chain. Values are 0, 1, 2, 3, or 4. If omitted, default is 3. (1)

DQS_EDGE_DETECT_ENABLE

String No Specifies whether edge detection prevents updates to DQS delay buffer control latches during a DQS transition. Values are TRUE or FALSE. If omitted, default is FALSE. If DQS_CTRL_LATCHES_ENABLE parameter is set to FALSE, DQS_EDGE_DETECT_ENABLE parameter cannot be set to TRUE. (1)

DQS_USE_DEDICATED_DELAYCTRLIN

String No Specifies whether DLL directly feeds DQS delay buffer control signals. Values are TRUE or FALSE. If omitted, default is FALSE. If DLL_DELAYCTRL_MODE parameter is set to NONE, DQS_USE_DEDICATED_DELAYCTRLIN parameter cannot be set to TRUE. If DQS_CTRL_LATCHES_ENABLE parameter is set to TRUE, DQS_USE_DEDICATED_DELAYCTRLIN parameter cannot be set to FALSE. (1)

DQSN_MODE String No Specifies whether to use dqsb_padio port. Values are NONE, INPUT, OUTPUT, or BIDIR. If omitted, default is NONE. If DQS_CTRL_LATCHES_ENABLE parameter is set to TRUE, DQS_USE_DEDICATED_DELAYCTRLIN parameter cannot be set to FALSE. (1)


Parameter Type

Requ

ired

Comments


Specifications

GATED_DQS String No Specifies whether to AND DQS output with a register clocked by delayed DQS signal. Values are TRUE or FALSE. If omitted, default is FALSE. GATED_DQS parameter can only be used when DQSN_MODE parameter is set to NONE or OUTPUT. (2)

DELAY_CHAIN_MODE String No Specifies delay chain mode.(1) There are two modes:● DLL Feedback Loop Counter used to control the DQS/nDQS

delay chains● No DLL used

DQS_DELAY_CHAIN_SETTING

Integer No Specifies value of delay chain. Legal values range from 0 through 63. DQS_DELAY_CHAIN_SETTING parameter is ignored if HAS_DQS_DELAY_REQUIREMENT parameter is specified to TRUE. (3)

DQS_DELAY_REQUIREMENT String No Specifies delay requirement value. This parameter is available only if HAS_DQS_DELAY_REQUIREMENT parameter is specified to TRUE.

HAS_DQS_DELAY_REQUIREMENT

String No Specifies whether to use a delay requirement. Values are TRUE or FALSE. If omitted, default is FALSE.

LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). Default is UNUSED.

LPM_TYPE String No Identifies library of parameterized modules (LPM) entity name in VHDL Design Files.

INTENDED_DEVICE_FAMILY

String No This parameter is used for modeling and behavioral simulation purposes. Create the altdqs megafunction with the MegaWizard Plug-in Manager to calculate the value for this parameter.

Notes for Table 3–8:(1) Available for Stratix II devices only.(2) Available for Stratix II and Cyclone II devices only.(3) Available for Cyclone II devices only.


Parameter Type

Requ

ired

Comments


Ports & Parameters

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