ald dielectrics and interface engineering for sic mosfet ...neil/sic_workshop... · b. lee, ncsu,...

B. Lee, NCSU, 2017 ARL-MOS Workshop

ALD Dielectrics and Interface Engineering for SiC MOSFET Transistors

1

12th Annual SiC-MOS workshop, Univ. of Maryland, August 17-18, 2017

Bongmook Lee, Minseok Kang, Xiangyu Yang, Kevin Lawless and Veena Misra

Department of Electrical and Computer Engineering

North Carolina State University, Raleigh NC USA


Outline

• Introduction and Approach

• Atomic Layer Deposition

• Electrical Characteristics of ALD SiO2

• LaSiOx Interface Passivation

• Summary

2


Introduction and Approach

3

Drain

n-type substrate

n-type drift layer

p-well p-well

n+ n+p+ p+

Source SourceThermal oxide

Gate

Poor

mobility

VT

control

• Poor mobility

• Mobility / Threshold voltage (VT) trade-off

Current issues of SiC MOSFET

High interface states density (Dit)

• Carbon rich interfacial layer

• Clustered carbons

• Dangling bonds

• Channel mobility in commercial MOSFETs low ~20 cm2 V-1 s-1

• Channel can contribute up to 50% of total on-resistance

• Higher mobility Smaller chip size, lower operating oxide fields, less design constraints, lower blocking voltages etc.

channel

channelR

1∝


Approach I: Pre/Post Oxidation Treatment

4

Institution Technique Mobility VT

Auburn University POCl3 105 cm2/V·s 1 V

CNM N2O 45cm2/V·s 0.7V

Kyoto University NO 103 cm2/V·s

Tokyo University H2 27 cm2/V·s

Nara Institute POCl3 83 cm2/V-s

Auburn University Sb 80~110 cm2/V·s 1.0~1.2V

-1 0 1 2 3 4 5 6 7 8 9

0

20

40

60

80

100

120

140

160

Nara, 2010

Auburn, 2016

Xidian, 2016 CNM, 2017

Ascatron, 2016Auburn, 2016

Kyoto, 2016

Tokyo, 2006

Nara IST, 2010

Fie

ld e

ffect m

obili

ty [ c

m2/V

s]

Threshold voltage [V]

Black: Thermal oxide + NO anneal

- Interface passivation before or after thermal oxidation- Enhanced mobility but low device VT

- Hydrogen, Nitrogen, Phosphorus, Arsenic, Antimony


Approach II: Deposited Dielectrics

Institution Annealing Technique Mobility VT

NCSU N2O ALD 133 cm2/V·s 3 V

DENSO CORPORATION

NO CVD 111 cm2/V·s ~ 3.5 V

Cree NO CVD 110 cm2/V·s 2V

Cree NO CVD 90 cm2/V·s < 2V

5

- Deposited oxides also show high mobility.- Device VT is 3~5V range (preferred).- Reliability and long term stability are unknown.

-1 0 1 2 3 4 5 6 7 8 9

0

20

40

60

80

100

120

140

160

NCSU, 2015

Nara, 2010

Auburn, 2016

Xidian, 2016 CNM, 2017

Ascatron, 2016Auburn, 2016

Kyoto, 2016

Tokyo, 2006

Nara IST, 2010

Fie

ld e

ffect m

obili

ty [ c

m2/V

s]

Threshold voltage [V]

Black: Thermal oxide + NO anneal

Cree, 2014

Cree, 2016

Denso, 2015

Rensselaer, 2016

CNM, 2016


Atomic Layer Deposition – A new pathway

• ALD film growth is Self-limited and based on surface reactions resulting in atomic scale deposition control (0.4A~1A per cycle)

• Provide best step coverage – for trench, DRAM capacitor, nanowire coating• Low temperature process, damage free, precise thickness control

6

Technology Backgrounder: Atomic Layer Deposition," IC Knowledge LLC, 24 April 06


ALD for Advanced Devices

7

Oxide and passivation for GaN HEMTAdvanced CMOS, sensors and Memory

-5 -4 -3 -2 -1 010

-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

A_Hf2

Dra

in C

urr

en

t (m

A/m

m)

Gate Voltage (V)

Initial

After VD =20V stress





VLD

ILD

IRD

VLG VSS

VTD

200 nm

InGaAs cap layer

InAlAs Schottky

δ-doped

InAlAs spacer

InGaAs channel

InAlAs Buffer

InP substrate

VRG

e-

(a)

c

tair=100 nm &

tAl203=0 nm

t

tair=30 nm &

tAl203=70 nm

tair=0 nm &

tAl203=100 nm

(b) (c) (d)

VRD


ALD for SiC Power Devices

8

PECVD passivation

ALD passivation

Passivation for SiC Diodes

For switch

W. Sung et. al, IEEE TED 2016

T. Hosoi et. al, ISPSD 2017.


Choice of Dielectrics for SiC Substrate

9

Eg (eV) DEc (eV) DEv (eV) kThermal Conductivity

(W/m-K)

*ThermalSiO2

8.7 2.65 2.79 3.9 1.3 Amorphous

ALD SiO2 8.72 2.85 2.61 3.9 Amorphous

ALD Al2O3 7.43 2.31 1.87 8.7 1.22 Amorphous

ALD HfAlO 6.0 1.16 1.59 11.5 Nanocrystalline

ALD HfO2 5.7 1.5 0.94 17 1.1 Crystal

*Heiji Watanabe et. al., Material Science Forum, Vol. 679, 2011, M. Nawaz, Active and Passive Electronic Components, 2016.

4H-SiCEg=3.26eV

Gate

Dielectric

DEv

DEC

SiC

Eg


ALD for SiC Gate Dielectrics

10

SiO2/SiC, Seoul Univ. (2012)

Al2O3/SiC, Electron Technology (2016) ALD on SiC, NCSU

HfO2/SiC, Warwick Univ. (2015)Al2O3/SiC, Hanyang Univ. (2015)

0 2 4 6 8 10 12 140.0

0.2

0.4

0.6

0.8

1.0

1.2D

rain

Curr

ent [u

A]

VG[V]

0

5

10

15

20

25

30

FE

Mobili

ty [cm

2/V

-s]

Vds

=0.1V

900C N2O PDA

0 2 4 6 8 10 120.0

0.2

0.4

0.6

0.8

1.0

1.2

FE

mobili

ty [cm

2/V

s]

VG [V]

Dra

in c

urr

ent [u

A]

0

5

10

15

20

25

30

Vds=0.1V

1100C N2O PDA


NCSU ALD Dielectrics on SiC

11

C-V Leakage VGS-IGS

ALD Al2O3

0 2 4 6 8 10 120.0

0.2

0.4

0.6

0.8

1.0

1.2

FE

mo

bili

ty [

cm

2/V

s]

VG [V]

Dra

in c

urr

en

t [u

A]

0

5

10

15

20

25

30

Vds=0.1V

1100C N2O PDA

0 2 4 6 8 101E-14

1E-12

1E-10

1E-8

1E-6

1E-4

Le

akage c

urr

ent [A

]

Effective field [MV/cm]

C-V Leakage VGS-IGS

ALD SiO2

ALD SiO2 shows better electrical characteristics

-4 -2 0 2 4 6 80

3

6

9

12

15

Capacitance [pF

]

VG [V]

1M Hz

100K Hz


ALD vs. Thermal SiO2

• Similar electrical characteristics were obtained between ALD SiO2and thermal SiO2 after NO anneal

• VT is still less than 1V.• 3nm transition region between SiO2

and SiC (similar to thermal)

12

S. Haney, Ph.D Dissertation, NCSU 2012


ALD SiO2 Dielectric + RTA

13

• N2O RTA anneal is much faster than furnace NO anneal and hence much less interfacial layer growth

• With ALD SiO2 + RTA N2O, similar interface states, slightly lower mobility but much positive threshold voltage were obtained.


ALD SiO2 Reliability

14 14

N+ SiC

P-epi

ALD SiO2

Gate

Source Drain

• VT is stable at room temperature

• NBTI is less than 0.1V

• Further optimization is going on for high temperature reliability.

*Detailed results will be presented at ICSCRM 2017


Long-Term Reliability

15

Gate leakage current

at 6.5MV/cmExtrapolated TDDB of

~ 105 hours at 4MV/cm

• Room temperature TDDB test is encouraging.

• Elevated TDDB test is on-going.


Our Approach toward High Mobility

16

Our approach :

• Interface engineering using Lanthanum silicate (LaSiOx)

• Damage Free SiO2 by Atomic Layer Deposition (ALD)

• Rapid thermal anneal (RTA) as the post deposition anneal (PDA) for mobility and VT control

• Minimize thermal oxidation and carbon related defects, and hence the mobility can be enhanced

Object: Separate and independent control of SiC/oxide interface and bulk of main oxide for SiC power device


Lanthanum Silicate + ALD SiO2

17

Advantages of LaSiOx:

• scavenging effect1,2

• resistant to crystallization up to

900oC1

Using ALD SiO2 on SiC:

• No substrate oxidation

• Precise thickness control

• Ideal for trench MOSFETs

• Negative charge

LaSiOx for interface engineering ALD SiO2 for gate dielectric

Scavenging effect1,2,3

ALD SiO2

SiC

LaSiOx

ALD SiO2

SiC

La2O3

PDA

How to create the LaSiOx layer?

1. J. -P. Maria et al., J. Appl. Phys., Vol. 90, No. 7, 2001. 2. H. Iwai et al., IEDM Tech. Dig., pp.625-628, 2002.3. B. Lee, NCSU Dissertation, 2010.

Reaction with SiO2 is the most important property. It is used to prevent interfacial layer formation on Si3.


MOSCAP Results with LaSiOx/SiO2

• The C-V characteristics of La containing capacitor show minimal frequency dispersion and hysteresis.

• Low field gate leakage is greatly reduced.

• The reduction is due to improved electron injection interface with less defects at the

interface.18

0.2 0.4 0.6 0.81E11

1E12

1E13

Ec-E [eV]

without LaSiOx

with LaSiOx

Dit [eV

-1cm

-2]


LaSiOx/SiO2 SiC MOSFET

19 19

LaO evaporation

in O2 at 200C

ALD SiO2 at 150C

1000C PDA in

N2O after SiO2

• 1nm LaO with leads to >

5X increase in mobility

• Maintain device VT=3V

peak = 120 cm2/V-s VT = 3.0V

Ids-Vgs and field effect (FE) mobility


Output characteristics are significantly improved by La2O3.

Output Characteristics of Lateral MOSFET

Measured device details:La2O3+SiO2

Thickness: 1nm + 30nmAfter 900 C N2O annealingW/L = 200 m/ 200mGate: TaN/W

ALD SiO2 only:Thickness: 30nmAnneal: 1100C N2OW/L = 200 m/ 200mGate: TaN/W

20


Sub-Threshold Swing

• The subthreshold swing is greatly reduced by the La-rich layer.

• Higher temperature PDA increases the swing.

21

SampleSubthreshold

swing (mV/dec)

With LaSiOx 900C

PDA100

With LaSiOx 1000C

PDA120

With LaSiOx 1100C

PDA520

ALD SiO2 1000C PDA > 1000

Dry oxide* 1200

NO 1250* 200~550

* D. Okamoto et al., IEEE Electron Device Lett., vol. 31, NO. 7, 2010.


Z-Contrast STEM Images

22

• Abrupt SiC/LaSiOx interface: lack of SiOx type interfacial layer

• The La-silicate is amorphous after 900oC PDA

SiC SiO2SiC SiO2LaSiOx

LaSiOX

ALD SiO2 ALD SiO2

Without silicate With silicate

NCSU AIF TEM/STEM


Mobility vs. Measurement Temperatures

23

Mobility T dependence

Bulk, μB ~ T-2.4

Coulomb (charge), μC ~ T

Surface Phonon, μsp ~ T-1

• The mobility of La-containing MOSFET after 900 oC and 1000 oC PDA is limited by phonon

scattering.

• In the ALD SiO2 MOSFET, the mobility is dominated by the coulomb mobility.

• The MOSFET with LaSiOx after 1100 oC PDA, the mobility could be dominated by more than

one components.

Total mobility:

*Powell et al., J. Appl. Phys., 2002.

With silicate

ALD SiO2


Reliability of LaSiO/SiO2 Dielectric

24 24

After 900oC N2O PDA only

•FGA significantly reduces the VT shift of the MOSFET with LaSiOx.

• The effect of FGA depends on the La concentration at the interface.

After 900oC N2O PDA + 800 oC FGA


Summary

• ALD SiO2 shows good overall electrical properties and similar bandgap as thermal oxide on SiC.

• By combining interfacial LaSiOx

passivation layer with ALD SiO2, high mobility SiC device can be realized.

• ALD is promising technique for gate oxide and passivation for SiC power devices.

25


Acknowledgements

• Students and Postdoc: Xiangyu Yang, Minseok Kang, Casey Kirkpatrick, and Kevin Lawless

• NCSU AIF and NNF Staff Members

26


Thank you !

27

ald dielectrics and interface engineering for sic mosfet ...neil/sic_workshop... · b. lee, ncsu,...

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