[AKD7734-A]

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GENERAL DESCRIPTION

The AKD7734-A is an evaluation board for AK7734, which is an audio processor including a stereo ADC, a stereo SRC and an audio DSP. This board is composed of a main board and a sub board. It is possible to control the setting of board via USB port. RCA connector is used for the input and output of analog signal. This board also has digital interface and can achieve the interface with digital audio system via optical connector.

Ordering guide

AKD7734-A --- Evaluation board for AK7734 Control software and USB cable are packed with this.

FUNCTION

Read/Write access to PRAM, CRAM, OFFRAM and registers of AK7734 Compatible with 2 types of digital audio interface

- Optical input (x1) / Optical output (x1) - 10pin header for interface with external data source (x2)

ADC 2ch input (single-end), DAC 8ch output (Note: There is no DAC within AK7734. 8ch DAC AK4359 is equipped.)

USB port for board control

AK4359

AK7734FPGA

(XC95144)

PIC4550

AK4114

Opt In

Opt Out

USB

AOUT 8ch

AIN 2ch

SMUX1 SMUX210 Pin Header

Amp

RegulatorRegulator

GND -12V +12V

3.3V3.3VUSB 3.3V

Regulator

Regulator

5V

(Note) AK4114 has DIR, DIT and X’tal oscillator.

Figure 1. AKD7734-A Block Diagram

AK7734 Evaluation Board Rev.1AKD7734-A

[AKD7734-A]

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Evaluation Board Diagram

Board Diagram

+12V

-12V

AIN-R

AIN-L

DAC4-R

DAC4-L

DAC3-R

DAC3-L

XILINXPIC18F4550

4114

USB

SPDIFOUT

SPDIFIN

AK4359

DAC2-R

DAC2-L

DAC1-R

DAC1-L

7734

AGND

DGND

DVSS TP3

TP5

TP6TP2

SMUXPORT2

1

2

9

10

SMUXPORT1

1

2

9

10

JTAG

1

2

9

10

74HCT54174HCT243

SW1

74HC221A

Color led

SW2

GND

REG1

REG4

HeatSink

HeatSink

REG2

REG3

5532

XTAL1

XTAL2Header5

D1

Figure 2. AKD7734-A Board Diagram

Description

(1) AIN/DAC (RCA-JACK)

AIN: These are analog signal input Jacks. The signals are input to AIN pins. (The white Jack is used for left channel, and the red one is used for right channel.) DAC: These are analog signal output Jacks. The signals are output from AK4359.

(2) AK4114 AK4114 has DIR, DIT and X’tal oscillator. It transports digital data to AK7734 when working in master mode and outputs data from AK7734 when working in slave mode.

(3) SPDIF-IN/ SPDIF-OUT SPDIF-IN: Optical input connector. It supports sampling frequencies from 32kHz to 96kHz for input. It is used as

digital data source for AK7734. SPDIF-OUT: Optical output connector. It outputs the data from whichever among SDOUT1~4.

(4) Power supply

Connect to +12V, GND and -12V. Current of about 250mA is consumed when normal operation. (5) PIC18F4550

USB control chip. It is possible to set up the registers of AK7734, Xilinx, AK4359 and AK4114 from PC via USB port.

(6) SW2

Push type button. It is used to initialize the PICIF4550. When connecting the board to PC, it is required to push down the button for initialization.

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(7) Xilinx

Xilinx used for data path control. It is possible to run a variety of tests by way of controlling the data path via control software.

(8) SW1 The SW1 is used to select clock source between [EXT] and [XTL] to change the clock mode of AK7734. The setting of other jumper pins is according to Table 3 and Table 4.

(9) SMUX port 10 pin header for interface with external data source. Two ports are equipped and available to achieve with other audio system.

Pin I/O Function pin I/O Function 1 I/O MCLK 2 P GND 3 I/O BITCLK 4 P GND 5 I/O LRCLK 6 P GND 7 I SDTI 8 P GND 9 P VDD 10 O SDTO

Table 1. The assignments of the SMUX port

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Evaluation Board Manual

Operation sequence

(1) Set up the power supply lines.

[The jumper pins should be set as following] JP2

7734-DVDD

(Short)

JP1 7734-AVDD

(Short)

JP6P-DVDD

(Short)

JP5PIC-VDD-SEL

DVDD 3.3V 5V Set up the power supply lines.

Name Color Voltage Comment Attention +12V Red +9～+12V Regulator,

Power supply for op-ampThis jack is always needed. Power line

-12V Blue -9～-12V Power supply for op-amp This jack is always needed. Power line

GND Black 0V Ground This jack is always needed. Table 2. Set up of power supply lines

Each supply line should be distributed from the power supply unit. The power of AK7734 and peripheral device is supplied by two regulators equipped on the board convert from 12V to 3.3V.

(2) Set up the evaluation mode, jumper pins and connectors. ( according to the follows ) (3) Connect the board to PC with the USB cable packed.

It is required to push down the button (SW2) to initialize the USB control chip.

(4) Power On

(5) Start the control soft and setup the register. ( according to the follows )

Evaluation Mode

In case of AK7734 evaluation using AK4114, it is necessary to correspond to audio interface format for AK7734 and AK4114. About AK7734’s audio interface format, refer to datasheet of AK7734. About AK4114’s audio interface format, refer to Table 9 in this manual.

Applicable Evaluation Mode

(1) Evaluation mode of ADC using DIT of AK4114 : CKM Master Mode = 0 (Default) (2) Evaluation mode of DSP using DIR/DIT of AK4114 : CKM Slave Mode = 2/3 (3) Evaluation mode of SRC using SMUX port : CKM Slave Mode = 3 – 5, 9 – D (4) Evaluation mode of sound ［tone］ quality using DAC of AK4359

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(1) Evaluation mode of ADC using DIT of AK4114: CKM Master Mode = 0 (Default) SPDIF-OUT is used. SPDIF-IN should be open. Set the clock mode of AK7734 to Master Mode (12.288MHz).

AK7734 supplies MCLK, BICK, and LRCK to AK4114 and AK4114 outputs the data from SDOUT1. [The jumper pins should be set as following]

JP101AK7734 CLKI

CRY-XTI EXT-XTI [Set up SW1] Toggle should be set to “EXT”.

1. Connection of connector For analog single-end input, AIN-L(W)/AIN-R(R) are available. For digital output, optical connector PORT2 (SPDIF-OUT) is available.

2. Set up the Xilinx and AK7734/AK4114 control register via PC. (See the Page.11)

(2) Evaluation mode of DSP using DIR/DIT of AK4114: CKM Slave Mode = 2/3

SPDIF-IN and SPDIF-OUT are used. Set the clock mode of AK7734 to Slave Mode (12.288MHz). AK4114 supplies MCLK, BICK, LRCK and digital data to AK7734. [The jumper pins should be set as following]

JP101AK7734 CLKI

CRY-XTI EXT-XTI [Set up SW1] Toggle should be set to “XTL”.

1. Connection of connector For digital input, optical connector PORT1 (SPDIF-IN) is available. For digital output, optical connector PORT2 (SPDIF-OUT) is available.

2. Set up the FPGA and AK7734 control register via PC. (See the Page.11)

(3) Evaluation mode of SRC using SMUX port: CKM Slave Mode = 3 – 5, 9 – D

PORT1 and PORT2 are used, leave the SPDIF-IN and SPDIF-OUT open.

Set the clock mode of AK7734 to CKM Slave Mode. The necessary clocks for AK7734 are generated by the PLL based on the clock input to BICK.

[The jumper pins should be set as following]

JP101AK7734 CLKI

CRY-XTI EXT-XTI

1. Connection of connector For digital input, SMUX PORT1 (10pin header) is available. (Each Clock should be connected respectively.) For digital output, SMUX PORT2 (10pin header) is available.

2. Set up the FPGA and AK7734 control register via PC. (See the Page.11)

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(4) Evaluation mode of sound ［tone］ quality using DAC of AK4359

AK4359 is used. AK7734 supplies MCLK, BICK, LRCK and digital data to AK4359, which converts digital data to analog signal and output it.

1. Connection of connector

For analog output, RCA3-10 (DAC1-4) is available.

2. Set up the FPGA and AK7734 control register via PC. (See the Page.11)

Board control It is possible to control AKD7734-A via general USB port. Connect the USB port on board to PC with the packed cable. Control software is packed with this board. The software operation sequence is included in the evaluation board manual.

Indication for LED

[LED] U9: When power is supplied, LED is lighted to red. Monitor the PC-RQN clock signal and change green when the board is communicating with PC.

[LED] D1: The status of AK7734’s STO pin is displayed. ‘H’ → Light off; ‘L’ → Light on.

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Setting of Jumper Pins

(Main board)

Jumper Setting (Default) Note

SW1 (AK4114 Clock) “XTL” AK4114 Clock Source “XTL”: Crystal Clock “EXT”: External Clock

JP1 (7734-AVDD) Short AK7734 AVDD JP2 (7734-DVDD) Short AK7734 DVDD JP3 (AGND-GND) Short Short of AGND and DVSS

JP5 (PIC-VDD-SEL) “USB-3.3V”

USB chip power supply “USB-5V”: USB 5V “USB-3.3V”: USB 3.3V “DVDD”: Peripheral DVDD 3.3V

JP6(P-DVDD) Short Peripheral DVDD Table 3. Setting of jumper pins on main board

(Sub board)

Jumper Setting (Default) Note

JP101(Clock) “EXT-XTI” AK7734 Clock Source “CRY-XTI”: Crystal Clock “EXT-XTI”: External Clock

JP102(TESTI2) Short Setup of the test pin of AK7734 Please set it to be shorted.

Table 4. Setting of jumper pins on sub board

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Analog Input Circuit

R810k

RCA2

MR-552LS(W)

TBS

+

C2210uF

+ C1610uF

C210.1uF

R1110k

C2368pF

+C19

22uF(A)

+C20

22uF(A)

RCA1

MR-552LS(R)

TBS

AMP-PW+

AMP-PW-

+

C18

4.7uF(A)

AINL

SILK-SCREENAINL

+

-

U2ANJM5532D

3

21

84

+

-

U2BNJM5532D

5

67

84

+

C17

4.7uF(A)

AINR

SILK-SCREENAINR

C2468pF

R1010k

R910k

C150.1uF

Figure 3. AINL, AINR Input Circuit

For analog single-ended input, RCA1 (AIN-R) / RCA2 (AIN-L) are available. The input range of each channel is 2.00Vpp@3.3V.

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Analog Output Circuit

+

C39

22uF

R2422k

R2522k

DAC1

DAC2

DAC3

DAC4

RCA4

MR-552LS(W)

TBS

RCA5

MR-552LS(W)

TBS

RCA7

MR-552LS(W)

TBS

RCA10

MR-552LS(W)

TBS

R2622k

R2722k

RCA3

MR-552LS(R)

TBS

RCA6

MR-552LS(R)

TBS

RCA8

MR-552LS(R)

TBS

RCA9

MR-552LS(R)

TBS

R2822k

R2922k

R3022k

LOUT1

+

C40

22uF

+

C41

22uF

+

C42

22uF

+

C43

22uF

ROUT1

+

C44

22uF

+

C45

22uF

+

C46

22uF

LOUT2

ROUT2

ROUT3

LOUT3

LOUT4

ROUT4

R2322k

Figure 4. AK4359(DAC) Analog Output Circuit

For analog output, RCA3/4(DAC1), RCA5/6(DAC2), RCA7/8(DAC3) and RCA9/10(DAC4) are available. The analog output circuit supports single-ended mode and the output range is 3.4Vpp@5V.

[AKD7734-A]

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Digital Input Circuit (External DIR:PORT1)

Figure 5. Digital Input Circuit (AK4114)

For digital input SPDIF-IN, optical connector PORT1 is available.

Digital Output Circuit (External DIT:PORT2)

Figure 6. Digital output circuit (AK4114)

For digital output SPDIF-OUT, optical connector PORT2 is available.

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Control Software Manual

Set-up of the evaluation board and control software

(1) Set up the AKD7734-A according to previous term. (2) Connect AKD7734-A to PC with the cable packed Push down the reset button (SW1) to initialize the USB chip.

(3) Insert the CD-ROM labeled “AKD7734-A Evaluation Kit” into the CD-ROM drive.

(4) Access the CD-ROM drive and double-click the icon of “AK7734.exe” to set up the program.

(5) Then please evaluate according to the follows.

Operation flow

Keep the following flow

1. Set up the control program according to the explanation above. 2. Click “Board Init” button to initialize the board. 3. Select the needed dialogue to evaluate by changing the setting. If the USB cable is removed when control software is used, please close the software and set up it again when operation is needed again.

Figure 7. The image of control software

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Control software is possible to execute program downloading, to set up the registers, to set up the FPGA and to process script file. They can be selected by the tab items above. The buttons of control signals which are frequently used and the initialization buttons are placed outside the tab dialogue. [INIT_RESET]: Initial Reset. It is used to initialize the AK7734. [S_RESET]: System Reset. DSP/ADC/DAC will be set to reset mode but the register will not be initialized. [ADC]: ADC Reset. [SRC]: SRC Reset. [CK]: Clock Reset. Clock Reset is required when changing the clock mode or the frequency of input clock

without initial reset. The register will not be initialized. [I2CSEL] Selector for 3-wire serial control mode or I2C control mode. I2C control mode is selected when the

button is pushed down and 3-wire serial mode is selected when button is released. [Board Init]: The setting of registers of AK7734, FPGA and AK4114 is written to board together. [READ]: Read back CONT register or TEST register decided by [Read Select] button and show the result on

register column.

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(1) Download

Figure 8. [Download] Dialogue

File of Source column, Program column, CRAM column or OFFSET column can be selected by clicking the [refer] button of each column or by way of dropping or tracking files from desktop. CRAM file or OFFSET file can be selected and be written to CRAM or OFF-RAM by clicking the [refer] button of CRAM write@operation column or OFF-RAM write@operation column when system is running. The data will be written to specific address of CRAM or OFF-RAM when the [write] button at right side is clicked. [Assemble]: Compile the source file and the output file will be selected to the download file automatically. [Write]: Download the program to AK7734. [Assemble Write]: Compile the source file and then download the file to AK7734. [PRAM read]: Read the data of PRAM to temporary file. [CRAM read]: Read the data of CRAM to temporary file. [Offset read]: Read the data of OFF-RAM to temporary file. [CRAM SAVE]: Read the data of CRAM and save to file. [Offset SAVE]: Read the data of OFF-RAM and save to file. [MICR1]: Read the data of register MICR1 when program is running and show the result to dialogue. [MICR2]: Read the data of register MICR2 when program is running and show the result to dialogue. [MICR3]: Read the data of register MICR3 when program is running and show the result to dialogue. [MICR4]: Read the data of register MICR4 when program is running and show the result to dialogue. [JX]: JX code setting column.

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(2) Register Set up

Figure 9. [REG1] Dialogue

Tab Dialogues of REG1/REG2/REG3 are used to regulate the registers’ setting. (It is prohibited to process test and reserved items.) As the checkbox is clicked, the data is written to the register after system reset. The reference pages of registers in datasheet are as following:

Register Reference page Register Reference page CONT00 27 CONT06 33 CONT01 28 CONT07 34 CONT02 29 CONT08 35 CONT03 30 CONT09 36 CONT04 31 CONT0A 37 CONT05 32 CONT10-11 38

Table 5. Reference page of registers

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(3) FPGA Set up

Figure 10. [FPGA1] Dialogue

The FPGA1/FPGA2 dialogues are used to regulate the data path of AK7734 and the setting of AK4114 via FPGA. FPGA Set up (It is prohibited to process test and reserved items.)

ADDRESS = 0 (A [1:0] = 00) Default: bold type Bit Function Description D[13:12] TX-DAT Output data source for AK4114

00 : SDOUT1 01 : SDOUT2 10 : SDOUT3 11 : SDOUT4

D[11:10] SDIN1 Input data source to SDIN1 pin of AK7734 00 : AK4114 IN (RX_DAT) 01 : SMUX1_DAT1 10 : SMUX2_DAT1 11 : Low

D[9:7] SDIN2/JX0 Input data source to SDIN2/JX0 pin of AK7734 000 : AK4114 IN (RX_DAT) 001 : SMUX1_DAT1 010 : SMUX2_DAT1 011 : Low 100 : Low 101 : High 110 : Low 111 : Low

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D[6:4] SDIN3/JX1 Input data source to SDIN3/JX1 pin of AK7734 000 : AK4114 IN (RX_DAT) 001 : SMUX1_DAT1 010 : SMUX2_DAT1 011 : Low 100 : Low 101 : High 110 : Low 111 : Low

D[3:1] SDIN4/JX2 Input data source to SDIN4/JX2 pin of AK7734 000 : AK4114 IN (RX_DAT) 001 : SMUX1_DAT1 010 : SMUX2_DAT1 011 : Low 100 : Low 101 : High 110 : Low 111 : Low

D[0] DAC-PDN Power Switch of AK4359 0 : Low 1 : High

Table 6. FPGA Set up table1

ADDRESS = 1 (A [1:0] = 01) Bit Function Description D[15:12] CKM[3:0] Clock mode of AK7734

Mode-0: XTI - MASTER 12.288MHz Mode-1: XTI - MASTER 18.432MHz Mode-2: XTI - SLAVE 12.288MHz Mode-3: BICK1 - SLAVE 64fs ( fs = 48kHz ) Mode-4: BICK1 - SLAVE 32fs ( fs = 8kHz ) Mode-5: BICK1 - SLAVE 64fs ( fs = 8kHz ) Mode-6: TEST N/A Mode-7: TEST N/A Mode-8: TEST N/A Mode-9: BICK1 – SLAVE 48fs ( fs = 48kHz ) Mode-A: BICK1 – SLAVE 48fs ( fs = 8kHz ) Mode-B: BICK2 – SLAVE 64fs ( fs = 48kHz ) Mode-C: BICK2 – SLAVE 32fs ( fs = 8kHz ) Mode-D: BICK2 – SLAVE 64fs ( fs = 8kHz ) Mode-E: TEST N/A Mode-F: TEST N/A

D[11:10] BICK1/LRCK1 Input switch of AK7734’s BICK1/LRCK1 00 : AK4114 BICK/LRCK 01 : SMUX1_BICK/LRCK 10 : SMUX2_BICK/LRCK 11 : Low

D[9:8] BICK2/LRCK2 Input switch of AK7734’s BICK2/LRCK2 00 : AK4114 BICK/LRCK 01 : SMUX1_BICK/LRCK 10 : SMUX2_BICK/LRCK 11 : Low

D[7:6] EXT-XTI Input switch of AK7734’s XTI 00 : AK4114 RX_CLK 01 : SMUX1_MCLK 10 : SMUX2_MCLK 11 : Low

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D[5] TRXPDN Power Switch of AK4114 0 : Low 1 : High

D[4] TRX-BICK/LRCK Switch of I/O direction of the AK4114’s BICK/LRCK 0 : BIT, LR input 1 : BITCLKO/LRCLKO output

D[3] SMUX2 In/Out Switch of I/O direction of the SMUX2’s BICK/LRCK 0 : BIT, LR input 1 : BITCLKO/LRCLKO output (7734)

D[2] SMUX1 In/Out Switch of I/O direction of the SMUX1’s BICK/LRCK 0 : BIT, LR input 1 : BITCLKO/LRCLKO output (7734)

Table 7. FPGA Set up table2 ADDRESS = 2 ( A[1:0] = 10 ) Bit Function Description D[15:14] SMUX2_DAT2 Output data source for DAT2 pin of port SMUX2

00 : SDOUT1 01 : SDOUT2 10 : SDOUT3 11 : SDOUT4

D[13:12] SMUX1_DAT2 Output data source for DAT2 pin of port SMUX1 00 : SDOUT1 01 : SDOUT2 10 : SDOUT3 11 : SDOUT4

D[11:10] TX-CLK Input switch of AK4114’s CLK 00 : AK7734 CLKO 01 : SMUX1_MCLK 10 : SMUX2_MCLK 11 : Low

D[9] SETSRC Low/High setup of AK7734’s SETSRC pin 0 : Low 1 : High

D[8:7] CAD[1:0] Set up of AK7734’s CAD1-0 pins 00 : Low, Low 01 : Low, High 10 : High, Low 11 : High, High

D[6:5] SMUX2_MCLK Input switch of SMUX2’s MCLK 01 : AK7734-CLKO 10 : AK4114_RX_CLK 11 : SMUX1_MCLK

D[4:3] SMUX1_MCLK Input switch of SMUX1’s MCLK 01 : AK7734-CLKO 10 : AK4114_RX_CLK 11 : SMUX2_MCLK

D[2:0] Reserved Table 8. FPGA Set up table3

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Function Description MCLK Frequency of main clock output from AK4114

00: 265fs 01: 256fs 10: 512fs 11: 128fs

CM Master clock operation mode of AK4114 00: CM = 00 01: CM = 01 10: CM = 10 11: CM = 11

DIF Format setup of AK4114 I/O 000: 16bit Right( O ) 001: 18bit Right( O ) 010: 20bit Right( O ) 011: 24bit Right( O ) 100: 24bit Left( O ) 101: 24bit I2S( O ) 110: 24bit Left( I ) 111: 24bit I2S( I )

Table 9. AK4114 Set up

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(4) Script

Figure 11. [SCRIPT] Dialogue

As the script file is selected, it is executed directly. If [Repeat] button is clicked, the selected script file will be executed once again. The script commands are listed as follow.

Command Description [SCRIPT] Header of script file. The script file will be compiled to error without this header. ;Comment The content after semicolon is ignored as comment. W,<address>,<data> W,0xC0,0x00

Write data to register. Both address and data must be BYTE(8bit).

WL,<command>,<address>,<data>,… WL,0x82,0x0022,0x4000,0x4000,0x4000,

Write data continuously. It can be used when CRAM is running. The command must be BYTE(8bit) and the data below must be WORD(16bit).

D,<address>,<data> Write data to AK4114. X,<address>,<data> Write data to the register of FPGA. P,<message> Show message and pause the processing of script. RI: H / RI:L RA:H / RA:L RD:H / RD:L

Init reset. ADC reset. DSP reset.

R2:H / R2:L Select for I2C bus mode T,<wait> T,50mS

Wait some milliseconds. When actual operation, it is possible to wait longer than this.

LP:<filename> Download program file to DSP. LC:<filename> Download CRAM file to DSP. LO:<filename> Download OFRAM file to DSP.

Table 10. Script Command

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Measurement Results [Measurement condition]

・ Measurement unit : Audio Precision, System two Cascade ・ MCKI : 12.288MHz ・ BICK : 64fs ・ fs : 8kHz/48kHz ・ Bit : 24bit ・ Measurement Mode : Master Mode, CKM Mode 0 ・ Power Supply : +12V, -12V, GND ・ Input Frequency : 1kHz ・ Measurement Frequency : 20 ~ 20kHz ・ Temperature : Room

[Measurement Results]

1. ADC BW=20Hz～4kHz@fs=8kHz

Result Unit Lch Rch ADC: AIN => ADC S/(N+D) (-1dBFS) 92.6 92.6 dB DR (-60dBFS, A-Weighted) 97.6 97.6 dB S/N (A-weighted) 97.7 97.7 dB

2. ADC BW=20Hz～20kHz@fs=48kHz

Result Unit Lch Rch ADC: AIN => ADC S/(N+D) (-1dBFS) 83.6 83.6 dB DR (-60dBFS, A-Weighted) 97.2 97.2 dB S/N (A-weighted) 97.3 97.3 dB

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[Plot Data] 1. FFT Input -1dB (fs=8kHz)

Figure 1. FFT ( 1kHz, -1dBFS )

2. FFT Input -60dB (fs=8kHz)

Figure 2. FFT ( 1kHz, -60dBFS )

AK7734 AIN=>ADC=>SDTO FFTfs=8kHz, fin=1kHz,-60dB

20 4k50 100 200 500 1k 2kHz

-140

+0

-120

-100

-80

-60

-40

-20

dBFS

AK7734 AIN=>ADC=>SDTO FFTfs=8kHz, fin=1kHz,-1dB

20 4k50 100 200 500 1k 2kHz

-140

+0

-120

-100

-80

-60

-40

-20

dBFS

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3. FFT No Input (fs=8kHz)

Figure 3. FFT ( No Input )

4. THD+N vs. Input Level (fs=8kHz)

Figure 4. THD+N vs. Input Level

AK7734 AIN=>ADC=>SDTO THD+N vs. Input Levelfs=8kHz, fin=1kHz

-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10dBr

-100

-60

-95

-90

-85

-80

-75

-70

-65

dBFS

AK7734 AIN=>ADC=>SDTO FFTfs=8kHz, No Signal

20 4k50 100 200 500 1k 2kHz

-140

+0

-120

-100

-80

-60

-40

-20

dBFS

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5. THD+N vs. Input Frequency (fs=8kHz)

Figure 5. THD+N vs. Input Frequency

6. Linearity (fs=8kHz)

Figure 6. Linearity

AK7734 AIN=>ADC=>SDTO Linearityfs=8kHz, fin=1kHz

-100 +0-80 -60 -40 -20dBr

-110

+0

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBFS

AK7734 AIN=>ADC=>SDTO THD+N vs. Input Freqfs=8kHz, fin=-1dB

20 4k50 100 200 500 1k 2kHz

-100

-60

-95

-90

-85

-80

-75

-70

-65

dBFS

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7. Frequency Response (fs=8kHz)

Figure 7. Frequency Response

8. Crosstalk (fs=8kHz)

Figure 8. Crosstalk

AK7734 AIN=>ADC=>SDTO Crosstalkfs=8kHz, fin=1kHz,-1dB

20 3k50 100 200 500 1k 2kHz

-140

-60

-130

-120

-110

-100

-90

-80

-70

dB

T TTTTT T T T TT TTTTT T T T TTTT TTTTTTT T T

AK7734 AIN=>ADC=>SDTO FrequencyResponsefs=8kHz, fin=-1dB

20 3k50 100 200 500 1k 2kHz

-2

+0

-1.8

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

dBFS

[AKD7734-A]

<KM094003> 2011/07 - 25 -

9. FFT Input -1dB (fs=48kHz)

Figure 9. FFT ( 1kHz, -1dBFS )

10. FFT Input -60dB (fs=48kHz)

Figure 10. FFT ( 1kHz, -60dBFS )

AK7734 AIN=>ADC=>SDTO FFTfs=48kHz, fin=1kHz,-60dB

20 20k50 100 200 500 1k 2k 5k 10kHz

-140

+0

-120

-100

-80

-60

-40

-20

dBFS

AK7734 AIN=>ADC=>SDTO FFTfs=48kHz, fin=1kHz,-1dB

20 20k50 100 200 500 1k 2k 5k 10kHz

-140

+0

-120

-100

-80

-60

-40

-20

dBFS

[AKD7734-A]

<KM094003> 2011/07 - 26 -

11. FFT No Input (fs=48kHz)

Figure 11. FFT ( No Input )

12. THD+N vs. Input Level (fs=48kHz)

Figure 12. THD+N vs. Input Level

AK7734 AIN=>ADC=>SDTO THD+N vs. Input Levelfs=48kHz, fin=1kHz

-100 +0-90 -80 -70 -60 -50 -40 -30 -20 -10dBr

-100

-70

-97.5

-95

-92.5

-90

-87.5

-85

-82.5

-80

-77.5

-75

-72.5

dBFS

AK7734 AIN=>ADC=>SDTO FFTfs=48kHz, No Signal

20 20k50 100 200 500 1k 2k 5k 10kHz

-140

+0

-120

-100

-80

-60

-40

-20

dBFS

[AKD7734-A]

<KM094003> 2011/07 - 27 -

13. THD+N vs. Input Frequency (fs=48kHz)

Figure 13. THD+N vs. Input Frequency

14. Linearity (fs=48kHz)

Figure 14. Linearity

AK7734 AIN=>ADC=>SDTO Linearityfs=48kHz, fin=1kHz

-100 +0-80 -60 -40 -20dBr

-110

+0

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBFS

AK7734 AIN=>ADC=>SDTO THD+N vs. Input Freqfs=48kHz, fin=-1dB

20 20k50 100 200 500 1k 2k 5k 10kHz

-100

-60

-95

-90

-85

-80

-75

-70

-65

dBFS

[AKD7734-A]

<KM094003> 2011/07 - 28 -

15. Frequency Response (fs=48kHz)

Figure 15. Frequency Response

16. Crosstalk (fs=48kHz)

Figure 16. Crosstalk

AK7734 AIN=>ADC=>SDTO Crosstalkfs=48kHz, fin=1kHz,-1dB

20 20k50 100 200 500 1k 2k 5k 10kHz

-140

-60

-130

-120

-110

-100

-90

-80

-70

dB

TTTT TTTTT TTTTT T

AK7734 AIN=>ADC=>SDTO Frequency Responsefs=48kHz, fin=-1dB

20 20k50 100 200 500 1k 2k 5k 10kHz

-2

+0

-1.8

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

dBFS

[AKD7734-A]

<KM094003> 2011/07 - 29 -

REVISION HISTORY

IMPORTANT NOTICE

These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products.

AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein.

Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.

AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.

It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.

Date (yy/mm/dd)

Manual Revision

Board Revision

Reason Page Contents

08/09/08 KM094001 0 First edition 10/02/01 KM094002 1 Device Rev. changed 1 AK7734: Rev.A → Rev.B 11/07/06 KM094003 1 Error Correction 6 The logic of the lighting LED_D1 was reversed:

‘H’ → Light off; ‘L’ → Light on.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CR

Y-X

TI

EX

T-X

TI

Title

Size Document Number Rev

Date: Sheet ofAK7734 0

AKD7734-SUB-48LQFPA3

1 1Friday, May 09, 2008

Title

Size Document Number Rev

Date: Sheet ofAK7734 0

AKD7734-SUB-48LQFPA3

1 1Friday, May 09, 2008

Title

Size Document Number Rev

Date: Sheet ofAK7734 0

AKD7734-SUB-48LQFPA3

1 1Friday, May 09, 2008

AGND

DGND

All test pins don't need to be mountedR12651R12651

R13151R13151

R12551R12551

TP107

SDIN3

TP107

SDIN3

1

C114

22pF(DIP)

C114

22pF(DIP)

C113

22pF(DIP)

C113

22pF(DIP)

TP113SDOUT3

TP113SDOUT3

1

R12351R12351

R101 51R101 51

TP110

DVDD1

TP110

DVDD1

1

R12851R12851

R113 51R113 51

TP117RSTN

TP117RSTN

1

+C125

100uF

+C125

100uF

C120

(open)

C120

(open)

R13051R13051

R120 51R120 51

R10551R10551

+C105

10uF

+C105

10uF

+C121

100uF

+C121

100uF

TP130SOTP130SO

1

CN102

48pin_2

CN102

48pin_2

13

14

15

16

17

18

19

20

21

22

23

24

TP129LRCKI2TP129LRCKI2

1

+C123

100uF

+C123

100uF

C1150.1uFC1150.1uF

R111 51R111 51

R12751R12751

Y10112.288MHzY10112.288MHz

TP120CLKO

TP120CLKO

1

R116 51R116 51

TP102VCOMTP102VCOM

1

R10851R10851

TP132SRCLFLT

TP132SRCLFLT

1

+

C112

10uF

+

C112

10uF

TP127SDIN4TP127SDIN4

1

R119 51R119 51

TP105

SDIN1

TP105

SDIN1

1

R11451

R11451

C1080.1uFC1080.1uF

CN104

48pin_4

CN104

48pin_4

37

38

39

40

41

42

43

44

45

46

47

48

TP125SI

TP125SI

1

R10951R10951

TP111DVDD4TP111DVDD4

1

TP124SDATP124SDA

1

TP112SDOUT4

TP112SDOUT4

1

TP131STOTP131STO

1

+C10910uF

+C10910uF

R117 51R117 51

TP128BICKI2TP128BICKI2

1

TP126RQNTP126RQN

1

+

C124

100uF

+

C124

100uF

TP123SCKTP123SCK

1

R10451R10451

R112 51R112 51

R118 51R118 51

C118

0.1uF

C118

0.1uF

TP114SDOUT2

TP114SDOUT2

1C1040.1uFC1040.1uF

TP106

SDIN2

TP106

SDIN2

1

R103 51R103 51

R121 51R121 51

CN10348pin_3CN103

48pin_3

252627282930313233343536

R12451R12451

TP122DVDD3TP122DVDD3

1

R115 0R115 0

R110 51R110 51

JP101XTI-SELJP101XTI-SEL

TP103 AINLTP103 AINL1

CN10148pin_1CN10148pin_1

1 2 3 4 5 6 7 8 9 10 11 12

R12251R12251

C10112nFC10112nF

+ C11610uF

+ C11610uF

JP102TESTI2JP102TESTI2

TP119BICKO

TP119BICKO

1

C111

0.1uF

C111

0.1uF

TP104 AINRTP104 AINR1

R10651R10651

C1020.1uFC1020.1uF

+C122100uF

+C122100uF

TP121AVDRV

TP121AVDRV

1

C1101uF(DIP)C1101uF(DIP)

TP118LRCKO

TP118LRCKO

1

TP108

BICKI1

TP108

BICKI1

1

+ C1032.2uF

+ C1032.2uF

C117

1uF(DIP)

C117

1uF(DIP)

R132 51R132 51

TP109

LRCKI1

TP109

LRCKI1

1

R12951R12951

+C119

10uF

+C119

10uF

TP115SDOUT1

TP115SDOUT1

1

R10751R10751

R10251R10251

U100

AK7734

U100

AK7734TE

STI

11

CK

M2

2

CK

M1

3

SD

IN1

4

JX0/

SD

IN2

5

JX1/

SD

IN3

6

BIT

CLK

I17

LRC

LKI1

8

DV

DD

9

VS

S1

10

XTI

11

XTO

12

SDOUT4 13

SDOUT3 14

SDOUT2 15

SDOUT1 16

VSS2 17

DVDD 18

I2CSEL 19

INITRSTN 20

CKM0 21

LRCLKO 22

BITCLKO 23

CLKO 24

LFLT48

VSS547

VCOM46

AVDD45

AINL44

AINR43

TESTI242

SETSRC41

CKM340

DVDD39

VSS438

SRCLFLT37

AV

DR

V36

VS

S3

35

DV

DD

34

SC

LK/S

CL

33

SD

A32

SI/C

AD

031

RQ

N/C

AD

130

JX2/

SD

IN4

29

BIT

CLK

I228

LRC

LKI2

27

SO

/RD

Y26

STO

25

TP116DVDD2

TP116DVDD2

1

TP101 AVDDTP101 AVDD1

- 30 -

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AVDD

DVDD

TESTI1 CKM2 CKM1 SDIN1 SDIN2 SDIN3 BICKI1 LRCKI1 7734-DVDD EXT-XTI

AINL

AINR

TESTI2

SETSRC

CKM3

7734-DVDD

SDOUT4

SDOUT3

SDOUT2

SDOUT1

7734-DVDD

I2CSEL

RSTN

LRCKO

BICKO

CLKO

CKM0

STOSOLRCKI2BICKI2SDIN4RQNSIPC-SDASCLK7734-DVDD

7734-DVDD

Title

Size Document Number Rev

Date: Sheet ofAK7734 0

AKD7734-AA3

1 1Friday, May 09, 2008

Title

Size Document Number Rev

Date: Sheet ofAK7734 0

AKD7734-AA3

1 1Friday, May 09, 2008

Title

Size Document Number Rev

Date: Sheet ofAK7734 0

AKD7734-AA3

1 1Friday, May 09, 2008

AGND

DGND

Show directionusing the arrow

Show directionusing the arrow

CN348pin_3

CN348pin_3

252627282930313233343536

JP1

->7734-AVDD

JP1

->7734-AVDD

CN2

48pin_2

CN2

48pin_2

13

14

15

16

17

18

19

20

21

22

23

24

CN4

48pin_4

CN4

48pin_4

37

38

39

40

41

42

43

44

45

46

47

48

CN148pin_1CN148pin_1

1 2 3 4 5 6 7 8 9 10 11 12

JP2

->7734-DVDD

JP2

->7734-DVDD

- 31 -

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PC-SI

PC-SCLK

PC-CS4N

AMP-PW+DVDD-DAC VDD-DAC

DVDD-DAC

DVDD-DAC

VDD-DAC

DAC-PDN

SDOUT2SDOUT3SDOUT4

CLKO

LRCKO

BICKOSDOUT1

Title

Size Document Number Rev

Date: Sheet ofDAC 0

AKD7734-AA3

1 1Thursday, May 01, 2008

Title

Size Document Number Rev

Date: Sheet ofDAC 0

AKD7734-AA3

1 1Thursday, May 01, 2008

Title

Size Document Number Rev

Date: Sheet ofDAC 0

AKD7734-AA3

1 1Thursday, May 01, 2008

DAC1

DAC2

DAC3

DAC4

SILK-SCREENAGND

R2422kR2422k

RCA4

MR-552LS(W)

RCA4

MR-552LS(W)

TBS

U3

AK4359

U3

AK4359

MCLK1

BICK2

SDTI13

LRCK4

RSTB5

SMUTE/CSN/CAD06

ACKS/CCLK/SDL7

DIF0/CDTI/SDA8

SDTI29

SDTI310

SDTI411

DIF112

DEM013

DVDD14

DVSS15

DZF1 30

DZF2 29

AVDD 28

AVSS 27

VCOM 26

LOUT1 25

ROUT1 24

P/S 23

LOUT2 22

ROUT2 21

LOUT3 20

ROUT3 19

LOUT4 18

ROUT4 17

DEM/I2C 16

R2822kR2822k

RCA10

MR-552LS(W)

RCA10

MR-552LS(W)

TBS

+ C2810uF

+ C2810uF

C270.1uFC270.1uF

REG4 LM1117-5VREG4 LM1117-5V

OUT2

GN

D3

IN 1

U4

74HCT243

U4

74HCT243

GAB1

NC2

1A3

2A4

3A5

4A6

GND7

VCC 14

GBA 13

NC 12

1B 11

2B 10

3B 09

4B 08

R15 51R15 51

R19 51R19 51

+

C39

22uF

+

C39

22uF

C350.1uFC350.1uF

RCA6

MR-552LS(R)

RCA6

MR-552LS(R)

TBS

+

C3310uF

+

C3310uF

R3022kR3022k

R22 51R22 51

+ C2910uF

+ C2910uF

C250.1uFC250.1uF

+ C3810uF

+ C3810uF

R16 51R16 51

R20 51R20 51

C340.1uFC340.1uF RCA5

MR-552LS(W)

RCA5

MR-552LS(W)

TBS

U5

74HCT541

U5

74HCT541

A12A23A34A45A56A67A78A89

G11G219

Y1 18Y2 17Y3 16Y4 15Y5 14Y6 13Y7 12Y8 11

VCC 20GND 10

R2322kR2322k

R2522kR2522k

R2722kR2722k

C260.1uFC260.1uF

+ C3010uF

+ C3010uF

RCA8

MR-552LS(R)

RCA8

MR-552LS(R)

TBS

R21 51R21 51

R2922kR2922k

R31 10R31 10

+ C3710uF

+ C3710uF

R12 51R12 51

+

C40

22uF

+

C40

22uF

R17 51R17 51

+

C41

22uF

+

C41

22uF

+

C42

22uF

+

C42

22uF

+

C43

22uF

+

C43

22uF

+

C44

22uF

+

C44

22uF

+

C45

22uF

+

C45

22uF

+

C46

22uF

+

C46

22uF

RCA7

MR-552LS(W)

RCA7

MR-552LS(W)

TBS

+ C3110uF

+ C3110uF

TP2TP(BLACK)TP2TP(BLACK)

1

R13 51R13 51

RCA9

MR-552LS(R)

RCA9

MR-552LS(R)

TBS

C320.1uFC320.1uF

RCA3

MR-552LS(R)

RCA3

MR-552LS(R)

TBS

JP3 GNDJP3 GND

R18 51R18 51

C360.1uFC360.1uF

R2622kR2622k

R14 51R14 51

- 32 -

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DIF-RX

DIF-TX

EXT

XTL

TRX-BICK

TRX-LRCK

TX-CLK

RX-CLK2TX-DAT

RX-DAT

RX-CLK

PC-SCLKPC-SI

PC-CS3N

TRX-PDN

DVDD-3.3V

DVDD-3.3V

DVDD-3.3VDVDD-3.3V

DVDD-3.3V

DVDD-3.3V

Title

Size Document Number Rev

Date: Sheet ofAK4114 0

AKD7734-AA3

2 8Friday, May 02, 2008

Title

Size Document Number Rev

Date: Sheet ofAK4114 0

AKD7734-AA3

2 8Friday, May 02, 2008

Title

Size Document Number Rev

Date: Sheet ofAK4114 0

AKD7734-AA3

2 8Friday, May 02, 2008

DVSS

SILK-SCREENSPDIN-IN

SILK-SCREENDVSS

SPDIF-IN

SPDI/F Optical in

SILK-SCREENSPDIN-OUT

SPDIF-OUT

SPDI/F Optical out

TP1TP(BLACK)TP1TP(BLACK)

1

C100.1uFC100.1uF

XTAL1

12.288MHz

XTAL1

12.288MHz

+ C14100uF/16V(A)

+ C14100uF/16V(A)

C722pF C722pF

L1

10uH

L1

10uH

R6 100R6 100

SW1SW1

+

C12 10uF

+

C12 10uF

R1

18k

R1

18k

C8 0.1uFC8 0.1uF

+

C1310uF

+

C1310uF

R7 100R7 100

C622pF C622pF

R5 100R5 100

R2 470R2 470

L2

10uH

L2

10uH

C90.1uF C90.1uF

R3 100R3 100

+

C1

10uF

+

C1

10uF

+ C1110uF

+ C1110uF

C3

0.1uF

C3

0.1uF

PORT2

TOTX141

PORT2

TOTX141GND 1VCC 2IN 3

+ C510uF

+ C510uFC4

0.1uFC40.1uF

C2

0.1uF

C2

0.1uF

PORT1

TORX141

PORT1

TORX141OUT 1

VCC 3GND 2

R4 100R4 100

AK4114

U1

AK4114

AK4114

U1

AK4114

RX41NC12RX53TEST24RX65NC36RX77IIC8P/SN9XTL010XTL111VIN12

TVD

D13

NC

414

TX0

15TX

116

BO

UT

17C

OU

T18

UO

UT

19V

OU

T20

DV

DD

21D

VS

S22

MC

KO

123

LRC

K24

SDTO 25BICK 26MCKO2 27DAUX 28XTO 29XTI 30PDN 31CDTO 32CDTI 33CCLK 34CSN 35INT0 36

INT1

37A

VD

D38

R39

VC

OM

40A

VS

S41

RX

042

NC

543

RX

144

TES

T145

RX

246

NC

647

RX

348

- 33 -

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AMP-PW+

AMP-PW-

AINRAINL

Title

Size Document Number Rev

Date: Sheet ofANALOG-IN 0

AKD7734-AA3

4 8Wednesday, May 21, 2008

Title

Size Document Number Rev

Date: Sheet ofANALOG-IN 0

AKD7734-AA3

4 8Wednesday, May 21, 2008

Title

Size Document Number Rev

Date: Sheet ofANALOG-IN 0

AKD7734-AA3

4 8Wednesday, May 21, 2008

SILK-SCREENAINR

SILK-SCREENAINL

AREA : SHORTEST WIRING

R910kR910k

+ C1610uF

+ C1610uF

RCA1

MR-552LS(R)

RCA1

MR-552LS(R)

TBS

R1010kR1010k

+

-

U2ANJM5532D

+

-

U2ANJM5532D

3

21

84

C2468pFC2468pF

+C19

22uF(A)

+C19

22uF(A) C2368pFC2368pF

+C20

22uF(A)

+C20

22uF(A)

+

C17

4.7uF(A)

+

C17

4.7uF(A)

+

-

U2BNJM5532D

+

-

U2BNJM5532D

5

67

84

R1110kR1110k

C210.1uF

C210.1uF

R810kR810k

+

C2210uF

+

C2210uF

+

C18

4.7uF(A)

+

C18

4.7uF(A)

C150.1uF

C150.1uF

RCA2

MR-552LS(W)

RCA2

MR-552LS(W)

TBS

- 34 -

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XTO

GND

USB-VDD

USB-RST

XTI

VUSB

D+D-

LED-IND

PC-CS3NPC-INITRSTNPC-CS4NPC-I2CSELPC-SCLKPC-SIPC-RQNPC-CS2N

PC-SCLPC-SO

DVDD-3.3VDVDD-3.3V

DVDD-3.3V

DVDD-3.3V

DVDD-3.3V

PC-SDA

Title

Size Document Number Rev

Date: Sheet ofPC I/F 0

AKD7734-AA3

6 8Friday, May 02, 2008

Title

Size Document Number Rev

Date: Sheet ofPC I/F 0

AKD7734-AA3

6 8Friday, May 02, 2008

Title

Size Document Number Rev

Date: Sheet ofPC I/F 0

AKD7734-AA3

6 8Friday, May 02, 2008

SILK-SCREENDVSS

SILK-SCREEN1: VDD2: MCLR3: PGD4: PGC5: GND

SILK-SCREEN1: USB-5V3: USB-3.3V5: DVDD

default 3-4 pin short

Up :ReleaseDown :Push Down

+

C6110uF

+

C6110uF

C52 22pFC52 22pF

+ C5833uF(A)

+ C5833uF(A)

R40 22R40 22

XTAL220MHzXTAL220MHz

U9

BICOLOR LED

U9

BICOLOR LED

GREEN1

RED3 COM 2

C600.1uFC600.1uF

C54

0.1uF

C54

0.1uF

R36 10kR36 10k

C51 22pFC51 22pF

REG1LM1117-3.3VREG1LM1117-3.3V

OUT 2

GN

D3

IN1

R50100kR50100k

JP4

HEADER 5

JP4

HEADER 5

12345

TP3TP(BLACK)TP3TP(BLACK)

1

SW2 APE 1FSW2 APE 1F

R3310kR3310k

C53

0.1uF

C53

0.1uF

+C59

100uF/16V(A)+

C59

100uF/16V(A)

R37 100R37 100

R39 22R39 22

+

C4910uF

+

C4910uF

R3410kR3410k

R35 100R35 100

U8A

74HC221

U8A

74HC221

CEXT14

REXT/CEXT15

A1B2CLR3

Q 13

Q 4

VCC16

GND8

C480.1uFC480.1uF

+ C56

10uF

+ C56

10uF

+ C55

10uF

+ C55

10uF

C500.1uFC500.1uF

R38 100R38 100

JP5PIC-VDD-SEL

JP5PIC-VDD-SEL

12

34

56

C470.1uFC470.1uF

U8B

74HC221

U8B

74HC221

CEXT6

REXT/CEXT7

A9B10CLR11

Q 5

Q 12

VCC16

GND8

U7

USB(B type)

U7

USB(B type)

VUSB1D-2D+3GND4

R32 10kR32 10k

PIC18F4550TQFP 44-PIN

U6

PIC18F4550

PIC18F4550TQFP 44-PIN

U6

PIC18F4550

RC7/RX/DT/SDO 1

RD4/SPP4 2RD5/SPP5/P1B 3RD6/SPP6/P1C 4RD7/SPP7/P1D 5

VS

S0

6

VD

D0

7

RB0/AN12/INT0/FLT0/SDI/SDA 8RB1/AN10/INT1/SCK/SCL 9RB2/AN8/INT2/VMO 10RB3/AN9/CPP2/VPO 11NC/ICCK/ICPGC12NC/ICDT/ICPGD13 RB4/AN11/KBI0/CSSPP 14RB5/KBI1/PGM 15RB6/KBI2/PGC 16RB7/KBI3/PGD 17MCLR_N/Vpp/RE318

RA0/AN019RA1/AN120RA2/AN2/Vref-/CVref21RA3/AN3/Vref+22RA4/T0CKI/C1OUT/RCV23RA5/AN4/SS_N/HLVDIN/C2OUT24

RE0/AN5/CK1SPP25RE1/AN6/CK2SPP26RE2/AN7/OESPP27

VD

D1

28

VS

S1

29

OSC1/CLKI30OSC2/CLKO/RA631

RC0/T1OSO/T13CKI 32

NC/ICRST_N/ICVpp33NC/ICPORTS34

RC1/T1OSI/CCP2/UOE_N 35RC2/CCP1/P1A 36

VUSB37

RD0/SPP0 38RD1/SPP1 39RD2/SPP2 40RD3/SPP3 41

RC4/D-/VM 42RC5/D+/VP 43RC6/TX/CK 44

C57 470nFC57 470nF

- 35 -

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AMP-PW+

AMP-PW-

AVDDDVDD

DVDD-3.3V

Title

Size Document Number Rev

Date: Sheet ofPOWER 0

AKD7734-AA3

7 8Wednesday, April 30, 2008

Title

Size Document Number Rev

Date: Sheet ofPOWER 0

AKD7734-AA3

7 8Wednesday, April 30, 2008

Title

Size Document Number Rev

Date: Sheet ofPOWER 0

AKD7734-AA3

7 8Wednesday, April 30, 2008

RED(+12V)

BLACK(GND)

BLUE(-12V)

default short

SILK-SCREENP-DVDD2 PIN: [->]

SILK-SCREENCHIP-DGND

SILK-SCREENDVSS

SILK-SCREENAGND

C650.1uFC650.1uF

+ C6610uF

+ C6610uF

TM2

TJ-563

TM2

TJ-563

i1

+ C7310uF

+ C7310uF

TP5TP(BLACK)TP5TP(BLACK)

1

+ C69100uF/16V(A)

+ C69100uF/16V(A)

REG2 LM1084-3.3VREG2 LM1084-3.3V

OUT2

GN

D3

IN 1

C710.1uFC710.1uF

+ C6710uF

+ C6710uF

TM3

TJ-563

TM3

TJ-563

i1

REG3 LM1084-3.3VREG3 LM1084-3.3V

OUT2

GN

D3

IN 1

C640.1uFC640.1uF

+ C7010uF

+ C7010uF

+ C6210uF

+ C6210uF

TP4TP(BLACK)TP4TP(BLACK)

1

L310uHL310uH TM1

TJ-563

TM1

TJ-563

i1

TP6TP(BLACK)TP6TP(BLACK)

1

+ C68100uF/16V(A)

+ C68100uF/16V(A)

C720.1uFC720.1uF

JP6P-DVDD

JP6P-DVDD

12

C630.1uFC630.1uF

- 36 -

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SMUX-MCLKSMUX-BICKSMUX-LRCKSMUX-DAT1

SMUX-DAT2

SMUX-DVDD

SMUX2-MCLKSMUX2-BICKSMUX2-LRCKSMUX2-DAT1

SMUX2-DAT2

PC-SIPC-RQN

PC-CS2N

PC-SCLK

PC-I2CSELPC-INITRSTN

PC-SDA

PC-SOPC-SCL

TRX-PDNTX-CLKTX-DATRX-CLK2TRX-BICKRX-DATTRX-LRCKRX-CLK

LED-IND

DVDD-3.3V

DVDD-3.3V

DVDD-3.3V

DVDD-3.3V

DVDD-3.3V

SDOUT1SDOUT2SDOUT3SDOUT4

CKM3SETSRC

SCLK

SIRQNSDIN4BICKI2LRCKI2SO

TESTI1CKM2CKM1SDIN1SDIN2SDIN3BICKI1LRCKI1EXT-XTI

RSTNI2CSEL

CLKOBICKOLRCKOCKM0

TESTI2

DAC-PDN

STO

Title

Size Document Number Rev

Date: Sheet ofXILINX 0

AKD7734-AA3

8 8Wednesday, May 21, 2008

Title

Size Document Number Rev

Date: Sheet ofXILINX 0

AKD7734-AA3

8 8Wednesday, May 21, 2008

Title

Size Document Number Rev

Date: Sheet ofXILINX 0

AKD7734-AA3

8 8Wednesday, May 21, 2008

SILK-SCREENSMUX PORT/SMUX PORT21: MCLK3: BIT5: LR7: DI10: DO

SMUX PORT1

SMUX PORT2

DVSSC85 0.1uFC85 0.1uF

+ C7910uF

+ C7910uF

C760.1uFC760.1uF

R66 51R66 51

U10

XC95144XL

U10

XC95144XL

GSR99GTS42GTS31GTS24GTS13GCK327GCK223GCK122

TCK48TDI45TDO83TMS47

VINT0 5VINT1 57VINT2 98

VIO0 26VIO1 38VIO2 51VIO3 88

GND0 21GND1 31GND2 44GND3 62GND4 69GND5 75GND6 84GND7 100

I/O06I/O17I/O28I/O39I/O410I/O511I/O612I/O713I/O814I/O915I/O1016I/O1117I/O1218I/O1319I/O1420I/O1524I/O1625I/O1728I/O1829I/O1930I/O2032I/O2133I/O2234I/O2335I/O2436I/O2537I/O2639I/O2740I/O2841I/O2942I/O3043I/O3146I/O3249I/O3350

I/O34 52I/O35 53I/O36 54I/O37 55I/O38 56I/O39 58I/O40 59I/O41 60I/O42 61I/O43 63I/O44 64I/O45 65I/O46 66I/O47 67I/O48 68I/O49 70I/O50 71I/O51 72I/O52 73I/O53 74I/O54 76I/O55 77I/O56 78I/O57 79I/O58 80I/O59 81I/O60 82I/O61 85I/O62 86I/O63 87I/O64 89I/O65 90I/O66 91I/O67 92I/O68 93I/O69 94I/O70 95I/O71 96I/O72 97

R45 51R45 51

R42 51R42 51

R57 51R57 51

C820.1uFC820.1uF

R53 51R53 51

C780.1uFC780.1uF

TP7DVSS (BLACK)TP7DVSS (BLACK)

1

R58 51R58 51

R63 51R63 51

C870.1uFC870.1uF

R48 51R48 51

R56 51R56 51

C770.1uFC770.1uF

JP8

HEADER 5X2

JP8

HEADER 5X2

1 23 45 67 89 10

R62 51R62 51

+ C86100uF/16V(A)

+ C86100uF/16V(A)

R41 470R41 47012

JP9

JTAG

JP9

JTAG

1 23 45 67 89 10

R67 51R67 51

R46 51R46 51

+ C8410uF

+ C8410uF

R43 51R43 51

D1

LEAD RED LED

D1

LEAD RED LED

12

C810.1uFC810.1uF

R54 51R54 51

R64 51R64 51

JP7

HEADER 5X2

JP7

HEADER 5X2

1 23 45 67 89 10

C740.1uFC740.1uF

R61 51R61 51

R65 51R65 51

R60 51R60 51

R49 51R49 51

C800.1uFC800.1uF

R59 51R59 51

R51 51R51 51

C830.1uFC830.1uF

R52 51R52 51

TP8

DVDD (RED)

TP8

DVDD (RED)

1

+ C7510uF

+ C7510uF

R44 51R44 51

R47 51R47 51

R55 51R55 51

- 37 -

- 38 -

- 39 -

- 40 -

- 41 -

- 42 -

- 43 -

- 44 -

- 45 -

- 46 -

- 47 -

- 48 -

- 49 -

- 50 -

- 51 -