ain shams university faculty of engineering integrated circuits lab vlsi design and implementation...
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Ain Shams UniversityAin Shams UniversityFaculty of EngineeringFaculty of Engineering
Integrated Circuits LabIntegrated Circuits Lab
VLSI Design and Implementation of VLSI Design and Implementation of ASICs for the Security Core of ASICs for the Security Core of
BLUETOOTH Wireless Communication BLUETOOTH Wireless Communication System StandardSystem Standard
Presented By:Sameh Assem IbrahimAhmad Abdelhameed
16 – July - 2001
2/16
Introduction Auth. & Key gen. Encryption Security core ASIC/FPGA
Introduction
Bluetooth SecurityBluetooth Security
Key generationKey generation EncryptionEncryptionAuthenticationAuthentication
Bluetooth BasebandBluetooth Baseband
Error CorrectionCorrection Hop SelectionHop Selection
SecuritySecurity OthersOthers
BluetoothBluetooth ArchitectureArchitecture
RFRF
BasebandBaseband
Link ManagerManager
SoftwareSoftware LayersLayers
16 – July - 2001
3/16Authentication & Key Generation
Package List
ieee std_logic_1164 ieee std_logic_arith
Declarations
algorithm
e_type : (1:0)
clkend_algostart_algo
ad_PIN_COFu : (47:0)
bdadb_COFl : (47:0)
algo_out : (127:0)
rst
key : (127:0) Rand : (127:0)
key_change
Design GoalsDesign Goals
E1 , E21, E22 and E3 algorithms implementation
Introduction Encryption Security core ASIC/FPGA
16 – July - 2001
4/16Authentication & Key Generation
Introduction Encryption Security core ASIC/FPGA
Ar/Ar’Controller
Input preparation
Feedback operationsoutput
e_type : (1:0)
start_algo
clk
rst
bdadb_COFl : (47:0)
a : (7:0)
b : (7:0)c : (7:0)
key : (127:0)Rand : (127:0)
output_4 : (7:0)
input : (7:0)
e_type(0) : (1:0)
Rand(7:0) : (127:0)
Rand(127:8) : (127:0) Concatenation
ad_PIN_COFu : (47:0)
SAFER
e_type(0) : (1:0)
algo_out : (127:0)
in1 : (127:0) in2 : (127:0)
key_change
in_2 : (127:0)
offset
key : (127:0)output_7 : (127:0)
y
in1 : (127:0) in2 : (127:0)
output : (127:0)sel
output_9 : (127:0)
e_type(0) : (1:0)
in1 : (127:0) in2 : (127:0)
output : (127:0)sel
output : (127:0)
in2 : (127:0)
algo_controlclk
e_type : (1:0)
start_algo
rst
dash
key : (127:0)
output : (127:0)
dash
output_2 : (127:0)
rst
sel
y
z
rst
e_type(1) : (1:0)
clkdonegodone
go
dash
go
key_change
cipher_text : (127:0)
cipher_text : (127:0) done
in1 : (127:0) in2 : (127:0)
in1 : (127:0) in2 : (127:0)
output : (127:0)sel
in1 : (127:0) in2 : (127:0)
output : (127:0)sel
output_1 : (127:0)
y
output_7 : (127:0)
output_8 : (127:0)
in_2 : (127:0)
in1 : (127:0) in2 : (127:0)
output : (127:0)sel
plain_text : (127:0)
output : (127:0)sel
output_3 : (127:0)
e_type(1) : (1:0)
Package List
ieee std_logic_1164 ieee std_logic_arith ieee std_logic_unsigned bdadb_COFl : std_logic_vector(47 DOWNTO 0)
end_algo
DeclarationsPorts:
ad_PIN_COFu : std_logic_vector(47 DOWNTO 0)Rand : std_logic_vector(127 DOWNTO 0)
end_algo
reg128
z
out_2 : (127:0)
end_algo
Diagram Signals:
SIGNAL output : std_logic_vector(127 DOWNTO 0)SIGNAL output_1 : std_logic_vector(127 DOWNTO 0)
SIGNAL output_2 : std_logic_vector(127 DOWNTO 0)SIGNAL output_3 : std_logic_vector(127 DOWNTO 0)
SIGNAL dash : std_logic
SIGNAL go : std_logic
SIGNAL y : std_logic
SIGNAL cipher_text : std_logic_vector(127 DOWNTO 0)
SIGNAL z : std_logic
e_type : std_logic_vector(1 DOWNTO 0)
SIGNAL in2 : std_logic_vector(127 downto 0)
SIGNAL output_4 : std_logic_vector(7 DOWNTO 0)
SIGNAL done : std_logic
SIGNAL in_2 : std_logic_vector(127 DOWNTO 0)
clk : std_logic
start_algo : std_logic
end_algo : std_logic
SIGNAL out_3 : std_logic_vector(127 downto 0)
SIGNAL output_5 : std_logic_vector(127 DOWNTO 0)SIGNAL output_6 : std_logic_vector(127 DOWNTO 0)SIGNAL output_7 : std_logic_vector(127 downto 0)
SIGNAL input : std_logic_vector(7 downto 0)
SIGNAL output_8 : std_logic_vector(127 DOWNTO 0)SIGNAL output_9 : std_logic_vector(127 DOWNTO 0)
SIGNAL out_2 : std_logic_vector(127 downto 0)
algo_out : std_logic_vector(127 DOWNTO 0)
rst : std_logickey : std_logic_vector(127 DOWNTO 0)
SIGNAL output_10 : std_logic_vector(127 downto 0)SIGNAL output_11 : std_logic_vector(127 downto 0)
key_change : std_logic
Bluetooth SecurityICL
by Sameh Assem on 14 2001 يوليو
Project:
Different AlgorithmsTitle:
Path:
E1,E21,E22,E3
Project2001/algorithm/struct
Edited:
xor_128
input1 : (127:0)
input2 : (127:0)output : (127:0)
add_128
input1 : (127:0)
input2 : (127:0)
output : (127:0)
out_3 : (127:0)
Rand : (127:0)
output_5 : (127:0)
output_6 : (127:0)
Block DiagramBlock Diagram
16 – July - 2001
5/16Authentication & Key Generation
Introduction Encryption Security core ASIC/FPGA
Key Schedule
SAFER+Encryption Round
Controlleroutput
Final roundoperations
Feedback operationsIn case of Ar’
safer_control
plain_text : (127:0)
dash
rst
clk
go
done
Package List
ieee std_logic_1164 ieee std_logic_arith
excess_operations
reg128
key_sched
round
key : (127:0)
Bluetooth SecurityICL
by Sameh Assem on 14 2001 يوليو
Project:
SAFER+ EncryptionTitle:
Path:
Ar or Ar' block
Edited:
cipher_text : (127:0)
Project2001/safer/struct
DeclarationsPorts:
Diagram Signals:
plain_text : std_logic_vector(127 DOWNTO 0)
SIGNAL int : std_logicSIGNAL input1 : std_logic_vector(127 DOWNTO 0)SIGNAL input : std_logic_vector(127 downto 0)
clk : std_logic
key : std_logic_vector(127 DOWNTO 0)
dash : std_logicgo : std_logic
rst : std_logiccipher_text : std_logic_vector(127 DOWNTO 0)
SIGNAL end_round : std_logic
done : std_logic
SIGNAL done_1 : std_logic
SIGNAL output_2 : std_logic_vector(127 downto 0)SIGNAL round_output : std_logic_vector(127 DOWNTO 0)
SIGNAL output : std_logic_vector(127 downto 0)SIGNAL out2 : std_logic_vector(127 downto 0)
SIGNAL s0 : std_logic
SIGNAL k17 : std_logic_vector(127 DOWNTO 0)
SIGNAL s1 : std_logic
SIGNAL out1 : std_logic_vector(127 downto 0)
SIGNAL output_1 : std_logic_vector(127 downto 0)
SIGNAL sel : std_logic_vector(2 downto 0)
SIGNAL kii : std_logic_vector(127 DOWNTO 0)SIGNAL ki : std_logic_vector(127 DOWNTO 0)
Ar/Ar'Ar/Ar'
16 – July - 2001
6/16Authentication & Key Generation
Introduction Encryption Security core ASIC/FPGA
Sequential
k1
feedback
k1 : std_logic_vector(127 DOWNTO 0)
SIGNAL out0 : std_logic_vector(7 DOWNTO 0)
SIGNAL out2 : std_logic_vector(7 DOWNTO 0)
SIGNAL out1 : std_logic_vector(7 DOWNTO 0)
SIGNAL out4 : std_logic_vector(7 DOWNTO 0)SIGNAL out3 : std_logic_vector(7 DOWNTO 0)
SIGNAL out6 : std_logic_vector(7 DOWNTO 0)SIGNAL out5 : std_logic_vector(7 DOWNTO 0)
SIGNAL out8 : std_logic_vector(7 DOWNTO 0)SIGNAL out7 : std_logic_vector(7 DOWNTO 0)
SIGNAL out10 : std_logic_vector(7 DOWNTO 0)
SIGNAL out9 : std_logic_vector(7 DOWNTO 0)
SIGNAL out12 : std_logic_vector(7 DOWNTO 0)SIGNAL out11 : std_logic_vector(7 DOWNTO 0)
SIGNAL out14 : std_logic_vector(7 DOWNTO 0)SIGNAL out13 : std_logic_vector(7 DOWNTO 0)
SIGNAL out16 : std_logic_vector(7 DOWNTO 0)SIGNAL out15 : std_logic_vector(7 DOWNTO 0)
SIGNAL in1 : std_logic_vector(135 DOWNTO 0)
SIGNAL output : std_logic_vector(135 DOWNTO 0)
SIGNAL input : std_logic_vector(135 DOWNTO 0)
SIGNAL output_1 : std_logic_vector(135 DOWNTO 0)
SIGNAL out_1 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_3 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_2 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_4 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_6 : std_logic_vector(7 DOWNTO 0)SIGNAL out_5 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_8 : std_logic_vector(7 DOWNTO 0)SIGNAL out_7 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_10 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_9 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_12 : std_logic_vector(7 DOWNTO 0)SIGNAL out_11 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_14 : std_logic_vector(7 DOWNTO 0)SIGNAL out_13 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_16 : std_logic_vector(7 DOWNTO 0)SIGNAL out_15 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_18 : std_logic_vector(7 DOWNTO 0)SIGNAL out_17 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_20 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_19 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_22 : std_logic_vector(7 DOWNTO 0)SIGNAL out_21 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_24 : std_logic_vector(7 DOWNTO 0)SIGNAL out_23 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_26 : std_logic_vector(7 DOWNTO 0)SIGNAL out_25 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_28 : std_logic_vector(7 DOWNTO 0)SIGNAL out_27 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_29 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_31 : std_logic_vector(7 DOWNTO 0)SIGNAL out_30 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_33 : std_logic_vector(7 DOWNTO 0)SIGNAL out_32 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_34 : std_logic_vector(7 DOWNTO 0)
sel : std_logic_vector(2 downto 0)
ki : std_logic_vector(127 DOWNTO 0)
SIGNAL Bi : std_logic_vector(127 DOWNTO 0)SIGNAL Bii : std_logic_vector(127 DOWNTO 0)
kii : std_logic_vector(127 DOWNTO 0)
SIGNAL B17 : std_logic_vector(127 DOWNTO 0)
k17 : std_logic_vector(127 DOWNTO 0)
feedback : std_logic
bias_rom
SIGNAL Q : std_logic
D : std_logicCLK : std_logic
octets_sum
octets_rotateoctets_circulate
octets_rotateoctets_circulate
reg136
sel : (2:0)
+
+
++
+
+
+
+
+
+
+
+
+
+
+
+
D QD
CLK
Q
ICL
by Sameh Assem on 14 2001 يوليو
Key SchedulerTitle:
Path: Project2001/key_sched/struct
Edited:
Bluetooth SecurityProject:
A sequential key scheduler
Package List
ieee std_logic_1164 ieee std_logic_arith
DeclarationsPorts:
Diagram Signals:
+
kii : (127:0)
k17
ki : (127:0)
++
++
++
++
+
+
++
+
++
+
+
+
+
+
+
+
+
+
++
+
+
+
++
Combinational
octets_rotate+SIGNAL out_217 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_125 : std_logic_vector(7 DOWNTO 0)
SIGNAL k5 : std_logic_vector(127 DOWNTO 0)
SIGNAL b_1 : std_logic_vector(7 downto 0)
Decl ar at i ons
Port s:
Di agram Si gnal s:
k1 : std_logic_vector(127 DOWNTO 0)
SIGNAL B2 : std_logic_vector(127 DOWNTO 0)
SIGNAL b : std_logic_vector(7 downto 0)
SIGNAL B3 : std_logic_vector(127 DOWNTO 0)
SIGNAL B4 : std_logic_vector(127 DOWNTO 0)SIGNAL B5 : std_logic_vector(127 DOWNTO 0)
SIGNAL B6 : std_logic_vector(127 DOWNTO 0)SIGNAL B7 : std_logic_vector(127 DOWNTO 0)SIGNAL B8 : std_logic_vector(127 DOWNTO 0)
SIGNAL B9 : std_logic_vector(127 DOWNTO 0)
SIGNAL B10 : std_logic_vector(127 DOWNTO 0)SIGNAL B11 : std_logic_vector(127 DOWNTO 0)
SIGNAL B12 : std_logic_vector(127 DOWNTO 0)SIGNAL B13 : std_logic_vector(127 DOWNTO 0)SIGNAL B14 : std_logic_vector(127 DOWNTO 0)
SIGNAL B15 : std_logic_vector(127 DOWNTO 0)SIGNAL B16 : std_logic_vector(127 DOWNTO 0)
SIGNAL B17 : std_logic_vector(127 DOWNTO 0)
k17 : std_logic_vector(127 DOWNTO 0)
k2r_1 : std_logic_vector(127 DOWNTO 0)k2r : std_logic_vector(127 DOWNTO 0)
sel : std_logic_vector(2 downto 0)
SIGNAL in16 : std_logic_vector(7 downto 0)
SIGNAL k2 : std_logic_vector(127 DOWNTO 0)
SIGNAL b_2 : std_logic_vector(7 downto 0)SIGNAL b_3 : std_logic_vector(7 downto 0)SIGNAL b_4 : std_logic_vector(7 downto 0)
SIGNAL b_5 : std_logic_vector(7 downto 0)SIGNAL b_6 : std_logic_vector(7 downto 0)
SIGNAL b_7 : std_logic_vector(7 downto 0)SIGNAL b_8 : std_logic_vector(7 downto 0)SIGNAL b_9 : std_logic_vector(7 downto 0)
SIGNAL b_10 : std_logic_vector(7 downto 0)SIGNAL b_11 : std_logic_vector(7 downto 0)
SIGNAL b_12 : std_logic_vector(7 downto 0)SIGNAL b_13 : std_logic_vector(7 downto 0)SIGNAL b_14 : std_logic_vector(7 downto 0)
SIGNAL k3 : std_logic_vector(127 DOWNTO 0)SIGNAL k4 : std_logic_vector(127 DOWNTO 0)
SIGNAL k10 : std_logic_vector(127 DOWNTO 0)SIGNAL k11 : std_logic_vector(127 DOWNTO 0)
SIGNAL k12 : std_logic_vector(127 DOWNTO 0)SIGNAL k13 : std_logic_vector(127 DOWNTO 0)
SIGNAL k14 : std_logic_vector(127 DOWNTO 0)SIGNAL k15 : std_logic_vector(127 DOWNTO 0)SIGNAL k16 : std_logic_vector(127 DOWNTO 0)
SIGNAL out_102 : std_logic_vector(7 DOWNTO 0)
SIGNAL out0 : std_logic_vector(7 DOWNTO 0)SIGNAL out1 : std_logic_vector(7 DOWNTO 0)
SIGNAL out2 : std_logic_vector(7 DOWNTO 0)SIGNAL out3 : std_logic_vector(7 DOWNTO 0)
SIGNAL out4 : std_logic_vector(7 DOWNTO 0)SIGNAL out5 : std_logic_vector(7 DOWNTO 0)
SIGNAL out6 : std_logic_vector(7 DOWNTO 0)SIGNAL out7 : std_logic_vector(7 DOWNTO 0)SIGNAL out8 : std_logic_vector(7 DOWNTO 0)
SIGNAL out9 : std_logic_vector(7 DOWNTO 0)
SIGNAL out10 : std_logic_vector(7 DOWNTO 0)
SIGNAL out11 : std_logic_vector(7 DOWNTO 0)SIGNAL out12 : std_logic_vector(7 DOWNTO 0)
SIGNAL out13 : std_logic_vector(7 DOWNTO 0)SIGNAL out14 : std_logic_vector(7 DOWNTO 0)SIGNAL out15 : std_logic_vector(7 DOWNTO 0)
SIGNAL out16 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_1 : std_logic_vector(7 downto 0)SIGNAL out_10 : std_logic_vector(7 downto 0)
SIGNAL out_100 : std_logic_vector(7 DOWNTO 0)SIGNAL out_101 : std_logic_vector(7 DOWNTO 0)
SIGNAL k6 : std_logic_vector(127 DOWNTO 0)
SIGNAL k7 : std_logic_vector(127 DOWNTO 0)SIGNAL k8 : std_logic_vector(127 DOWNTO 0)SIGNAL k9 : std_logic_vector(127 DOWNTO 0)
SIGNAL out_11 : std_logic_vector(7 downto 0)
SIGNAL out_12 : std_logic_vector(7 downto 0)
SIGNAL out_103 : std_logic_vector(7 DOWNTO 0)SIGNAL out_104 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_105 : std_logic_vector(7 DOWNTO 0)SIGNAL out_106 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_107 : std_logic_vector(7 DOWNTO 0)SIGNAL out_108 : std_logic_vector(7 DOWNTO 0)SIGNAL out_109 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_110 : std_logic_vector(7 DOWNTO 0)SIGNAL out_111 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_112 : std_logic_vector(7 DOWNTO 0)SIGNAL out_113 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_114 : std_logic_vector(7 DOWNTO 0)SIGNAL out_115 : std_logic_vector(7 DOWNTO 0)SIGNAL out_116 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_117 : std_logic_vector(7 DOWNTO 0)SIGNAL out_118 : std_logic_vector(7 DOWNTO 0)SIGNAL out_119 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_120 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_121 : std_logic_vector(7 DOWNTO 0)SIGNAL out_122 : std_logic_vector(7 DOWNTO 0)SIGNAL out_123 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_124 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_171 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_149 : std_logic_vector(7 downto 0)
SIGNAL out_13 : std_logic_vector(7 downto 0)
SIGNAL out_14 : std_logic_vector(7 downto 0)
SIGNAL out_126 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_127 : std_logic_vector(7 DOWNTO 0)SIGNAL out_128 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_129 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_130 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_131 : std_logic_vector(7 DOWNTO 0)SIGNAL out_132 : std_logic_vector(7 DOWNTO 0)SIGNAL out_133 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_134 : std_logic_vector(7 DOWNTO 0)SIGNAL out_135 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_136 : std_logic_vector(7 DOWNTO 0)SIGNAL out_137 : std_logic_vector(7 downto 0)SIGNAL out_138 : std_logic_vector(7 downto 0)
SIGNAL out_139 : std_logic_vector(7 downto 0)
SIGNAL out_140 : std_logic_vector(7 downto 0)
SIGNAL out_141 : std_logic_vector(7 downto 0)SIGNAL out_142 : std_logic_vector(7 downto 0)
SIGNAL out_143 : std_logic_vector(7 downto 0)SIGNAL out_144 : std_logic_vector(7 downto 0)SIGNAL out_145 : std_logic_vector(7 downto 0)
SIGNAL out_146 : std_logic_vector(7 downto 0)SIGNAL out_147 : std_logic_vector(7 downto 0)SIGNAL out_148 : std_logic_vector(7 downto 0)
SIGNAL out_15 : std_logic_vector(7 downto 0)
SIGNAL out_16 : std_logic_vector(7 downto 0)
SIGNAL out_17 : std_logic_vector(7 downto 0)
SIGNAL out_150 : std_logic_vector(7 downto 0)SIGNAL out_151 : std_logic_vector(7 downto 0)SIGNAL out_152 : std_logic_vector(7 downto 0)
SIGNAL out_153 : std_logic_vector(7 downto 0)SIGNAL out_154 : std_logic_vector(7 DOWNTO 0)SIGNAL out_155 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_156 : std_logic_vector(7 DOWNTO 0)SIGNAL out_157 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_158 : std_logic_vector(7 DOWNTO 0)SIGNAL out_159 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_160 : std_logic_vector(7 DOWNTO 0)SIGNAL out_161 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_162 : std_logic_vector(7 DOWNTO 0)SIGNAL out_163 : std_logic_vector(7 DOWNTO 0)SIGNAL out_164 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_165 : std_logic_vector(7 DOWNTO 0)SIGNAL out_166 : std_logic_vector(7 DOWNTO 0)SIGNAL out_167 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_168 : std_logic_vector(7 DOWNTO 0)SIGNAL out_169 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_170 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_195 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_18 : std_logic_vector(7 downto 0)
SIGNAL out_19 : std_logic_vector(7 downto 0)
SIGNAL out_172 : std_logic_vector(7 DOWNTO 0)SIGNAL out_173 : std_logic_vector(7 DOWNTO 0)SIGNAL out_174 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_175 : std_logic_vector(7 DOWNTO 0)SIGNAL out_176 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_177 : std_logic_vector(7 DOWNTO 0)SIGNAL out_178 : std_logic_vector(7 DOWNTO 0)SIGNAL out_179 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_180 : std_logic_vector(7 DOWNTO 0)SIGNAL out_181 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_182 : std_logic_vector(7 DOWNTO 0)SIGNAL out_183 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_184 : std_logic_vector(7 DOWNTO 0)SIGNAL out_185 : std_logic_vector(7 DOWNTO 0)SIGNAL out_186 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_187 : std_logic_vector(7 DOWNTO 0)SIGNAL out_188 : std_logic_vector(7 DOWNTO 0)SIGNAL out_189 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_190 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_191 : std_logic_vector(7 DOWNTO 0)SIGNAL out_192 : std_logic_vector(7 DOWNTO 0)SIGNAL out_193 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_194 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_2 : std_logic_vector(7 downto 0)SIGNAL out_20 : std_logic_vector(7 downto 0)
SIGNAL out_21 : std_logic_vector(7 downto 0)
SIGNAL out_196 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_197 : std_logic_vector(7 DOWNTO 0)SIGNAL out_198 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_199 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_200 : std_logic_vector(7 DOWNTO 0)SIGNAL out_201 : std_logic_vector(7 DOWNTO 0)SIGNAL out_202 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_203 : std_logic_vector(7 DOWNTO 0)SIGNAL out_204 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_205 : std_logic_vector(7 DOWNTO 0)SIGNAL out_206 : std_logic_vector(7 DOWNTO 0)SIGNAL out_207 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_208 : std_logic_vector(7 DOWNTO 0)SIGNAL out_209 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_210 : std_logic_vector(7 DOWNTO 0)SIGNAL out_211 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_212 : std_logic_vector(7 DOWNTO 0)SIGNAL out_213 : std_logic_vector(7 DOWNTO 0)SIGNAL out_214 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_215 : std_logic_vector(7 DOWNTO 0)SIGNAL out_216 : std_logic_vector(7 DOWNTO 0)
++
Panel 0
octets_sum
octets_rotate+
+
in2
in15
out 15
in0in1
in6
out 6
in2
out 2
in0 in1 in3 in4 in5
out 0out 1 out 3out 4out 5
in11
out 10out 11
in10in7 in8 in9 in12 in13 in14
out 7out 8out 9 out 12out 13out 14
in10in9
in3in4in5in6in7in8
in11in12in13in14in15
out put
in16
out 16
++
octets_rotate
in14
out 14
octets_rotate
in14
out 14
+
in5
out 5
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10
out 10
in6 in7 in8 in9
out 6out 7out 8out 9
in11 in12 in13
out 11out 12out 13
+
++
+ +
++
+
++
+
++
+
+
in15in16
out 15out 16
+
+
+
+
in5
out 5
in0 in1 in2 in3 in4 in10 in11 in12 in13in6 in7 in8 in9
out 0out 1out 2out 3out 4 out 10out 11out 12out 13out 6out 7out 8out 9
+
++
++
in15in16
+
++
+
+
out 15out 16
++
+
+
+
+
++
+
octets_rotate
in14
out 14
octets_rotate
in14
out 14
in14
in5
out 5
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10 in11 in12 in13in6 in7 in8 in9
out 10out 11out 12out 13out 6out 7out 8out 9
++
in15in16
out 15out 16
+
+
++
+
+
+
+
++
+
+
+
+
+
+
+
in5
out 5
in5
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10
out 10out 11out 12out 13out 6out 7out 8out 9
in6 in7 in8 in9 in11 in12 in13
in0 in1 in2 in3 in4 in10 in11 in12 in13in6 in7 in8 in9
+
+
+
out 15out 16
+
in15in16
++
+
+
+ +
+
in15in16
+
+
+
++
octets_rotate
out 14
octets_rotate
in14
out 14
in14
out 14
out 5
in5
out 5
out 0out 1out 2out 3out 4 out 10out 11out 12out 13out 6out 7out 8out 9
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10 in11 in12 in13in6 in7 in8 in9
out 10out 11out 12out 13out 6out 7out 8out 9
+
+
+
out 15out 16
++
+
+
+
+
+
+
in15in16
out 15out 16
++
+
++
in5
out 5
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10
out 10
in6 in7 in8 in9 in11 in12 in13
out 6out 7out 8out 9 out 11out 12out 13
+
++
+
+
+
+
+
++
++
++
+
++
in15in16
out 15out 16
++
+
SIGNAL out_94 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_48 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_24 : std_logic_vector(7 downto 0)
SIGNAL out_22 : std_logic_vector(7 downto 0)
SIGNAL out_23 : std_logic_vector(7 downto 0)
SIGNAL out_218 : std_logic_vector(7 DOWNTO 0)SIGNAL out_219 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_220 : std_logic_vector(7 DOWNTO 0)SIGNAL out_221 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_222 : std_logic_vector(7 downto 0)SIGNAL out_223 : std_logic_vector(7 downto 0)
SIGNAL out_224 : std_logic_vector(7 downto 0)SIGNAL out_225 : std_logic_vector(7 downto 0)SIGNAL out_226 : std_logic_vector(7 downto 0)
SIGNAL out_227 : std_logic_vector(7 downto 0)SIGNAL out_228 : std_logic_vector(7 downto 0)SIGNAL out_229 : std_logic_vector(7 downto 0)
SIGNAL out_230 : std_logic_vector(7 downto 0)
SIGNAL out_231 : std_logic_vector(7 downto 0)SIGNAL out_232 : std_logic_vector(7 downto 0)SIGNAL out_233 : std_logic_vector(7 downto 0)
SIGNAL out_234 : std_logic_vector(7 downto 0)SIGNAL out_235 : std_logic_vector(7 downto 0)SIGNAL out_236 : std_logic_vector(7 downto 0)
SIGNAL out_237 : std_logic_vector(7 downto 0)SIGNAL out_238 : std_logic_vector(7 downto 0)
SIGNAL out_239 : std_logic_vector(7 downto 0)
SIGNAL out_3 : std_logic_vector(7 downto 0)
SIGNAL out_4 : std_logic_vector(7 downto 0)
SIGNAL out_25 : std_logic_vector(7 downto 0)
SIGNAL out_26 : std_logic_vector(7 downto 0)SIGNAL out_27 : std_logic_vector(7 downto 0)SIGNAL out_28 : std_logic_vector(7 downto 0)
SIGNAL out_29 : std_logic_vector(7 downto 0)
SIGNAL out_30 : std_logic_vector(7 downto 0)SIGNAL out_31 : std_logic_vector(7 downto 0)SIGNAL out_32 : std_logic_vector(7 downto 0)
SIGNAL out_33 : std_logic_vector(7 downto 0)SIGNAL out_34 : std_logic_vector(7 downto 0)SIGNAL out_35 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_36 : std_logic_vector(7 DOWNTO 0)SIGNAL out_37 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_38 : std_logic_vector(7 DOWNTO 0)SIGNAL out_39 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_40 : std_logic_vector(7 DOWNTO 0)SIGNAL out_41 : std_logic_vector(7 DOWNTO 0)SIGNAL out_42 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_43 : std_logic_vector(7 DOWNTO 0)SIGNAL out_44 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_45 : std_logic_vector(7 DOWNTO 0)SIGNAL out_46 : std_logic_vector(7 DOWNTO 0)SIGNAL out_47 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_70 : std_logic_vector(7 downto 0)
SIGNAL out_5 : std_logic_vector(7 downto 0)
SIGNAL out_6 : std_logic_vector(7 downto 0)
SIGNAL out_7 : std_logic_vector(7 downto 0)
SIGNAL out_49 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_50 : std_logic_vector(7 DOWNTO 0)SIGNAL out_51 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_52 : std_logic_vector(7 DOWNTO 0)SIGNAL out_53 : std_logic_vector(7 DOWNTO 0)SIGNAL out_54 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_55 : std_logic_vector(7 DOWNTO 0)SIGNAL out_56 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_57 : std_logic_vector(7 DOWNTO 0)SIGNAL out_58 : std_logic_vector(7 DOWNTO 0)SIGNAL out_59 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_60 : std_logic_vector(7 DOWNTO 0)SIGNAL out_61 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_62 : std_logic_vector(7 DOWNTO 0)SIGNAL out_63 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_64 : std_logic_vector(7 DOWNTO 0)SIGNAL out_65 : std_logic_vector(7 DOWNTO 0)SIGNAL out_66 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_67 : std_logic_vector(7 DOWNTO 0)SIGNAL out_68 : std_logic_vector(7 DOWNTO 0)SIGNAL out_69 : std_logic_vector(7 downto 0)
SIGNAL out_8 : std_logic_vector(7 downto 0)
SIGNAL out_9 : std_logic_vector(7 downto 0)
SIGNAL out_71 : std_logic_vector(7 downto 0)SIGNAL out_72 : std_logic_vector(7 downto 0)SIGNAL out_73 : std_logic_vector(7 downto 0)
SIGNAL out_74 : std_logic_vector(7 downto 0)SIGNAL out_75 : std_logic_vector(7 downto 0)SIGNAL out_76 : std_logic_vector(7 downto 0)
SIGNAL out_77 : std_logic_vector(7 downto 0)SIGNAL out_78 : std_logic_vector(7 downto 0)
SIGNAL out_79 : std_logic_vector(7 downto 0)
SIGNAL out_80 : std_logic_vector(7 downto 0)
SIGNAL out_81 : std_logic_vector(7 downto 0)SIGNAL out_82 : std_logic_vector(7 downto 0)SIGNAL out_83 : std_logic_vector(7 downto 0)
SIGNAL out_84 : std_logic_vector(7 downto 0)SIGNAL out_85 : std_logic_vector(7 downto 0)
SIGNAL out_86 : std_logic_vector(7 DOWNTO 0)SIGNAL out_87 : std_logic_vector(7 DOWNTO 0)SIGNAL out_88 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_89 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_90 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_91 : std_logic_vector(7 DOWNTO 0)SIGNAL out_92 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_93 : std_logic_vector(7 DOWNTO 0)
Package List
ieee st d_logic_1164 ieee st d_logic_ar it h
Bluet oot h Secur it yI CL
by Sam eh Assem on 14 2001 و ي ل و ي
Pr oject :
Key Schedule of t he SAFER+ algor it hmTit le:
Pat h:
This block is used in t he Ar and Ar ' blocks of t he
E1 algor it hmPr oject 2001b/ key_sched/ key_sched_ar ch
Edit ed:
SIGNAL out_95 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_96 : std_logic_vector(7 DOWNTO 0)SIGNAL out_97 : std_logic_vector(7 DOWNTO 0)SIGNAL out_98 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_99 : std_logic_vector(7 DOWNTO 0)
octets_rotate
+
octets_rotate
in14
out 14
octets_rotate
in14
out 14
+
in5
out 5
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10
out 10
in6 in7 in8 in9
out 6out 7out 8out 9
in11 in12 in13
out 11out 12out 13
+
+
+
+
+
+
+
++
+
++
+
+
in15in16
out 15out 16
+
++
+
+
in5
out 0out 1 out 10out 11out 12out 13out 2out 3out 4out 5out 6out 7out 8out 9
in0 in1 in2 in3 in4 in10 in11 in12 in13in6 in7 in8 in9
out 15out 16
+
+
++
in15in16
+
+
+
+
++
++
++
+
+
+
++
+
octets_rotate
in14
out 14
octets_rotate
in14
out 14
in14
in5
out 5
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10
out 10
in6 in7 in8 in9 in11 in12 in13
out 6out 7out 8out 9 out 11out 12out 13
+
in15in16
out 15out 16
++
++
+
+
+
+
++
+
+
+
+
+
++
in5
out 5
in5
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10
out 10
in6 in7 in8 in9
out 6out 7out 8out 9
in11 in12 in13
out 11out 12out 13
in0 in1 in2 in3 in4 in10 in11 in12 in13in6 in7 in8 in9
+
+
+
in15in16
out 15out 16
+
+
+
+
+
++
++
in15in16
+
++
+
octets_rotate+
octets_rotate
out 14
octets_rotate
in14
out 14
in14
out 14
++
out 5
in5
out 5
out 0out 1out 2out 3out 4 out 10out 11out 12out 13out 6out 7out 8out 9
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10 in11 in12 in13in6 in7 in8 in9
out 10out 11out 12out 13out 6out 7out 8out 9
+
+
+
out 15out 16
++
+
+
+
+
++
+
in15in16
out 15out 16
++
++
in5
out 5
in0 in1 in2 in3 in4
out 0out 1out 2out 3out 4
in10
out 10out 11out 12out 13out 6out 7out 8out 9
in6 in7 in8 in9 in11 in12 in13
+
+
+
++
+
++
+
+
+
+
+
+
+
out 15out 16
+
in15in16
++
+
in14
out 14
++
in0 in1 in10 in11 in12 in13in2 in3 in4 in5 in6 in7 in8 in9
out 5out 0out 1out 2out 3out 4 out 10out 11out 12out 13out 6out 7out 8out 9
in15in16
+
+
++
++
++
+
++
+
out 15out 16
++
+
++
+
+
++
+
++
B2 B3 B4
bias_romB13B10 B11 B12B5 B6 B7 B8 B9 B14 B15 B16 B17
mux16x2
Key ScheduleKey Schedule
16 – July - 2001
7/16Authentication & Key Generation
Introduction Encryption Security core ASIC/FPGA
Sequential
round_input : (127:0)
output
@ +
k2r_1 : (127:0)
PHT
PHT
PHT
PHT
SIGNAL out_42 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_19 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_27 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_11 : std_logic_vector(7 DOWNTO 0)
DeclarationsPorts:
Diagram Signals:
SIGNAL c_10 : std_logic_vector(7 DOWNTO 0)
round_output : std_logic_vector(127 DOWNTO 0)pass : std_logicround_input : std_logic_vector(127 DOWNTO 0)k2r_1 : std_logic_vector(127 DOWNTO 0)k2r : std_logic_vector(127 DOWNTO 0)
clk : std_logicgo : std_logic
RST : std_logic
SIGNAL Result : std_logic_vector(7 downto 0)SIGNAL Result_1 : std_logic_vector(7 downto 0)SIGNAL c : std_logic_vector(7 downto 0)SIGNAL c_1 : std_logic_vector(7 downto 0)
SIGNAL c_2 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_12 : std_logic_vector(7 DOWNTO 0)SIGNAL c_13 : std_logic_vector(7 DOWNTO 0)SIGNAL c_14 : std_logic_vector(7 DOWNTO 0)SIGNAL c_15 : std_logic_vector(7 DOWNTO 0)SIGNAL c_16 : std_logic_vector(7 DOWNTO 0)SIGNAL c_17 : std_logic_vector(7 DOWNTO 0)SIGNAL c_18 : std_logic_vector(7 DOWNTO 0)SIGNAL c_19 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_20 : std_logic_vector(7 DOWNTO 0)SIGNAL c_21 : std_logic_vector(7 DOWNTO 0)SIGNAL c_22 : std_logic_vector(7 DOWNTO 0)SIGNAL c_23 : std_logic_vector(7 DOWNTO 0)SIGNAL c_24 : std_logic_vector(7 DOWNTO 0)SIGNAL c_25 : std_logic_vector(7 DOWNTO 0)SIGNAL c_26 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_3 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_4 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_5 : std_logic_vector(7 DOWNTO 0)SIGNAL c_6 : std_logic_vector(7 DOWNTO 0)SIGNAL c_7 : std_logic_vector(7 DOWNTO 0)SIGNAL c_8 : std_logic_vector(7 DOWNTO 0)SIGNAL c_9 : std_logic_vector(7 DOWNTO 0)SIGNAL d : std_logic_vector(7 DOWNTO 0)SIGNAL d_1 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_28 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_10 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_29 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_11 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_30 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_12 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_31 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_13 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_32 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_14 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_33 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_15 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_34 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_16 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_35 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_17 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_36 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_18 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_37 : std_logic_vector(7 DOWNTO 0)SIGNAL c_38 : std_logic_vector(7 DOWNTO 0)SIGNAL c_39 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_40 : std_logic_vector(7 DOWNTO 0)SIGNAL c_41 : std_logic_vector(7 DOWNTO 0)
round_control
pass
loge
@+
reg16oct
PHT PHT PHT PHT PHT PHT PHT
PHT PHTPHT
permute
PHT PHT PHT PHT
SIGNAL out_12 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_2 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_3 : std_logic_vector(7 DOWNTO 0)SIGNAL d_4 : std_logic_vector(7 DOWNTO 0)SIGNAL d_5 : std_logic_vector(7 DOWNTO 0)SIGNAL d_6 : std_logic_vector(7 DOWNTO 0)SIGNAL d_7 : std_logic_vector(7 DOWNTO 0)
SIGNAL out0 : std_logic_vector(7 DOWNTO 0)SIGNAL out1 : std_logic_vector(7 DOWNTO 0)
SIGNAL out2 : std_logic_vector(7 DOWNTO 0)SIGNAL out3 : std_logic_vector(7 DOWNTO 0)SIGNAL out4 : std_logic_vector(7 DOWNTO 0)SIGNAL out5 : std_logic_vector(7 DOWNTO 0)SIGNAL out6 : std_logic_vector(7 DOWNTO 0)SIGNAL out7 : std_logic_vector(7 DOWNTO 0)SIGNAL out8 : std_logic_vector(7 DOWNTO 0)SIGNAL out9 : std_logic_vector(7 DOWNTO 0)
SIGNAL out10 : std_logic_vector(7 DOWNTO 0)SIGNAL out11 : std_logic_vector(7 DOWNTO 0)SIGNAL out12 : std_logic_vector(7 DOWNTO 0)SIGNAL out13 : std_logic_vector(7 DOWNTO 0)SIGNAL out14 : std_logic_vector(7 DOWNTO 0)SIGNAL out15 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_8 : std_logic_vector(7 DOWNTO 0)SIGNAL d_9 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_1 : std_logic_vector(7 DOWNTO 0)SIGNAL out_10 : std_logic_vector(7 DOWNTO 0)SIGNAL out_11 : std_logic_vector(7 DOWNTO 0)
SIGNAL d_20 : std_logic_vector(7 DOWNTO 0)SIGNAL d_21 : std_logic_vector(7 DOWNTO 0)SIGNAL d_22 : std_logic_vector(7 DOWNTO 0)SIGNAL d_23 : std_logic_vector(7 DOWNTO 0)
SIGNAL out16 : std_logic_vector(7 DOWNTO 0)
SIGNAL input : std_logic_vector(15 DOWNTO 0)
SIGNAL out_2 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_3 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_4 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_13 : std_logic_vector(7 DOWNTO 0)SIGNAL out_14 : std_logic_vector(7 DOWNTO 0)SIGNAL out_15 : std_logic_vector(7 DOWNTO 0)SIGNAL out_16 : std_logic_vector(7 DOWNTO 0)SIGNAL out_17 : std_logic_vector(7 downto 0)SIGNAL out_18 : std_logic_vector(7 downto 0)SIGNAL out_19 : std_logic_vector(7 downto 0)
SIGNAL out_20 : std_logic_vector(7 downto 0)SIGNAL out_21 : std_logic_vector(7 downto 0)SIGNAL out_22 : std_logic_vector(7 downto 0)SIGNAL out_23 : std_logic_vector(7 downto 0)SIGNAL out_24 : std_logic_vector(7 downto 0)SIGNAL out_25 : std_logic_vector(7 downto 0)SIGNAL out_26 : std_logic_vector(7 downto 0)SIGNAL out_27 : std_logic_vector(7 downto 0)SIGNAL out_28 : std_logic_vector(7 downto 0)SIGNAL out_29 : std_logic_vector(7 downto 0)
SIGNAL out_30 : std_logic_vector(7 downto 0)SIGNAL out_31 : std_logic_vector(7 downto 0)SIGNAL out_32 : std_logic_vector(7 downto 0)SIGNAL out_33 : std_logic_vector(7 DOWNTO 0)SIGNAL out_34 : std_logic_vector(7 DOWNTO 0)SIGNAL out_35 : std_logic_vector(7 DOWNTO 0)SIGNAL out_36 : std_logic_vector(7 DOWNTO 0)SIGNAL out_37 : std_logic_vector(7 DOWNTO 0)SIGNAL out_38 : std_logic_vector(7 DOWNTO 0)SIGNAL out_39 : std_logic_vector(7 DOWNTO 0)
SIGNAL out_40 : std_logic_vector(7 DOWNTO 0)SIGNAL out_41 : std_logic_vector(7 DOWNTO 0)
PHT PHT PHT
permute
PHT PHT PHT PHT
PHT PHT PHT
permute
PHT PHT PHT PHT
by Sameh Assem on 14 2001 يوليو
A single round of the SAFER+ algorithm
Project2001/round/struct
round_output : (127:0)
Package List
ieee std_logic_1164 ieee std_logic_arith ieee std_logic_unsigned
Title:
Path:
Edited:
Bluetooth SecurityICL Project:
This is used in the implementation of both Ar and Ar'
k2r : (127:0)
SIGNAL out_5 : std_logic_vector(7 DOWNTO 0)SIGNAL out_6 : std_logic_vector(7 DOWNTO 0)SIGNAL out_7 : std_logic_vector(7 DOWNTO 0)SIGNAL out_8 : std_logic_vector(7 DOWNTO 0)SIGNAL out_9 : std_logic_vector(7 DOWNTO 0)
SIGNAL sel : std_logic_vector(2 DOWNTO 0)
SIGNAL out_43 : std_logic_vector(7 DOWNTO 0)SIGNAL out_44 : std_logic_vector(7 DOWNTO 0)SIGNAL out_45 : std_logic_vector(7 DOWNTO 0)SIGNAL out_46 : std_logic_vector(7 DOWNTO 0)SIGNAL out_47 : std_logic_vector(7 DOWNTO 0)
SIGNAL output_2 : std_logic_vector(15 DOWNTO 0)SIGNAL output_1 : std_logic_vector(15 DOWNTO 0)SIGNAL output : std_logic_vector(15 DOWNTO 0)
SAFER+ Encryption RoundSAFER+ Encryption Round
Combinational
PHT
PHT
PHT
PHT
+
e
@
SIGNAL out_11 : std_logic_vector(7 downto 0)
SIGNAL c_42 : std_logic_vector(7 downto 0)
SIGNAL c_15 : std_logic_vector(7 downto 0)
DeclarationsPorts:
Diagram Signals:
SIGNAL c_10 : std_logic_vector(7 downto 0)SIGNAL c_11 : std_logic_vector(7 downto 0)SIGNAL c_12 : std_logic_vector(7 downto 0)SIGNAL c_13 : std_logic_vector(7 downto 0)SIGNAL c_14 : std_logic_vector(7 downto 0)
round_input : std_logic_vector(127 DOWNTO 0)round_output : std_logic_vector(127 DOWNTO 0)
k2r_1 : std_logic_vector(127 DOWNTO 0)k2r : std_logic_vector(127 DOWNTO 0)
SIGNAL c : std_logic_vector(7 downto 0)SIGNAL c_1 : std_logic_vector(7 downto 0)
SIGNAL Result : std_logic_vector(7 downto 0)SIGNAL Result_1 : std_logic_vector(7 downto 0)
SIGNAL Result_2 : std_logic_vector(7 downto 0)SIGNAL Result_3 : std_logic_vector(7 downto 0)SIGNAL Result_4 : std_logic_vector(7 downto 0)SIGNAL Result_5 : std_logic_vector(7 downto 0)SIGNAL Result_6 : std_logic_vector(7 downto 0)SIGNAL Result_7 : std_logic_vector(7 downto 0)SIGNAL Result_8 : std_logic_vector(7 downto 0)SIGNAL Result_9 : std_logic_vector(7 downto 0)
SIGNAL Result_10 : std_logic_vector(7 downto 0)SIGNAL Result_11 : std_logic_vector(7 downto 0)SIGNAL Result_12 : std_logic_vector(7 downto 0)SIGNAL Result_13 : std_logic_vector(7 downto 0)SIGNAL Result_14 : std_logic_vector(7 downto 0)SIGNAL Result_15 : std_logic_vector(7 downto 0)
SIGNAL c_2 : std_logic_vector(7 downto 0)
SIGNAL c_3 : std_logic_vector(7 downto 0)
SIGNAL c_4 : std_logic_vector(7 downto 0)
SIGNAL c_16 : std_logic_vector(7 downto 0)SIGNAL c_17 : std_logic_vector(7 downto 0)SIGNAL c_18 : std_logic_vector(7 DOWNTO 0)SIGNAL c_19 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_20 : std_logic_vector(7 DOWNTO 0)SIGNAL c_21 : std_logic_vector(7 DOWNTO 0)SIGNAL c_22 : std_logic_vector(7 DOWNTO 0)SIGNAL c_23 : std_logic_vector(7 DOWNTO 0)SIGNAL c_24 : std_logic_vector(7 DOWNTO 0)SIGNAL c_25 : std_logic_vector(7 DOWNTO 0)SIGNAL c_26 : std_logic_vector(7 downto 0)SIGNAL c_27 : std_logic_vector(7 downto 0)SIGNAL c_28 : std_logic_vector(7 downto 0)SIGNAL c_29 : std_logic_vector(7 downto 0)
SIGNAL c_30 : std_logic_vector(7 downto 0)SIGNAL c_31 : std_logic_vector(7 downto 0)SIGNAL c_32 : std_logic_vector(7 downto 0)SIGNAL c_33 : std_logic_vector(7 downto 0)SIGNAL c_34 : std_logic_vector(7 downto 0)SIGNAL c_35 : std_logic_vector(7 downto 0)SIGNAL c_36 : std_logic_vector(7 downto 0)SIGNAL c_37 : std_logic_vector(7 downto 0)SIGNAL c_38 : std_logic_vector(7 downto 0)SIGNAL c_39 : std_logic_vector(7 downto 0)
SIGNAL c_40 : std_logic_vector(7 downto 0)SIGNAL c_41 : std_logic_vector(7 downto 0)
PHT
PHT PHT PHT PHT PHT PHT PHT
log
@
e
+
log
+
e
@
e
@
+ @ @ + +
round_input
e
@
log
+ +
log e
@ +
log
@@ + + @
e
@
e
@+
log
+
log
+
log
+@ + @@
PHTPHT
permute
PHT
permute
PHT PHT PHT
SIGNAL d_2 : std_logic_vector(7 DOWNTO 0)
SIGNAL c_5 : std_logic_vector(7 downto 0)
SIGNAL c_6 : std_logic_vector(7 downto 0)SIGNAL c_7 : std_logic_vector(7 downto 0)SIGNAL c_8 : std_logic_vector(7 downto 0)SIGNAL c_9 : std_logic_vector(7 downto 0)SIGNAL d : std_logic_vector(7 DOWNTO 0)SIGNAL d_1 : std_logic_vector(7 DOWNTO 0)SIGNAL d_10 : std_logic_vector(7 downto 0)SIGNAL d_11 : std_logic_vector(7 downto 0)SIGNAL d_12 : std_logic_vector(7 downto 0)SIGNAL d_13 : std_logic_vector(7 downto 0)SIGNAL d_14 : std_logic_vector(7 downto 0)SIGNAL d_15 : std_logic_vector(7 downto 0)SIGNAL d_16 : std_logic_vector(7 downto 0)SIGNAL d_17 : std_logic_vector(7 downto 0)SIGNAL d_18 : std_logic_vector(7 downto 0)SIGNAL d_19 : std_logic_vector(7 downto 0)
SIGNAL c_43 : std_logic_vector(7 downto 0)SIGNAL c_44 : std_logic_vector(7 downto 0)SIGNAL c_45 : std_logic_vector(7 downto 0)SIGNAL c_46 : std_logic_vector(7 downto 0)SIGNAL c_47 : std_logic_vector(7 downto 0)SIGNAL c_48 : std_logic_vector(7 downto 0)SIGNAL c_49 : std_logic_vector(7 downto 0)
SIGNAL c_50 : std_logic_vector(7 downto 0)SIGNAL c_51 : std_logic_vector(7 downto 0)SIGNAL c_52 : std_logic_vector(7 downto 0)SIGNAL c_53 : std_logic_vector(7 downto 0)SIGNAL c_54 : std_logic_vector(7 downto 0)SIGNAL c_55 : std_logic_vector(7 downto 0)
SIGNAL d_3 : std_logic_vector(7 DOWNTO 0)SIGNAL d_4 : std_logic_vector(7 DOWNTO 0)SIGNAL d_5 : std_logic_vector(7 DOWNTO 0)SIGNAL d_6 : std_logic_vector(7 DOWNTO 0)SIGNAL d_7 : std_logic_vector(7 DOWNTO 0)
SIGNAL out0 : std_logic_vector(7 downto 0)SIGNAL out1 : std_logic_vector(7 downto 0)
SIGNAL out2 : std_logic_vector(7 downto 0)SIGNAL out3 : std_logic_vector(7 downto 0)SIGNAL out4 : std_logic_vector(7 downto 0)SIGNAL out5 : std_logic_vector(7 downto 0)SIGNAL out6 : std_logic_vector(7 downto 0)SIGNAL out7 : std_logic_vector(7 downto 0)SIGNAL out8 : std_logic_vector(7 downto 0)SIGNAL out9 : std_logic_vector(7 downto 0)
SIGNAL out10 : std_logic_vector(7 downto 0)SIGNAL out11 : std_logic_vector(7 downto 0)SIGNAL out12 : std_logic_vector(7 downto 0)SIGNAL out13 : std_logic_vector(7 downto 0)SIGNAL out14 : std_logic_vector(7 downto 0)SIGNAL out15 : std_logic_vector(7 downto 0)
SIGNAL d_8 : std_logic_vector(7 downto 0)SIGNAL d_9 : std_logic_vector(7 downto 0)
SIGNAL out_1 : std_logic_vector(7 downto 0)SIGNAL out_10 : std_logic_vector(7 downto 0)
SIGNAL d_20 : std_logic_vector(7 downto 0)SIGNAL d_21 : std_logic_vector(7 downto 0)SIGNAL d_22 : std_logic_vector(7 downto 0)SIGNAL d_23 : std_logic_vector(7 downto 0)
by Sameh Assem on 14 2001 يوليو
A single round of the SAFER+ algorithm
Project2001b/round/round_arch
PHT
PHT
PHTPHT
PHT PHT
PHT
permute
PHT PHTPHT
PHT PHT PHT PHT
Package List
ieee std_logic_1164 ieee std_logic_arith ieee std_logic_unsigned
Title:
Path:
Edited:
Bluetooth SecurityICL Project:
This is used in the implementation of both Ar and Ar'
round_output
k2r_1
k2r
SIGNAL out_2 : std_logic_vector(7 downto 0)
SIGNAL out_3 : std_logic_vector(7 downto 0)
SIGNAL out_4 : std_logic_vector(7 downto 0)SIGNAL out_5 : std_logic_vector(7 downto 0)SIGNAL out_6 : std_logic_vector(7 downto 0)SIGNAL out_7 : std_logic_vector(7 downto 0)SIGNAL out_8 : std_logic_vector(7 downto 0)SIGNAL out_9 : std_logic_vector(7 downto 0)
SIGNAL out_12 : std_logic_vector(7 downto 0)SIGNAL out_13 : std_logic_vector(7 downto 0)SIGNAL out_14 : std_logic_vector(7 downto 0)SIGNAL out_15 : std_logic_vector(7 downto 0)SIGNAL out_16 : std_logic_vector(7 downto 0)SIGNAL out_17 : std_logic_vector(7 downto 0)SIGNAL out_18 : std_logic_vector(7 downto 0)SIGNAL out_19 : std_logic_vector(7 downto 0)
SIGNAL out_20 : std_logic_vector(7 downto 0)SIGNAL out_21 : std_logic_vector(7 downto 0)SIGNAL out_22 : std_logic_vector(7 downto 0)SIGNAL out_23 : std_logic_vector(7 downto 0)SIGNAL out_24 : std_logic_vector(7 downto 0)SIGNAL out_25 : std_logic_vector(7 downto 0)SIGNAL out_26 : std_logic_vector(7 downto 0)SIGNAL out_27 : std_logic_vector(7 downto 0)SIGNAL out_28 : std_logic_vector(7 downto 0)SIGNAL out_29 : std_logic_vector(7 downto 0)
SIGNAL out_30 : std_logic_vector(7 downto 0)SIGNAL out_31 : std_logic_vector(7 downto 0)SIGNAL out_32 : std_logic_vector(7 downto 0)
16 – July - 2001
8/16Authentication & Key Generation
Introduction Encryption Security core ASIC/FPGA
GUI MATLAB GUI MATLAB program for simulationprogram for simulation
16 – July - 2001
9/16Encryption
CL26
BD_ADDR
E0
KEY
RES
DATA
Package List
ieee std_logic_1164 ieee std_logic_arith
Declarations
•Input Shuffling (confusion and diffusion)Input Shuffling (confusion and diffusion)
•Summation Stream Cipher (Massey - Rueppel)Summation Stream Cipher (Massey - Rueppel)
Encryption EngineEncryption Engine
Introduction Auth. & Key gen. Security core ASIC/FPGA
16 – July - 2001
10/16 Encryption
P 2 5
Z 9 4Z 9 5Load_reg
P a n e l0
DATA
P222 : (1:55)P444 : (1:55)
concat 55_1 concat 49
P333 : (1:49)concat 49
P111 : (1:49)
concat 55_2
P 2 2 2 : (1 :5 5 ) P 111
Z 11 9 Z 11 9
IN IT
IN IT
Z
Z
Z 1 2 5Z 1 2 5
Z 1 2 6
Z 1 2 7Z 1 2 8 Z 1 2 8
Z 1 2 7Z 1 2 6
Z 1 2 0Z 1 2 1
Z 1 2 2Z 1 2 3Z 1 2 4
Z 1 2 1
Z 1 2 4
Z 1 2 3Z 1 2 2
Z 1 2 0
Z 1 0 6
Z 1 0 7Z 1 0 7
Z 11 2
Z 11 3Z 11 3
Z 11 4Z 11 5
Z 11 6Z 11 7
Z 11 8Z 11 8
Z 11 7
Z 11 6Z 11 5
Z 11 4
Z 1 0 8
Z 1 0 9Z 11 0
Z 111Z 11 2
Z 111Z 11 0
Z 1 0 9Z 1 0 8
Z 1 0 0Z 1 0 1 Z 1 0 1
Z 1 0 2Z 1 0 3
Z 1 0 4Z 1 0 5
Z 1 0 4Z 1 0 3
Z 1 0 2
Z 1 0 6Z 1 0 5
Z 9 5Z 9 6
Z 9 7Z 9 8Z 9 9
Z 9 7
Z 1 0 0Z 9 9
Z 9 8
Z 9 6
IN IT
Q : (7:0)
INIT
CLK_IN
L o a d _ re g
Z 4 6 Z 4 6
IN P U T _ 2 5
SR55 IN P U T _ 3 1
L o a d _ re g
SR49C L K _ IN
SR49C L K _ IN
C L K _ IN
L o a d _ re g
IN P U T _ 3 3
Z 7 0Z 7 1
Z 7 0
SR128
Z 8 2Z 8 3
Z 8 2
Z 8 8Z 8 8
Z 8 9Z 8 9Z 9 0
Z 9 1Z 9 2
Z 9 3Z 9 4
Z 9 3Z 9 2
Z 9 1Z 9 0
Z 8 3
Z 8 4Z 8 5
Z 8 6Z 8 7 Z 8 7
Z 8 6Z 8 5
Z 8 4
Z 7 6Z 7 7
Z 7 6
Z 7 7Z 7 8
Z 7 9Z 8 0
Z 8 1
Z 8 0
Z 7 9Z 7 8
Z 8 1
Z 7 1
Z 7 2Z 7 3Z 7 4
Z 7 5
Z 7 2
Z 7 5Z 7 4
Z 7 3
Z 5 8 Z 5 8
Z 6 4 Z 6 4
Z 6 5Z 6 6Z 6 7
Z 6 8Z 6 9 Z 6 9
Z 6 8Z 6 7
Z 6 6Z 6 5
Z 5 9Z 6 0
Z 6 1Z 6 2
Z 6 3Z 6 3
Z 6 2
Z 6 1Z 6 0
Z 5 9
Z 5 2Z 5 2
Z 5 3
Z 5 4Z 5 5
Z 5 6Z 5 7
Z 5 6Z 5 5
Z 5 4Z 5 3
Z 5 7
Z 4 7Z 4 8
Z 4 9Z 5 0Z 5 1
Z 4 8
Z 4 7
Z 5 1
Z 5 0Z 4 9
SR55 IN P U T _ 3 9
Z 2 1
Z 2 2Z 2 2
Z 3 3Z 3 4
Z 3 4
Z 3 9
Z 4 0Z 4 0
Z 4 1Z 4 2
Z 4 3Z 4 4
Z 4 5Z 4 5
Z 4 4
Z 4 3Z 4 2
Z 4 1
Z 3 5
Z 3 6Z 3 7
Z 3 8Z 3 9
Z 3 8Z 3 7
Z 3 6Z 3 5
Z 2 7Z 2 8 Z 2 8
Z 2 9Z 3 0
Z 3 1Z 3 2
Z 3 3Z 3 2
Z 3 1Z 3 0
Z 2 9
Z 2 3
Z 2 4Z 2 5Z 2 6
Z 2 4Z 2 3
Z 2 7Z 2 6
Z 2 5
Z 9Z 1 0
Z 9
Z 1 5Z 1 6Z 1 6
Z 1 7
Z 1 8Z 1 9
Z 2 0
Z 1 7Z 1 8
Z 1 9Z 2 0
Z 2 1
Z 1 0
Z 11Z 1 2
Z 1 3Z 1 4
Z 1 5Z 1 4
Z 1 3Z 1 2
Z 11
C L KC L K _ IN Z 3Z 4
Z 3
Z 4Z 5
Z 6Z 7
Z 8Z 8
Z 7
Z 6Z 5
Z 1
Z 2Z 2
Z 1
FB3
FB2P a c k a g e L is t
ie e e s td _ lo g ic _ 11 6 4
ie e e s td _ lo g ic _ a rith
D e c la ra tio n s
counterQ : (7 :0 )
IN IT
fsmF B 1
F B 2
F B 3
F B 4
Q : (7 :0 )
IN IT
C L K _ c o u n te r
C
L O A D
C L K _ IN
FB1
FB4
C L K _ IN
C L K
P 1 P 2F B 2 5
IN 2 5 LFSR25L O A D
P 1 0 P 11 P 1 2 P 1 3P 1 4 P 1 5 P 1 6 P 1 7 P 1 8 P 1 9 P 2 0 P 2 1P 2 2 P 2 3 P 2 4P 3 P 4 P 5 P 6 P 7 P 8 P 9
X 2 4
IN IT
L O A D IN IT
C
LOAD
En_CLK_C
O U T P U T
CLK_IN
CLK_Enable
CLK
E N
IN P U T
C L K
E n _ C L K _ C
C L K _ IN E N
IN P U T
O U T P U T
LFSR39P 2 3
P 1 2
LFSR31P 1 P 1 0P 11 P 1 2 P 1 3 P 1 4 P 1 5 P 1 6 P 1 7 P 1 8P 1 9P 2 P 2 0 P 2 1 P 2 2 P 2 3 P 2 4 P 2 5P 3 P 4 P 5 P 6 P 7 P 8 P 9 P 2 6P 2 7 P 2 8 P 2 9 P 3 0 P 3 1F B 3 1
C L K
IN 3 1
L O A D IN IT
C L K _ IN L O A D IN IT
X 2 4
C L K L O A D
P 1 P 1 0 P 11P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 9F B 3 3
IN 3 3IN IT
L O A DC L K _ IN IN IT
LFSR33P 1 3P 1 4 P 1 5 P 1 6 P 1 7 P 1 8 P 1 9 P 2 0 P 2 1P 2 2 P 2 3 P 2 4 P 2 5 P 2 6 P 2 7 P 2 8 P 2 9P 3 0 P 3 1 P 3 2 P 3 3
X 3 2
C L K L O A D
P 1 P 1 0 P 11 P 1 2 P 1 3 P 1 4 P 1 5 P 1 6 P 1 7P 1 8 P 1 9P 2 P 2 0 P 2 1 P 2 2P 3 P 4 P 5 P 6 P 7 P 8 P 9F B 3 9
IN 3 9IN IT
IN IT
Xt3
Xt2
Xt1Z
Ct(0)
P 2 4 P 2 5P 2 6 P 2 7 P 2 8 P 2 9 P 3 0 P 3 1 P 3 2 P 3 3
X 3 2
P 3 4 P 3 5 P 3 6 P 3 7 P 3 8 P 3 9
XORING5x 1
x 2
x 3
Z
Xt4
c 0
x 4
XORINGR E S
C L K _ IN
b : (1 :0 ) C tt : (1 :0 )
S : (1 :0 )
C tt : (1 :0 )
CLK_C
DELAY
T1
Ct : (1:0)
C
C t : (1 :0 )
Ct
C L K _ C
Ct(0)
X 1X t1
DELAY T2
C t0
C t1
S 2
o u tp u t_ 5 : (1 :0 )
S (0 )
Ct(1) a : (1 :0 )
b : (1 :0 )
b _ 1 : (1 :0 )
ADDER1
X 2
X 3
X 4
Y t0
Y t1
Y t2
X t2
X t3
X t4
ADD2
S 3
Y t0
Y t1
Y t2
Y t0
Y t1
Y t2
S (1 )
XORING2
S : (1 :0 )
Block DiagramBlock Diagram
Introduction Auth. & Key gen. Security core ASIC/FPGA
16 – July - 2001
11/16 Security Core
cl26 : (25:0)
security
rst
data_inrand_inkey_in
Declarations
key_out
sres_outdata_outrand_out
Package List
ieee std_logic_1164 ieee std_logic_arith
Features:Features:•Key generation : EKey generation : E2121, E, E2222, E, E33
•Authentication : EAuthentication : E11
•Encryption : EEncryption : E00
•Built in PRNG : 128 bitsBuilt in PRNG : 128 bits•Built in S/P & P/SBuilt in S/P & P/S•Built in ControllerBuilt in Controller
load_key key_in
algo_out(47:40) : (127:0)a lgo_out(39:32) : (127:0)a lgo_out(31:24) : (127:0)a lgo_out(23:16) : (127:0)a lgo_out(15:8) : (127:0)a lgo_out(7 :0) : (127:0)
cl26 : (25:0)
Load_reg
data_in
data_out
SIGNAL ADDR_REG : std_logic_vector(48 DOWNTO 1)
Pac k age L is t
ieee s td_ log ic _1164 ieee s td_ log ic _ari th
Bluetooth Sec uri tyFoE - ASU - ICL
by Ahmed Abd-El -Hameed and Sameh As s em on 25-6-2001
Pro jec t:
The Sec uri ty Eng ineTi tle :
Path :
Th is engine is c apable o f performing the func tions o f a lgori thms E0,E1,E21,E22 and E3 together wi th a ps eudo-random number generator
Pro jec t2001/s ec uri ty /s truc t
Ed i ted:
DeclarationsPorts:
Diagram Signals:
out_start : std_logic
clk : std_logic
rst : std_logic
key_out : STD_LOGIC
sres_out : std_logic
SIGNAL ACO_REG : STD_LOGIC_VECTOR(96 DOWNTO 1)
data_out : std_logic
data_in : std_logic
rand_in : STD_LOGIC
rand_out : std_logic
load_adr : std_logic
rand_start : std_logic
load_key : std_logic
key_in : STD_LOGICen_fb : STD_LOGIC
adda_pin : std_logicaddb : std_logic
e_select : std_logic_vector(2 DOWNTO 0)
cl26 : std_logic_vector(25 DOWNTO 0)
SIGNAL KEY_REG : STD_LOGIC_VECTOR(128 DOWNTO 1)
SIGNAL ad_PIN_COFu : std_logic_vector(47 DOWNTO 0)
SIGNAL bdadb_COFl : std_logic_vector(47 DOWNTO 0)
SIGNAL B1 : STD_LOGIC_VECTOR(48 DOWNTO 1)
SIGNAL CLK_ADDR_REG : std_logic
SIGNAL algo_out : std_logic_vector(127 DOWNTO 0)
SIGNAL E_type : std_logic_vector(1 downto 0)SIGNAL INIT : std_logic
SIGNAL CLK_Enable : std_logic
SIGNAL Load_reg : std_logic
SIGNAL C1 : std_logic
SIGNAL start_algo : std_logic
SIGNAL ClK_RNG : std_logicSIGNAL EN : std_logic
SIGNAL CLK_REG128 : std_logic
SIGNAL OUTPUT : std_logic
SIGNAL RAND : std_logic_vector(128 downto 1)
SIGNAL key_change : std_logic
SIGNAL Q : std_logic
KEY_REG : (128:1)
SAVE_KEY
CLK
D
c lkout_s tart
CLK
CLK_REG128
c lk
key_outKEY_OUT_SR
CLK
KEY_OUT
KEY_READY
Q
KEY_REG : (128:1)
c lk
RNGRAND : (128:1)
EN_FB
REG_128
GET_KEY : (128:1)
KEY_REG : (128:1)
KEY_IN
en_fb
RAND_IN
RST
RAND_OUT
rs t
KEY_REG : (128:1)
Q
ClK
c lk
ClK_RNGRAND : (128:1)
rst
algo_out : (127:0)
a lgo_out : (127:0)
rs tk ey : (127:0)
Rand : (127:0)
k ey _c hange
rs t
k ey _c hange
RNGcontrol
RST
algo_out(127:96) : (127:0)
EN
rs t
s tart_a lgo
algorithme_ty pe : (1 :0)
c lk
end_algo
s tart_a lgo
out_s tart
c lk SRES_SRCLK
SRES_IN : (32:1)
SRES_OUT
SRES_READY
c lk
ADDR_SR ADDR_SRe_select : (2:0)
controller
E_ty pe : (1 :0)
RST
s tart_a lgo
E_ty pe : (1 :0)
s tart_a lgo
ACO_REG : (48:1)
ACO_REG(48:1) : (96:1)
ACO_ADDR : (48:1)
ADDR_REG : (48:1)
C1
ACO_ADDR : (48:1)
ACO_REG : (48:1)ADDR_REG : (48:1)
C1
ad_PIN_COFu : (47:0) bdadb_COFl : (47:0)
ad_PIN_COFu : (47:0)bdadb_COFl : (47:0)
C1
ACO_REG(96:49) : (96:1)
REG96 SAVE_ACO
algo_out(95:0) : (127:0)
ACO_REG : (96:1)
ADDR_REG : (48:1)ADDR_REG : (48:1)
B1 : (48:1)ADDR_REG : (48:1)
C1
CLK_Enable
E_s e lec t : (2 :0)
en_fb
end_algo
INIT
load_adr
load_k ey
RAND_s tart
INIT
CLK_Enable
C1
out_s tart
load_adr
load_k ey
en_fb
addA_PIN_addB
c lk load_adrc lk
addA_PIN_addBCLK CLK
CLK_ADDR_REG OUTPUT algo_out : (127:0)
a lgo_out(127:120) : (127:0)a lgo_out(119:112) : (127:0)a lgo_out(111:104) : (127:0)a lgo_out(103:96) : (127:0)a lgo_out(95:88) : (127:0)a lgo_out(87:80) : (127:0)a lgo_out(79:72) : (127:0)a lgo_out(71:64) : (127:0)a lgo_out(63:56) : (127:0)a lgo_out(55:48) : (127:0)
DATA
out_start
out_s tart
rand_out
sres_out
rand_in
en_fb
rand_start
CLK
Load_reg
clk
E0
ADDR_REG : (48:1)
ADDR_REG(48:41) : (48:1)ADDR_REG(40:33) : (48:1)ADDR_REG(32:25) : (48:1)ADDR_REG(24:17) : (48:1)ADDR_REG(16:9) : (48:1)ADDR_REG(8:1) : (48:1)
CLK
c lk c l26(25) : (25:0)c l26(24) : (25:0)c l26(23:16) : (25:0)c l26(15:8) : (25:0)c l26(7 :4) : (25:0)c l26(3 :0) : (25:0)
adda_pin
load_adr
addb
Pseudo-Random Number Generator
Proposed DesignProposed Design
Introduction Auth. & Key gen. Encryption ASIC/FPGA
16 – July - 2001
12/16
ASIC/FPGA
ASIC/FPGA
Back AnnotationBack Annotation
All Controls
E0control
algo_control
controller
safer_control
Declarations
Diagram Signals:
INIT : std_logic
CLK : std_logic
SIGNAL dash : std_logic
go : std_logic
RST : std_logic
done : std_logicend_algo : std_logic
start_algo : std_logic
E_type : std_logic_vector(1 DOWNTO 0)
y : std_logicz : std_logic
s0 : std_logics1 : std_logic
int : std_logic
FB1 : std_logicFB2 : std_logicFB3 : std_logicFB4 : std_logic
LOAD : std_logic
C : std_logic
En_CLK_C : std_logic
CLK_Enable : std_logic
Load_reg : std_logic
load_adr : std_logicload_key : std_logic
en_fb : std_logic
RAND_start : std_logic
C1 : std_logic
E_select : std_logic_vector(2 downto 0)
sel_round : std_logic_vector(2 DOWNTO 0)sel_safer : std_logic_vector(2 DOWNTO 0)
Package List
ieee std_logic_1164 ieee std_logic_arith
Ports:
<company name>
by Sameh Assem on 14 2001 يوليو
<enter diagram title here>
Project2001/all_controls/struct
round_control
Title:
Path:
Edited:
<enter project name here>Project:
<enter comments here>
SIGNAL pass : std_logic
CL26
BD_ADDR
E0
KEY
RES
DATA
Package List
ieee std_logic_1164 ieee std_logic_arith
Declarations
(Modified)
S10PC84
Introduction Auth. & Key gen. Encryption Security core
16 – July - 2001
13/16
ASIC/FPGA
ASIC/FPGA
FPGA testsFPGA tests
Introduction Auth. & Key gen. Encryption Security core
16 – July - 2001
14/16 ASIC/FPGA
FPGA ReportsFPGA Reports
***************************************************Device Utilization for S10PC84***************************************************Resource Used Avail Utilization---------------------------------------------------IOs 32 61 52.46%FG Function Generators 233 392 59.44%H Function Generators 7 196 3.57%CLB Flip Flops 294 392 75.00%---------------------------------------------------Clock Frequency Report
Clock : Frequency ---------------------------------------------CLK : 55.3 MHz
S10PC84
EncryptionEncryption EngineEngine
Number of ports : 45Total accumulated area : Number of Dffs or Latches : 2553 Number of Function Generators : 4948 Number of MUX CARRYs : 1006 Number of MUXF5 : 367 Number of MUXF6 : 110 Number of gates : 4752***************************************************Device Utilization for v1000fg680***************************************************Resource Used Avail Utilization---------------------------------------------------IOs 45 512 8.79%Function Generators 4948 24576 20.13%CLB Slices 2474 12288 20.13%Dffs or Latches 2553 24576 10.39%---------------------------------------------------Clock : Frequency---------------------------------------------------clk : 66.2 MHz
V1000FG680
SecuritySecurityCoreCore
Introduction Auth. & Key gen. Encryption Security core
16 – July - 2001
15/16 ASIC/FPGA
ASIC flowASIC flow
AMS 0.6 µm technologyDouble metal layersSingle poly
Core Area: 12.04 mmCore Area: 12.04 mm22
Introduction Auth. & Key gen. Encryption Security core
16 – July - 2001
16/16