AN-559

AID CONVERSION SERIES - PART 2

IA SINGLE RAMP

ANALOG- TO-DIGITAL CONVERTER

Prepared by

Jim Barnes

A simple single ramp AID converter which incorporatesa calibration cycle to insure an accuracy of 12 bits isdiscussed. The circuit uses standard ICs and requires onlyone precision part - the reference voltage used in thecalibration. This converter is useful in a number of instru-mentation and measurement applications.

MOTOROLA Semiconductor Products Inc.

INTRODUCTION

The current trend towards digital readout, both in labo-ratory test equipment and in industrial instrumentationhas created a large demand for simple but accurate analog-to-digital (A/D) converters. However, the two words"simple" and "accurate" are usually contradictory; simpleconverters usually are not accurate.

As an aid to understanding the range of accuraciesavailable in A/D converters, three general categories ofaccuracy might be identified; 2 to 6 bits, 6 to 10 bits, andgreater than 10 bits. The lowest category, with accuracyup to about I %, can be attained by most of the simpleschemes. Digital panel meters usually fall in this class. Thesecond class, 6 to 10 bits, with an accuracy up to 0.1 %requires a more sophisticated approach and is representedby 3-1/2 digit digital volt meters (DVM). The final classwhich includes 4 and 5 digit DVMs and precision instru-mentation, is the subject of this note.

Probably the simplest, and certainly the easiest to under-stand of the available A/D designs, is the single rampconverter. This converter generates a time gate signal

SweepVoltageInput V

UnknownVoltageInput

whose length is proportional to the unknown analogvoltage. This gate allows a series of oscillator clock pulsesto pass in to a counter. The number of pulses passed isproportional to the length of the gate pulse. These clockpulses are converted to a digital number in whatever codeis desired: Binary, BCD, gray, or other.

The simple converter suffers from several inaccuracies;the voltage-to-time converter may be non-linear, its startingtime and stopping time may be uncertain or it may havethe wrong transfer gain. The clock pulse generator mayintroduce inaccuracies if it is too fast, too slow, or variesin frequency with time.

The following sections describe a method of correctingall these inaccuracies, except the non-linearity of thevoltage-to-time converter. [n brief, a known analog inputis measured and the resulting digital number is comparedto the correct answer. If this digital number is not correct,the converter is automatically adjusted so that the correctanswer will be produced. This calibration cycle is inter-laced with cycles which measure the unknown analogvoltage, thereby providing compensation for all but the

Digital

Output

RampCompoOutput

Circuit diagrams external to Motorola products are included as a means of illustrating typical semiconductor applications; consequently,complete information sufficient for construction purposes is not necessarily given. The information in this AppJication Note has been care-fully checked and is believed to be entirely reliable. However, no responsibility is assumedfor inaccuracies. Furthermore, such informationdoes not convey to the purchaser of the semiconductor devices described any license under the patent rights of Motorola Inc. or others.

most rapid variations in converter accuracy. The knowninput must, of course, be as accurate as the desired meas-urements. The explanation also describes a method whichsenses input signal polarity.

THEORY OF OPERATIONThe ramp type AID converter uses a linearly rising

voltage ramp to convert an unknown voltage to an equiva-lent time interval. This time interval is used to gate aportion of the output of a clock-oscillator. The cyclesof the oscillator which are passed by the time gate consti-tute a digital number proportional in value to the unknownvoltage. The train of pulses is normally converted to amore usable number system such as binary, BCD, gray,etc. Figure I shows the single ramp AID converter in asimple form. In general, some time is required for recoveryof the ramp after each use, as well as for whatever digitaloperations that may be required to produce the type ofdigital word desired. Therefore, timing gates are requiredto separate the various operations. Figure l(a) includes asimple arrangement to accomplish the desired gating, andFigure I(b) shows typical waveshapes. Operation of thevarious components shown on the block diagram will nowbe described.

The ramp generator consists of an operational amplifierwith a capacitor in the feedback path. The input is froma constant sweep voltage through a resistor. Because theoperational amplifier input terminal remains at virtualground, the current through the resistor is constant. Thiscurrent is available to charge the capacitor, resulting in alinear ramp voltage. It is important that the ramp belinear, because this is the only significant source of errornot corrected by the calibration cycle used in the AIDconverter described in this note.

UnknownVoltageInput

SweepVoltageInput

-"-V

TimingInterval

GatedClock

The comparator is also a high gain amplifier. Wheneverinput (2) is more positive than input (1), the comparatoroutput is high, otherwise the output is low. The clockand gate generators are oscillators which produce the wave-forms indicated. The "AND" gate has a positive outputwhenever all its inputs are positive, a zero output otherwise.

The coder may take various forms; for example, ifbinary code output is desired, the coder is a binary counter.

This simple type of AID converter works extremely wellif only a few bits of accuracy is required. However, asmore accuracy is demanded, various errors begin to becomeapparent. The follOWing paragraphs discuss these errorsand describe a particular configuration which uses severaltechniques to reduce their effect.

There are two types of ramp errors (other than non-linearities); those related to slope, and those related tostarting time. If the ramp starts late, fewer than the correctnumber of counts will be included. If the slope of theramp is too steep, it will reach the unknown voltage toosoon and fewer than the correct pulse count will beincluded. Comparator voltage offset and delay have aneffect similar to errors in ramp starting time. If the rampvoltage must exceed the unknown voltage by a givenamount to change the state of the comparator, the gatewill close late and too many counts will be included. Like-wise, comparator propagation delay will cause too manycounts to be indicated for a similar reason. Taking theabove errors in order; variations in ramp slope are causedby variations in the sweep voltage V, input resistance R,capacitance C, and to a much smaller extent, non-idealparameters of the op amp B, and the reset switch A.Variations in ramp start time are caused by changes in theoffset voltage and delay time of operational amplifier B.

It is desirable to employ some means of assuring thatramp delay errors be small, and react predictably toenvironmental variations. A frequently-used method is tostart the ramp below the zero reference voltage as shownin Figure 2. Then the timing gate is opened by the rampcrossing the zero reference and closed by its crossing theunknown voltage. The two crossings are detected byidentical comparator circuits and should therefore trackeach other well. Delays and non-linearities associated withramp start-up are also eliminated by this technique. Onesmall problem is created by this technique: It is verydifficult to synchronize the clock with the opening of thetiming gate because the gate opening is an analog eventnot related to the clock. This non-synchronization canresult in a 1/2 least significant bit (LSB) error if the gatingoccurs during the rise time of the clock. With practicalclock speeds and standard logic families, this error willoccur less than I% of the time.

The clock frequilncy, of course, has the same effect oncount correctness as does ramp slope - if the clock is tooslow it will not produce a sufficient number of pulsesduring the gate interval. Variations in clock frequency canbe made small by use of a crystal or other high Q frequencydetermining device.

The previous discussions indicate tha t even if the counteris gated perfectly, there are still at least two factors whichcan cause errors; improper ramp slope and improper clockfrequency. As mentioned previously, these are closelyrelated because too fast a clock or too shallow a rampslope both result in too many counts being gated. There-fore, if the clock frequency could be controlled, it couldbe used to compensate not only for its own drift, butalso for ramp slope errors. (An alternate method wouldbe to control the ramp slope.) Oscillator frequency canvery easily be controlled if it is known what frequency isrequired. One way of determining the required frequencyis by trial and error. The known analog voltage is convertedto a digital number and the resultant output is observed.

SweepVoltageInput

ReferenceVoltageInput

(1/2 full scale)

Unknown 9Vo Itage o-----JInput

IIIIIIL _

If the output indication is too high, the clock could beslowed down and vice versa. Figure 3 shows a blockdiagram of such a calibration scheme. The voltage refer-ence has been selected to be exactly half the full scalevalue of the converter. In a binary counter, the mostsignificant bit is switched only under one condition, andthis is at exactly half the full-scale count. This fact isutilized as will be seen later and is the main reasoncalibration of a binary system is done at the half-scale value.

If BCD counters are used, the MSB normally goes toa "one" at the count of 8 and returns to a "zero" at 10.In this case, calibration would be done at 80% of full scalerather than 50%.

In operation, the comparator is switched alternativelybetween the unknown voltage and the reference voltage.The MSB of the binary output is decoded so that it can bedetermined if the oscillator frequency is too high or toolow. This decoded output, is converted to a bipolar devoltage, and used to control the oscillator frequency.Because this calibration output can, at most, be available25% of the time (and in the instrument shown here isavailable a much smaller percentage of the time), a meansmust be provided to store the value when it is not presentat the decoder output. In the system shown, an integratingoperational amplifier is used in a sample and hold circuit.

The capacitor and charging resistor values are selectedso that the voltage resulting from an error will correct theoscillator frequency by an amount corresponding to aboutLSB/4. The benefit of using the most significant bit (MSB)is that its decoding always proVides the proper error sense,even when large errors are present. This is true becausethe MSB only changes state once at half of the full count.

Figure 4 shows the waveshapes generated for control ofthe A/D converter. Note that there are alternatingCALIBRATE and MEASURE cycles. A 'RESET pulse isgenerated at the end of each cycle to reset the counters tozero. Just prior to the RESET pulse, another pulse isgenerated. In the calibrate cycle, this is called "Ec" and it

LogicGates&

III Driver I

SamPle/Hold! .J------- -...- - -----

is used to gate the error signal into the sample-and-holdcircuit. In the MEASURE cycle this pulse is calledDISPLA Y ENABLE and is used to latch the digital equiva-lent of the unknown analog voltage into the output display.

The error voltage changes rapidly during the "Ec" pulseand remains constant between pulses. With large errors,such as might be present for a few seconds when the unitwas first turned on, a staircase error waveshape would beproduced, but at near zero error, the MSB error decoderoutput will be toggling between a plus and minus value toproduce a squarewave. This toggling during the calibrationcycle has no real effect on the measuring cycle because theoscillator frequency is only being shifted an amount corre-sponding to LSB/4 which is less than the resolution of theconverter.

This converter, as so far described, cannot distinguishbetween a negative input voltage and zero input. It givesa zero output for either one. To correct this situation,additional circuitry is required. If a zero or negative inputvoltage is applied, we note that during the MEASURE cyclea STOP pulse is generated before or simultaneously withthe START pulse, or in other words: no TIMING GATEis generated. In this event, it is desired that the inputpolarity be reversed with a mechanical relay. If no TIMINGGATE is present during the following MEASURE cycle, aswould be the case with zero input, the input should againbe reversed. Hence, with an exactly zero voltage input,the input switch should be reversed once each cycle, andthe plus and minus sign should likewise alternate at thecycle rate.

The electronics to accomplish the above polarity sensingis implemented as follows: polarity is indicated by a 1-Kflip-flop, S, connected so it will change state every time itreceives a negative going pulse. The TIMING GATE isconnected to its input so that each occurrence of a TIMINGGATE signal will trigger the flip-flop S. Use of the nega-tive edge triggering assures that the flip-flop will not trigger

until the end of the TIMING GATE, i.e., after the measure-ment is completed. Thus this flip-flop triggers when theramp crosses either the unknown or Reference voltage level.

In operation, flip-flop S changes state at the end ofeach measurement of a positive voltage. The TIMINGGATE which is always present during the CALIBRATEcycle (because the reference voltage is always positive)returns the flip-flop S to its original state, ready for the nextmeasurement. However, if the input is negative or zero,only the CALIBRATE cycle TIMING GATE will bepresent, so the state of flip-flop S would alternate foreach cycle.

A second 1-K flip-flop, T, is connected to flip-flop Ssuch that its state is forced to be the same as that of flip-flop S at the time of the DISPLAY ENABLE pulse. Withtwo flip-flops connected in this way, the polarity relay(and readout) will only be activated under the conditionsthat the unknown input is either negative or exactly zerovoltage.

FEASIBILITY MODELA prototype model AID converter was constructed

which utilized all the techniques previously discussed. Thelinear voltage ramp is started at a voltage below groundpotential. Two comparators are used, the first to generatea START signal at the time the ramp crosses zero volts,and the second to generate the STOP signal when the rampcrosses the voltage being measured. Two cycles of oper-ation are used: CALIBRATE and MEASURE. During theCALIBRATE cycle a voltage equal to one-half of full scalevoltage is measured and the resulting count compared tothe known correct count. If the counts are different, theresultant error voltage is used to adjust the clock frequency.

Standard IC operational amplifiers and the MTTL familyof IC digital devices are used in the feasibility model. Fig-ure 5 is the schematic diagram.

The components were assembled on two PC boards, the

Timing

Gate

'-v-' CountComparatorOutputs

DisplayEnableInput

ResetInput

~2000 pf

SweepVoltage·Input

RAMP VOLTAGEGENERATOR

B NegativeOutputVoltage

C

MPS6517A Positive

InputVoltage

ReferenceVoltageInputgnd

UnknownVoltageInput

MLM101A

6

PolarityReversingRelay -=

PolarityPulseOutput (To Relay)

1.0 J.Lf510 k

lrst including all the circuitry of Figure 5(a), and the;econd the circuitry of Figure 5(b), (b) being the basic~/D converter, (a) being the counter and output wordcoder. Components A and B of Figure 5(b) make up theramp generator; the transistor switch, when open, allowsthe ramp to rise. Values are selected so that the rampreaches its maximum value of nearly +15 volts in about3 milliseconds. The resistors connected to the non-invertinginput of the operational amplifier cause the ramp to startbelow 0 volts allowing comparator F to sense the ramplero crossing.

Transistor C is provided on the board to increase theversatility of the circuit. A negative voltage is required:or the SWEEP INPUT. This may be provided from an~xternal source or, by use of the inverter C, may be derivedfrom the positive reference voltage or the +5 volts supply.

Components, D, E, and H are the switches which alter-[late the converter input between the unknown analoginput being measured and the known reference voltage.Comolementary FET switches are used so that the samewa.. pe can be used to control both switches.

I25IJ.f

=2.2 k62 pf

To PolarityFlIp-Flop 12

(T)

Components F and G are the two com"parators whichsense the time when the ramp voltage crosses zero voltsand either the reference voltage or the unknown voltage.Their outputs, in conjunction with component I,gate theappropriate number of clock counts to the output.

The two resistors from the inputs of component I to itsoutput provide positive feedback which eliminates anytendency the gate might have to oscillate because of therather slow pulse transitions from the comparators.

The clock oscillator is an RC multivibrator consistingof transistors K and M. Transistor L is a current sourceused to provide a small degree of isolation from the +15 voltsupply. The potentiometer in the base of transistor L setsthe oscillator operating range, providing a coarse frequencycontrol. Note that use of the previously mentioned alter-nate control system - control of ramp slope rather thanoscillator frequency - would allow use of a simple crossed-gate fixed frequency oscillator.

Overflow(MSB)

0.1 IJ.f

TIMING OSCILLATOR

All the timing gates originate trom the oscillator whichis one half of component P. Flip-flops Rand Q providesuitable frequency divisions, while gates I and 0 supplythe various gates shown in Figure 4.

The last remaining circuit, made up of operationalamplifier N and parts of the gate circuit 0, is the sampleand hold circuit used to generate the error control signalwhich is the principal advantage of this type of AID con-verter. The s~nse determining signal; the most significantbit in a binary counter or the overflow from the lastdecade of a BCD counter, gates the input to either theinverting or the non-inverting input of operational amplifierN. The other gated signal, called Ec, is a pulse, generatedonly during the calibrate cycle, which occurs after thecalibrate count has settled, but just prior to counter reset.The two 2 pF capacitors hold the error signal constantexcept during the Ec gate, and also in conjunction with thetwo input resistors, determine the amplitude of error signalgenerated when either input is gated on. These valueswere selected so that the full range of about + 15 volts to-15 volts is covered in about 10 seconds. The two 51 knresistors which couple this error voltage into the voltagecontrolled clock oscillator are selected to provide a ±2.5%frequency range for full error voltage excursion. Thiscircuit could be simplified slightly if a fixed bias wereapplied to this amplifier to cause a slow tuning rate inone direction. Errors in the opposite direction wouldreverse this rate, allowing the required control function.

The circuitry of Figure 5(a) was made up using threeMC7493 binary counters and an MC7473 J-K flip-flop tosense incorrect input polarity. Note that the J and K inputsof the first flip-flop are connected to the Q output of theramp gate flip-flop (component R). This disables the firstpolarity flip-flop at the time the two comparators arereturning to their rest condition, eliminating any possibilityof a spurious trigger at that time. The RESET and COUNTinputs were connected as indicated, while the most signifi-cant bit, or 12th count was brought out to generate theerror signal. The polarity signal was also brought out toindicate the sign of the input. The following data wasobtained primarily with this output circuitry, although a4 digit decade output circuit, with latches, 7-segmentdecoders, and LED digit readouts was used briefly.

The following values were measured:

Clock Oscillator FrequencyGate Oscillator FrequencyClock Tuning RangeTuning Voltage RangeVeO-SensitivityDigital WordCorrection Increment

2MHz1.3 kHz+2.5% or ±SO kHz±15 V3.3 kHz/V12 Bits122 Hz or 36 mV/Ec(amplitude corresponds toLSB/4+10 V+5 V1.024 ms

Full Scale ReadingCalibrate VoltageCalibrate Time

Sweep Time (ramp) 3.1 msOverrange 1.052 ms or 50%Correction Rate 10 Hz/msMaximum Correction Time 10 secondsVoltage Ramp Slope 5 V/ms

The error voltage, i.e., the de voltage applied to theclock VCO, was observed to toggle each calibrate cycle.Occasionally when a power supply transient occurred, twoor three corrections would be made in the same directionindicating a momentary error of 1/2 or 3/4 LSB. Thisindicates that accuracy was almost always within ±LSB/4and peak errors did not exceed +LSB/2.

Only one manual control is used in this circuit, a po-tentiometer, to displace the VCO lock-in range by about±25%. Its adjustment is very non-critical.

The converter was also tested with a 4-1/2 digit BCDcounter and display. The signal used for calibration wasthe 8000 count output (this is the BCD MSB). A referencevoltage of 8.000 volts was used and clock frequency cor-rections were ba~ed on thi~ value. The maximum inputvoltage which could be measured was slightly over 13wllich was limited by the available ramp voltage.

The clock locked at 2.6 MHz, the 8000 counts occurringin 3.0 ms. (Ramp duration had been increased to 5.5 ms.)

Input voltages of 0 to 13 volts in one volt incrementswere applied and the readings compared to a laboratorygrade DVM; average readings agreed within 0.001 V, butsince no input smoothing was used, the reading followednoise on the input voltages. However, when the input wasshorted firmly to ground, a zero reading was obtained. Theinput voltage return, reference voltage return and thegrounded comparator input must all be securely bondedtogether, and isolated from all other return currents tominimize noise problems.

A considerably more refined model of this A/D con-verter was later built as a digital volt meter using a 4 1/2 digitLED readout. Correction was made at the 80% of fullscale point or 8.000 volts. This model incorporated all theoptions previously mentioned.

The first of these options was use of the ramp generatorinstead of the oscillator as the controlled element of thecorrection loop.

As mentioned previously, when BCD counters are usedthe MSB normally goes to "one" at the 80% of full scal:point and back to "zero" at full scale. Therefore, looperrors must never be allowed to become so great that thethe loop might try to lock-up outside this 80 to 100 percent range. To avoid the necessity of precision parts in thelOOP, the potentiometer frequency control of the oscillatoremployed in the previous model was retained. This allowsthe oscillator to be set so that even if the ramp has beendriven by the control voltage to its most shallow slope, nomore than 10,000 clock pulses can reach the counter duringthe calibrate cycle before the ramp reaches the 8 volt ref-erence. The error signal will hence always be of the correctpolarity to drive the ramp up until the proper 8,000 pulses

are reached when the ramp crosses the 8 volt reference, atwhich point the loop locks.

The ramp generator and the integrating amplifier whichprovides the error control voltage are shown in Figure 6(a).

SweepVoltage

he error input to the integrating amplifier is single-ended,i.e., error pulses are supplied only when the gate count istoo high, control in the other direction being provided bya fixed bias as was discussed previously as an option. Withno error pulses the integrated error signal drifts slowlypositive, while with continuous error pulses, it steps morenegative at the same average rate.

Another feature of this model, not previously men-tioned, is the use of the 60 hertz line frequency to syn-chronize the system as shown in Figure 6(b). This improves

60 'V15 Vp/p

the appearance of the display when a digital readout isused, since the voltage under measurement frequently hasa small 60 hertz component. When the sampling rate issynchronized with this "hum", the reading is always takenat the same point in the "hum" waveshape so the last digitis less prone to fluctuate. The actual reading obtained is,of course, the input voltage at this instant and may not bethe RMS value of the input signal plus hum.

Another small difference between this model and theprevious is the use of a potentiometer to vary the offset ofone of the comparators. This forms a zero offset adjust forthe instrument and allows the output to read zero for anon-zero input, a condition sometimes desirable when theinput comes from a transducer. This adjustment allows theuse of a less precise operational amplifier, the MLM 301 A,for the comparators. Figure 6(c) shows the circuit.

Figure 7 shows a photo of a laboratory AID converterof this type.

FromRampGen.

10 k

CONCLUSIONThe application of feedback techniques to the single

ramp AID converter for the purpose of improving its long-term accuracy is very feasible. The model which wasconstructed worked very well, displaying an accuracy ofabout 1 part in 10,000. Advantages of the techniqueinclude simplicity of concept, non-criticalness of com-ponents and extremely good long term accuracy. The onlyprecision element required is the reference voltage; thesystem accuracy is proportional to the referen"ce voltageaccuracy. A further advantage which makes this techniqueunique is: the correction loop may be closed around theentire system (except for the polarity reversing relay). Forexample, if a scaling amplifier is used, this amplifier canbe included in the loop and any variations in its character-istics will be cancelled out.

The speed of the unit constructed was about 85 measure-ments per second. By use of MECL logic this rate could,in principal, be increased to more than 5000 measurementsper second.

APPENDIXThe follOWing paragraphs present a brief examination

of the errors encountered in the AID converter previouslydescribed.

RAMP VOLTAGE ERRORSThe errors to be considered first concern the timing of

the ramp. The ramp voltage, Vr, is expressed by thefollowing equation:

t(Vs - Vio) (Vr - Vio) RCVr= RC +Vio; t= VV'

s 10

where: t = time to reach the ramp voltageVs = sweep voltage

Vio = operational amplifier offset voltageR = charging resistorC = timing capacitor

This ramp voltage is compared, first with zero volts, thenwith the unknown voltage to produce a time interval pro-portional to the magnitude of the unknown voltage. Thetime of zero crossing, to, is:

(Viol - Vio) RCto = V V. + tpis - 10

where: Viol = comparator #1 offset voltagetpi = comparator #1 propagation time

The time of crossing the unknown voltage level is:

(Vu - Vio + Vi02) RCt I = V V. + tp2 (3)s - 10

where: Vu = unknown voltageVi02 = comparator #2 offset voltage

tp2 = comparator #2 propagation time

The desired time interval, 6t, is then obtained by:subtraction:

(Vu + Vi02 - Viol) RC6t=tl-to= Vs-Vio +tp2-tpl (4)

The partial derivitive of this expression is taken with respectto each variable. It is then noted that, for the worst case,

This value is substituted into each partial derivitive togive the values listed in Table I.

TABLE 1 PARTIAL DERIVITIVES

2C2R

RC!Vs2RC!Vs

These values indicate that, for worst case, the gate time issensitive to the three parameters, R, C, and V s in a ratioof 2:1. In other words, if one of these values, such as thesweep voltage Vs varies 10% the time gate (tl - to) willvary 20% (worst case). Because a periodic correction isemployed to remove long term errors, it is only noise onthese quantities which is of interest. Of these, the mostsignificant is noise on the reference voltage. This can intheory be minimized by using proper by-passing pro-

cedures. If thin film resistors are used, resistor noise istypically reduced to 0.1 IlV per volt. Capacitor noise iseven less significant. Ramp timing errors, therefore,compute to be very small.

veo ERRORSThe next series of errors to be considereq are frequency

errors in the voltage controlled oscillator (VCO). In theRC oscillator considered, frequency is controlled byvarying the threshold voltage at which triggering takesplace. This threshold is determined by parameter variationswithin the semiconductor materials from which the devicesare fabricated. Current levels and temperatures are theprincipal influences on the amplitude variation of theseparameters. The current variations are caused, for themost part, by supply voltage variations and can hence becontrolled by suitable regulation. Likewise, the effects oftemperature variations are removed by the periodic cali-brations. However, at any given temperature and curren tlevel, there is still a frequency jitter caused by a combi-na tion of thermal noise in the resistors and semiconductors,and residual supply voltage noise. In the feasibility modeldescribed in the previous paragraphs, this residual noiseresulted in converter errors of about one part in 10,000.

OPERA TING SPEED

The speed of operation of a ramp type AID converteris dependent upon two major factors:

1. The maximum slope of the ramp voltage which isdetermined by the operational amplifier slew ratecapability.

2. The allowable clock rate.Whether one or the other of these two factors is more

critical depends on the number of bits of resolution desiredand the speed of the digital logiC family being used. Togive a specific example, consider an operational amplifierwith a slew rate of 2.5 volts/llS and a logic family with amaximum clock rate of 10 MHz. This amplifier will pro-duce a 15 V ramp in no shorter than 6 IlS. This gate timeinterval will pass 60 clock pulses. To assure 1/2 leastsignificant bit accuracy, twice the number of pulses asthere are bits of resolution must be used. This imposes acritical resolution of 5 bits with 60 clock pulses. If greaterthan 5 bits are required, speed will be limited by theclock speed, while for less than 5 bits, the ramp slew rateplaces a limitation on speed. If a high speed logic family,like M ECL, which allows clock speeds of greater than200 MHz is used, the critical resolution with a 2.5 VIllsramp generator is computed to be 9 bits.

@ MOTOROLA Senliconduc'for Produc'fs Inc.

AN SS9