agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)
Post on 19-Dec-2015
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TRANSCRIPT
![Page 1: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/1.jpg)
![Page 2: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/2.jpg)
Agenda
目標與概述 (purpose)
架構 (structure)
流程 (procedure)
成果 (result)
![Page 3: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/3.jpg)
Purpose
學習目標:學習 VHDL 標準規格與語法,以及相關輔助工具 Xilinx ISE ,並參與教育部大專院校積體電路設計 FPGA 組之比賽。
專題概述:此專題為直角三角形之直角座標轉譯系統,可將直角三角形的三個頂點座標 (x1,y1),(x2,y2),(x3,y3) 轉譯,依續輸出涵蓋於直角三角形平面內的所有座標點。
![Page 4: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/4.jpg)
Structure
虛擬碼:
![Page 5: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/5.jpg)
Procedure
轉譯流程:(1) 設定直角三角形座標。
(2) 基準點從左下角開始,由左至右依序 trace 每個座標點。
(3) 檢查是否超過右邊界,若尚未超過,則將該座標點儲存,若超過則基準點往上 shift 一個單位。
(4) 檢查是否超過上邊界,若尚未超過則持續往右 trace ,若超過則結束 trace ,即完成轉譯。(5) 依序輸出每個座標點。
![Page 6: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/6.jpg)
State Diagram
![Page 7: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/7.jpg)
Code (input/output)
entity triangle is Port (
reset : in STD_LOGIC; clk : in STD_LOGIC; xi : in STD_LOGIC_VECTOR (2 downto 0); yi : in STD_LOGIC_VECTOR (2 downto 0); nt : in STD_LOGIC;
busy : out STD_LOGIC; po : out STD_LOGIC; xo : out STD_LOGIC_VECTOR (2 downto 0); yo : out STD_LOGIC_VECTOR (2 downto 0));
end triangle;
![Page 8: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/8.jpg)
Code when mvr =>
xo <= xc;yo <= yc;po <= '1';xc <= xc + 1;side <= (x2-xc)*(y3-y2)- (yc-y2)*(x2-x3);if side(7)='1' then
xc <= x1;yc <= yc + 1;state_next <= mvu;
end if;
![Page 9: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/9.jpg)
Code (cont.) when mvu =>
xo <= xc;yo <= yc;xc <= xc + 1;side <= (x2-xc)*(y3-y2)- (yc-y2)*(x2-x3);if yc=y3 then
state_next <= stop;elsif side(7)='1' then
xc <= x1;yc <= yc + 1;state_next <= mvu;
elsestate_next <= mvr;
end if;
![Page 10: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/10.jpg)
Result
RTL Schematic Diagram (1) 系統方塊:
![Page 11: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/11.jpg)
Result
RTL Schematic Diagram (2) :
![Page 12: Agenda 目標與概述 (purpose) 架構 (structure) 流程 (procedure) 成果 (result)](https://reader033.vdocuments.mx/reader033/viewer/2022061609/56649d375503460f94a0fd71/html5/thumbnails/12.jpg)
Result
RTL Schematic Diagram (3) :