advanced vlsi chap4-1
TRANSCRIPT
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Topics
Standard cell-based layout.
Channel routing.
Simulation.
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Standard cell structure
VDD
VSS
n tub
p tub
Intra-cell wiring
pullups
pulldowns
pin
pin
Feedthrougharea
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Standard cell design
Pitch: height of cell.
All cells have same pitch, may have different
widths.
VDD, VSS connections are designed to run
through cells.
A feedthrough area may allow wires to berouted over the cell.
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Single-row layout design
Routing channel
cell cell cell cell cell
cellcellcellcellcell
wire Horizontal trackVerti
cal track
height
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Routing channels
Tracks form a grid for routing.
Spacing between tracks is center-to-center
distance between wires.
Track spacing depends on wire layer used.
Different layers are (generally) used for
horizontal and vertical wires.Horizontal and vertical can be routed relatively
independently.
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Routing channel design
Placement of cells determines placement of
pins.
Pin placement determines difficulty of
routing problem.
Density: lower bound on number of
horizontal tracks needed to route thechannel.
Maximum number of nets crossing from one
end of channel to the other.
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Pin placement and routing
before
a b c
b c a
before
a b c
bca
Density = 3 Density = 2
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Example: full adder layout
Two outputs: sum, carry.
sum
carry
x1
x2
n1
n2
n3
n4
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Layout methodology
Generate candidates, evaluate area and
speed.
Can improve candidate without starting fromscratch.
To generate a candidate:
place gates in a row;draw wires between gates and primary
inputs/outputs;
measure channel density.
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
A candidate layout
x1 x2 n1 n2 n3 n4
a
b
c
s
cout
Density = 5
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Improvement strategies
Swap pairs of gates.
Doesnt help here.
Exchange larger groups of cells.
Swapping order of sum and carry groups
doesnt help either.
This seems to be the placement that givesthe lowest channel density.
Cell sizes are fixed, so channel height
determines area.
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Left-edge algorithm
Basic channel routing algorithm.
Assumes one horizontal segment per net.
Sweep pins from left to right:
assign horizontal segment to lowest available
track.
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Example
A B C
A B B C
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Limitations of left-edge
algorithm
Some combinations of nets require more
than one horizontal segment per net.
B A
A B
aligned
?
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Vertical constraints
Aligned pins form vertical constraints.
Wire to lower pin must be on lower track; wire
to upper pin must be above lower pins wire.
B A
A B
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Dogleg wire
A dogleg wire has more than one horizontal
segment.
B A
A B
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Rats nest plot
Can be used to judge placement before final
routing.
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Modern VLSI Design 4e: Chapter 4 Copyright 2008 Wayne Wolf
Types of simulation
Circuit simulation:
analog voltages and currents.
Timing simulation:
simple analog models to provide timing but not
detailed waveforms.
Switch simulation:transistors as semi-ideal switches.
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Types of simulation, contd.
Gate simulation:
logic gates as primitive elements.
Models for gate simulation:
zero delay;
unit delay;
variable delay.
Fault simulation:
models fault propagation (more later).
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Example: switch simulation
a
+
+
b
cd
c
1
0
0
X
X
Xo0
1
1
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Example, contd.
a
+
+
b
cd
c
1
0
0
0
1
1o
0
1
0
0