advanced packaging for 5g and radar application · advanced packaging for 5g and radar application...

© Fraunhofer IIS/EAS

ADVANCED PACKAGING FOR 5G AND RADAR APPLICATION

Andy Heinig, Group Manager Advanced System Integration

Fraunhofer IIS/EAS

© Fraunhofer IIS/EAS | Heinig, Andy | 03.10.2019 2

AGENDA

5G technology and 5G enabled applications

New packaging technologies

Advances and effort

Assembly Design Kit (ADK) enabled EDA flow

Introducing ADK

Introducing EDA flow

System design

Summary


5G Technology

Fifth generation of cellular mobile communications

Speed up to 20 Gbit/s

Various frequencies

Below 6 GHz (similar to 4G/LTE)

24-86 GHz (high bandwidth, but reduced range)

Massive multiple input and multiple output

Real Time Capabilities

Latency below 1ms


5G Enabled Applications: C2C

Car to Car Communication (C2C)

Communication about the speed (harmonize the speed of the cars)

Look „behind the corners“

radioaustralia.net.au

https://www.qosmotec.com/car-2-x-communication/


5G Enabled Applications: C2I

Car to Infrastructure Communication (C2I)

Communication with traffic lights

Communication with/from roadworks

http://www.its.dot.gov/image_gallery/image36.htmhttps://www.kbb.com/car-news/all-the-latest/government-starts-

rulemaking-to-enable-car_to_car-communication/2000010307/


5G Technology

Increasing amount of communication systems due to the

Increase of data rate by C2C, C2I, C2x, etc.

Increase of communication protocols (especially at 5G)

Cumulative utilization of different frequency spectra

Increasing number of antennas due to

Different spectra

Cover different directions Placement on various positions on the vehicle

Beam forming and MIMO applications

Conclusions

To confine the increasing costs by the increasing number of systems and antennas, new integration and fabrication approaches are necessary


Integration Technologies for 60 GHz Antennas

Tri-band application (2.4/5/60 GHz)

System performance:

Maximum Throughput: 4.6 Gbps

Supported Frequencies: 57-66 GHz

Bandwidth: 1.7 GHz (possible up to 9Ghz)

Reference Designs:

External Antenna Module

16 element printed antenna array

Dimensions: 32mm x 8mm

No active beamforming



Large, complex Printed Circuit Board (PCB)

Antennas surrounds Front End Chip

Differential feeding lines (right figure) to feed rectangular patch antenna

16 phased-array antennas (for active beamforming



Easy and cheap mold package (radar applications)

Single Printed Loop Antenna (PLA) or Printed Dipole Antenna (PDA)

Use Mold compound (h>400µm, εr ≈ 3, tanδ ≈ 0.005 @ 77GHz)

Bandwidth ≈ 8GHz

Metal shield is on PCB, not under control of the system owner

Difficult to integrate antenna arrays

1.65mm

0.4 mm

≈ 0.2mm

PDA

PLA

0.91mm


New Packaging TechnologiesAdvances

Movement of passive structures from chip to package (e.g. combiner, splitter, inductors, …)

Reduce silicon cost

Better processes available in the package for RF/HF parts

Less interaction between the components

Multi-chip integration

Processing chip + low power RF-part

Power stage of the RF part

Short path between different components in the RF-path



Stacking of chip and antenna

Bottom part – chip embedded into mold; redistributionlayers

Top part – mold or glass

Allows antenna arrays for MIMO or beamforming

Easy and cheap solution in the future; usage of standardpackage approaches

RF/ Logic chip (face-up)

Antenna module (mold compound)

Molded package

TMV (optional: metallized TH)TMV (Cu pillar)

Shield

Antenna pattern

Antenna module (mold compound )

RDL first


Molded packageRF/ Logic chip (face-down)

Shield

Antenna pattern




RDL first



Shield

Antenna pattern


New Packaging TechnologiesAdvances

Different materials for antenna possible (depends on the requirements e.g. quality of the beam, cost, …)

Glass

Ceramic

Polymers

Organic

Multi-antenna integration

Very short path between chip an antenna especially for the higher number of RF-signals


New Packaging Technologies

But: design is much more complex, more interaction across integration levels

Assembly Design Kit (ADK) enabled EDA flow

Allows overall design

Allows overall design analysis (e.g. comprehensive simulation)

Allows overall optimization

Allows overall DRC

Allows overall LVS


Assembly Design Kit (ADK)

Analog to PDK, but in package and assembly domain

Combine multiple packaging and IC technologies

Design- and manufacturing process getting more comple

ADK bundles packaging and assembly information

Enable Chip-Package and Chip-Package-Board Co-Design

Comprehensive DRC and LVS checking

Optimization across intergration levels



Verified systemSystem specification

3D

Layout data2D

Verification toolSystem integration

Layout toole.g., Virtuoso

Verification tool2D database

e.g., OpenAccess

3D database

MappingNetlists Geometries

ADK

2D PDK



Verified systemSystem specification

Layout data

3D

2D

Verification toole.g., Calibre

System integration

Layout toole.g., Virtuoso

Verification toole.g., Calibre

ADK

PDK


Introducing EDA flowmm-Wave Design Example

Components

RF chip in an advanced IC technology (LVL0)

RDL-first package technology (LVL1)

RDL-last mold technology (LVL2)

RF-Transeiver for 5G 60 GHz

20x20 mm Package

10x10 mm IC

Antenna array on LVL2

Beamforming

RF components on LVL1


RDL first



Shield

Antenna pattern


Introducing EDA flowmm-Wave Design Example

Production samplesAntenna module (mold compound )

RDL first



Shield

Antenna pattern


Introducing EDA flowTraditional Design Flow

Dedicated tooling for each components

Independent implementation

Checking

Manual

Based on Excel


RDL first



Shield

Antenna pattern

IC Design Package LVL2 Design

Package LVL1 Design

Check


Introducing EDA flowADK enabled Design Flow

Common Design Environment

Comprehensive System View

Optimization and cross-relation

Common Design Database

Export Design to

Dedicated Analysis like RF

Optimization

Checking

Design Rules (IC, Package, Assembly)

Layout-vs- Schemativ

Back-annotation of results


RDL first



Shield

Antenna pattern

IC Design Package LVL2 Design

Package LVL1 Design

Common Design Environment

Common Design Database

Analysis

Optimization

Checking


Level0: IC

Level1: RDL-first package

Level2: RDL-last package

Introducing EDA flowComprehensive Design

Custom IC and package design using dedicated design environment


RDL first



Shield

Antenna pattern


Introducing EDA flowMicrowave Analysis

Simulation with Microwave Stdio


Introducing EDA flowChecking

Design rules

proc_pad_align {out = NOT INSIDE proc_pads ip_m1padviol = ENCLOSURE proc_pads ip_m1pad

< 5 OVERLAP REGIONOR out viol

}



}



}

Rule configuration

Chip PDKsChip PDKsChip PDKsIP PDKPackage rules

IP PDKAssembly rules


RDL first



Shield

Antenna pattern


Introducing EDA flowChecking

Layout vs. Schematic

Checking IC

Checking Package LVL1

Checking Package LVL2

BUT: ADK also enables comprehensive checking ofIC, package LVL1 and package LVL2

Multiple ICs from different technologies arepossible


RDL first



Shield

Antenna pattern


Summary

Advanced system integration using new packagetechnologies

But rising requirements from system perspective andtherefore design and validation effort

Introduction of Assembly Design Kits enables

Co-Analysis

Co-Optimization

Design safety

advanced packaging for 5g and radar application · advanced packaging for 5g and radar application...

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