HanbatHanbat

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UniversityUniversityHanbatHanbat

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Advanced Modeling Advanced Modeling Techniques Techniques

Advanced Modeling Advanced Modeling Techniques Techniques

Gookyi Dennis N. A. Gookyi Dennis N. A.

SoC Design Lab.SoC Design Lab.

July.15.2014

ContentsContents Delay Modules Timing Checks

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Delay ModelsDelay Models There are three delay models that are often used to

model various delays hardware module:Distributed delay modelLumped delay modelPath delay model

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Distributed Delay ModelDistributed Delay Model In this model delays are associated with an individual

element, gate, cell or interconnect An example is shown below:

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Distributed Delay ModelDistributed Delay Model Code and waveform

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Distributed Delay ModelDistributed Delay Model RTL schematic

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Lumped Delay modelLumped Delay model Delays are associated with the entire module The cumulative delay of all paths are lumped at the

single output An example is shown below:

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Lumped Delay modelLumped Delay model Code and waveform

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Lumped Delay modelLumped Delay model RTL schematic

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Path Delay ModelPath Delay Model Delays are individually assigned to each module path Path delay is specified on a pin-to-pin (port-to-port)

basis

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Specify BlocksSpecify Blocks The specify block is a mechanism for providing the

following functionsDescribe various paths across the moduleAssign delays to these pathsPerform necessary timing checks

Its general form is as follows:specify

path_declarationspecparam_declarationtiming_checks

endspecify

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Specify BlocksSpecify Blocks An example using module path delays

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Specify BlocksSpecify Blocks Code and waveform

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Path DeclarationPath Declaration There are three kinds of path declarations that can

be declared within a specify:Simple pathEdge-sensitive pathState-dependent path

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Simple PathSimple Path It simply construct a path from a path source to a

path destination It can be declared in one of the following forms:

Parallel connectionFull connection

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Parallel ConnectionParallel Connection It uses the symbol => and every path source

connects to exactly one path destination It has the following form:

source => destination = delay_value;

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Full ConnectionFull Connection Uses the symbol *> and every path source connects

to all path destination Its syntax is as follows: source *> destination =delay_value

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Full ConnectionFull Connection Code and waveform

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State Dependent PathState Dependent Path In actual hardware module, the module path delays

might be changed when the states of input signals to the circuit changes

The module path delay can be assigned conditionally, based on the value of the signals in the circuit

The general form is as follows:if (cond_expr) simple_path_declarationif (cond_expr) edge_sensitive_path_declarationifnone simple_path_declaration

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State Dependent PathState Dependent Path The timing of NOR gate

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State Dependent PathState Dependent Path

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Testbench and waveform

Specparam DeclarationSpecparam Declaration It is used to define specify parameters which are

intended to provide timing and delay It has the general form as below:

specparam [range] specparam_assignment;

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Specparam DeclarationSpecparam Declaration The timing of NOR gate

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Specparam DeclarationSpecparam Declaration Waveform

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Timing ChecksTiming Checks In Verilog, a set of functions is provided for timing

checks All checks must be inside the specify blocks The most commonly used timing checks include:

$setup$hold$setuphold$width$skew$period$recovery

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Setup time checkSetup time check Setup time is the amount of time that data must be

stable before they are sampled The general form is as follows:

$setup (data_event, reference_event, limit); Violation is reported when:

t_reference_event – t_data_event < limit An example is shown below:

specify$setup (data, posedge clock, 3);endspecify

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Hold Time CheckHold Time Check It is the amount of time that data must continually

remain stable after they have been sampled It has the general form as below:

$hold (reference_event, data_event, limit) Violation is reported when:

t_data_event – t_reference_event < limit An example is shown below:

specify$hold (posedge clock, data, 3);endspecify

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Pulse Width CheckPulse Width Check Checks to see whether the width of a pulse meets the

minimum width requirement It has the following form:

$width (reference_event, limit); Violation is reported when:

t_data_event – t_reference_event < limit An example is shown below:

specify $width (posedge reset, 10);endspecify

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Period CheckPeriod Check This is used to check whether the period of a signal

meets the minimum period requirement It has the general form as below:

$period (reference_event, limit); Violation is reported when:

t_data_event – t_reference_event < limit An example is shown below:

specify$period (posedge clk, 25)endspecify

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Timing ChecksTiming Checks An example is a d-ff with timing checks The simulator will report errors when the timing

relationship between the inputs clk, d and reset_n violates any specification on the timing checks: $setup, $hold, $period

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Timing ChecksTiming Checks Code

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Timing ChecksTiming Checks Testbench

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Timing ChecksTiming Checks Simulation results

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Analyzing Simulation ResultsAnalyzing Simulation Results From 0 to 10 time units, there are no violations

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Analyzing Simulation ResultsAnalyzing Simulation Results After 10ns, the period is violated t_data – t_reference <

limit

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Analyzing Simulation ResultsAnalyzing Simulation Results After 20ns, there are three violations

SetupPeriodHold

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Analyzing Simulation ResultsAnalyzing Simulation Results Setup violation t_reference_event – t_data_event <

limit

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Analyzing Simulation ResultsAnalyzing Simulation Results Period violation t_data – t_reference < limit

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Analyzing Simulation ResultsAnalyzing Simulation Results Hold violation t_data_event – t_reference_event <

limit

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