Prime: National Renewable Energy Laboratory ---------------------------

Additively Manufactured Photovoltaic Inverter (AMPVI)

Motherboard

Stacked Daughterboards

Integrated Heat Sink

Auxiliary Power

Digital Controller (Optional to Power Block)

Air In

Air Out

DCSide

ACSide

Gate Driver

Protection

Measurements

SiC Power Poles

Communications

Auxiliary Power Source

Film Cap

1

Principal Investigator: Dr. Sudipta Chakraborty Contributors: Dr. Madhu Chinthavali and ORNL team; Dr. Scott Sudhoff and Purdue team; Dr. Mariko Shirazi, Dr. Kumaraguru Prabakar, Dr. James Cale, Kevin Bennion, Dr. Feng Xuhui

Presented at DOE workshop on Enabling High-Penetration Solar PV through

Next-Generation Power Electronic Technologies Golden, CO

October 11, 2016

Project Objective §  To enable integration of hundreds of GWs of solar generation to the

U.S. electric power system, this project will develop a unique PV inverter design that combines high-voltage Silicon Carbide (SiC) with revolutionary concepts such as additive manufacturing and multi-objective magnetic design optimization

§  The final deliverables from the project will include: a)  High power density (>100W/in3), high efficiency (>98%) power block

and 50 kW prototype inverter

b)  Additive manufacturing techniques for power block and heat sink

c)  Magnetic design optimization tool

d)  A versatile controller

e)  Standard HIL inverter testing techniques

f)  Cost and reliability analysis of SiC based PV inverter

2

SunShot PE Target Metrics

3

Project Technical Approach

Superior Switches

1700 V SiC MOSFET

Novel Packaging

Additive Manufacturing

Economies of Scale

Power Block Architecture

Flexible Control & Comm.

Mother & Daughterboard

Optimized Magnetics

Multi-objective Optimization

Superior Inverter Design

Holistic Approach

PHIL Testing

System Validation

Current State

4

AMPVI&

η&>&98%&

Life&>&25&yrs.&

Interoperable&

Cost&<&$0.125/W&

Grid&support&FuncIons&

Power&Density&>&100W/in3&

Project Technical Approach

5

Integrated Heat Sink

Auxiliary Power

Digital Controller (Optional to Power Block)

Air In

Air Out

DCSide

ACSide

Gate Driver

Protection

Measurements

SiC Power Poles

Communications

Auxiliary Power Source

Film Cap

Power&modules&

DC.bus&capacitors&Busbars,&Lead&frame&

Sensors&

Controller&PCB&

Gate&driver&PCB&

Heatsink&

Electromagnetic Analysis

Solid Body Analysis

Change Parameter

Change Geometry Geometry

R,L,C

Device Loss

Device Temp.

Program and Data Flow

Electrical Circuit Analysis

Thermal Analysis

Temperatures

EMI

Results

Control

feasible

objective

space

f1(x)(minimize)

f2(x)(minimize)x2

x1

feasible

decision

space Pareto-optimal frontB

C

Pareto-optimal solutions

A

feasible

objective

space

feasible

objective

space

f1(x)(minimize)

f2(x)(minimize)x2

x1

feasible

decision

space

x2

x1

feasible

decision

space Pareto-optimal frontPareto-optimal frontBBB

CCC

Pareto-optimal solutionsPareto-optimal solutions

AA

Motherboard

Stacked Daughterboards

PV Simulator

or DC Source Reduced-order

Distribution Model

AC Grid Simulator

Real-time SimulatorInverter Current Measurements

Voltage Commands

AMPVISub

Topology& Controller&

AM.based&Power&Block&

MagneDc&Design&

Thermal&and&Mechanical&Design&&

System.level&ValidaDon&

Economies of Scale

6

AM-based Power Block with 1700V SiC MOSFETs and Diodes

7

3D Printed Heatsink

Dynamic Characterization of SiC MOSFET

Fabricated All-SiC Module

Switch Package Phase-leg Module with Cooling

System

Phase-leg Module with Cooling System and DC Capacitors

Three-phase Power Block

Gate Driver Board

Thermal Analysis

Power Block Assembly

§  The switching performance of the SiC module is evaluated through a high voltage double pulse test setup

8

Power Block – Testing

SiC power module Universal gate driver

Overcurrent protection Load inductor

§  Power stage with high voltage (>2000V DC) and current capability (>20A RMS)

§  Embedded solid-state circuit breaker for fast and reliable overcurrent protection

§  Preliminary test: 700V dc bus voltage and 55A load current

§  Excellent turn-on switching behavior; moderate turn-off ringing due to non-optimized external power loop connection

Time scale: (2 µs/div)

Drain-Source Voltage (400 V/div)

Gate Voltage (20 V/div)

Drain-Source Current (30 A/div)

turn off turn on

Initial Test Results for SiC Module

Inductor Design Using Multi-Objective Optimization

9

Multi-Objective Design Methodology

AMPVI Circuit Topology

Evolutionary Computing for MO Design

Example: AC Inductor Design

10

Integrated Analysis Magnetic – MEC Thermal – TEC Losses AC resistive losses (skin effect) Proximity effect loss Core loss (hysteresis + eddy)

Constraints Geometry/bending radius Aspect ratio Mass/Loss Current density Inductance (and variation) Cross-inductance Peak wind. temperature Objectives (minimize) Volume Loss

Inverter Side Current

t, s

i aLi

, A

10

Pareto-Optimal Front

Y-Core AC Inductor Top View Profile View

Controller

11

NI 9607�

NI 9683�Controller�

ORNL Gate Driver Board�

Power Module�

Interface Board�

Control Algorithms and Simulation Validation

4-Quadrant Operation Grid-tied Current Control

Advanced Functions (VVAR, FWATT, Ride through, AI etc.)

SBRIO: Xilinx Zynq-7000, 667 MHz dual-core ARM Cortex-A9 processor, an Artix-7 FPGA, and a mezzanine card connector

Controller Hardware and Interface

Controller Hardware-in-the-Loop (CHIL)

12

CHIL Experimental Setup Pure Simulation

CHIL Results Controller(

(SBRIO+GPIC)(Real(4me(simulator(

Real(4me((simulator(GUI(

SBRIO(GUI(

Scope(

SBRIO&real&+me&layer&

Advanced&inverter&func+ons&

SBRIO&&FPGA&layer&

PWM&signals&

Real&+me&simulator&

Inverter&model&

Current&command&

Feedbacks& Feedbacks&

PWM,&trip&signals&

•  V,&I,&f&•  Alarms&•  CB&Status&

•  Instantaneous&V,I&

CHIL System Architecture

Component Layout (Alpha-prototype)

13

Ø  Components are grouped into three thermal subsystems : 1: DC capacitors, DC current and voltage sensors II: power block, LCL filters III: Control board, AC current and voltage sensors

Ø  Subsystem II has largest heat loads and therefore becomes the main focus in thermal design Ø  The inverter designed volume is 1378 in3, yielding a power density of approximately 36 W/in3

Packaging

Define  Component  Thermal  Specifications

Define  System  Thermal  Specifications

Identify  Component  Layout  Requirements

Establish  Thermal  Management  Subsystem  Performance  Metrics

Select  System  Package  and  Thermal  

Management  Design

Identify  Thermal  Subsystem  Technologies

Perform  System  PackagingDesign  Meets  Specifications  and  Targets

No

yes

Thermal Design Process

14

Air Temperature Distribution

Evaluation of Thermal Design Sample Mesh

•  Heat exchanger is modeled as a porous media within ANSYS

•  Parameters are defined to match the desired pressure drop versus flow of the specified heat exchanger

Preliminary CFD Simulations

AMPVI Design Process Flow

15

Inverter Design

ControllerMagnetics Power Block

AMPVI

Power Hardware

Switch Package and Power Module

Common Mode Filter

AC Filter Design

Inverter Validation

Harmonics, Losses, P, V, I, PD

Harmonics, η, PD, P, V, I

η, P, Harmonics, PD

Grid support functions,

Interoperable, PD

ΔIdc

fs

fs

Thermal limits Mechanical data

Thermal limits, Mechanical data η, PD, Operational limit

Thermal limits, Mechanical data

Validation feedback Validation feedback

Validation feedback

Control Algorithm

Testing & ValidationTesting & Validation CHIL Validation

Verification

System PHIL Validation (in BP 3)

System level design inputsInter-subsystem dependencySubsystem design stepsSystem validation feedback to sub-systems

Power Testing

Control Hardware

Stakeholder Engagement

16

§  Technology advisory panel (TAP) –  Getting industry feedback and building industry interest in developed

technologies for future commercialization

–  TAP was formed and currently have four members Solectria, Unified Power, National Instruments, Semikron USA

• Semikron  • NI  

• Rohm?  • Solectria  • Unified  Power  

Inverter  Manufacturer  

Chip  Manufacturer  

Power  Stage  Packaging  

Controller  Manufacturer  

§  1-hour call in every 3 months

§  No travel requirement

§  Typically be at high level without discussing any detailed technology or IPs

§  May need to sign a multi-party NDA if detailed technologies discussed

Acknowledgements

17

§  This work was supported by the U.S. Department of Energy under Contract No. DE-AC36-08-GO28308 with the National Renewable Energy Laboratory

§  We gratefully acknowledge the support of Dr. Guohui Yuan

and his SunShot Systems Integration team for funding this work….

§  And this workshop.

Thank You!!