adc-dac-ppt

Lecture 9

Today: Basics of A/D and D/A.

Spartan3 analog I/O and DDS.

Digilent family boards.

Handouts: Printed copy of today’s lecture slides.

Read: VHDL materials on handouts web page

References: Pedroni, data sheets, etc.

Please keep the lab clean and organized.

Last one out should close the lab door!!!!

Nothing is more difficult, and therefore more precious, than to be able to decide.— Napoleon I.

EECS 452 – Fall 2009 Lecture 9 – /59 Mon 9/28/2009

This week’s reminders

◮ HW 3b due this Wednesday.

◮ HWs 2 and 3 due this Friday.

◮ Project team formation and topic selection next Wed night.


ADC and DAC

ADC (analog to digital converter) and DAC (digital to analog converter)

are two critical elements in most digital systems.

◮ We will take a look at the basic idea behind these.

◮ We will introduce the A/D and D/A on S3SB and other related IO.

◮ You will get to practice these in Lab 4.

What do you do when you have an analog waveform?

◮ Discretize it in time: sampling or time quantization.

◮ Discretize it in value/amplitude: quantization or amplitude

quantization.

What do you do when you have a sequence of discrete numbers?

◮ Reverse quantization: assign real value to each quantile

◮ Reverse sampling: interpolation (reconstruction)


Visualize sampling & reconstruction

0 0.2 0.4 0.6 0.8 1

x 10−3

−1

−0.5

0

0.5

1Analog waveform

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plit

ud

e

0 0.2 0.4 0.6 0.8 1

x 10−3

−1

−0.5

0

0.5

1Time quantized waveform

am

plit

ud

e

0 0.2 0.4 0.6 0.8 1

x 10−3

−1

−0.5

0

0.5

1Reconstructed time quantized waveform

am

plit

ud

e

time in seconds

Analog waveform.

Discretize in time:

sampling using

ADC.

Reconstruct: zero

order hold.


Comments on sampling

◮ Given a real valued lowpass spectrum with bandwidth BW (zero

to null), the sampling frequency 2BW is often called the Nyquist

sampling rate/frequency.

◮ There is good reason behind this. You may recall from 216

and/or 451.◮ We will take another more realistic look at this in another

two lectures.

◮ In practice one often should sample at a rate of at least two or

three times the Nyquist sampling rate.

◮ It is also common practice to take the analog signal through an

antialias filter before sampling.

◮ We will see more details on this later, but this is basically a

low pass filter to get rid of high frequency components in

the analog signal.◮ The AIC23 used on the C5510 DSK has built in antialias

filters. The cutoff frequencies change with the selected

sampling rate.


Interesting audio frequencies

Many waveforms can have energy beyond a band of interest.

Voice: fundamental around 150 Hz, overtones to about 5 kHz.

male fundamental about 120 Hz.

female fundamental about 200 Hz.

bass low E is 82.4 Hz.

soprano high C is 1,046.5 Hz.

Piano: 27.5 Hz (A0) to 4816 Hz (C8).

Normal young adult hearing range is 20 Hz to 20,000 Hz.

Telephone nominally passes range 300 Hz to 3200 Hz.


Common sampling rates

Common sampling rates:

standard telephone system 8 kHz

wideband telecommunications 16 kHz

home music CDs 44.1 kHz

professional audio 48 kHz

DVDAudio 192 kHz

instrumentation, RF, video extremely fast


Most common A/D techniques

There are several additional ways in which the conversion of an

analog waveform into a series of numbers can be implemented.

Pencil and paper.

Dual slope integration.

Successive approximation.

R2R resistive ladders.

charge redistribution.

Flash.

Deltasigma (DSP systems in their own right).


Successive approximation A/D

Sampling: uses a track

and hold to capture a

voltage on a capacitor.

Quantization: uses a

local voltage reference

bits of a D/A converter;

they are successively

switched so as to match

the D/A output to the

captured voltage.

High speed, high MHz is possible. Common accuracies range

from 8 to 16 bits.

Successive approximation converters can also be pipelined to

develop a few bits at a time as values pass through the pipeline.

This provides high speed at the cost of a small of delay.

Figure from Atmel AD023 data sheet.


Flash A/D (1/2)

Multiple comparators:

determine all bits at the

same time. VERY fast.

Note that there is no

explicit sampling, but

the comparators are

controlled by clock tics.

What is the output for

reference 4V and input

2.5?

How many possible out

put values?


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Basic idea is to save bandwidth by sending the changes (often encoded

using a single bit) in a waveform rather than the full waveform. Samples

very fast. Exploits the cheap availability and small size of today’s digital

logic. More details to come in a later lecture.


Going from voltages to numbers

Consider a Bbit A/D converter. Two common mappings

from voltages to numbers are:

Offset Binary.

Most negative value is 0.

Most positive value is 2B − 1.

Two’s Complement.

Most negative value is −2B−1.

Most positive value is 2B−1 − 1.

To convert between the two formats, invert the most significant

bit.


Two’s complement scaling

Given a Bbit A/D output value:

most positive value is 2B−1 − 1,

most negative value is −2B−1.

Note that these limits are slightly asymmetric.

Usually place zero volts mid input step. This will be seen to

give zero DC offset with a zero DC input.

Assume a maximum input voltage excursion of ±Vp

Assign voltage −Vp to −2B−1.

Voltage step size per count change is ∆V = Vp/2B−1

for uniform quantization.

Often write ∆V simply as ∆ and refer to it as a quanta. That is,

the voltage change required for a increment of one in the A/D

converter output value.


Uniform quantization

−1 −0.75 −0.5 −0.25 0 0.25 0.5 0.75 1

−8

−6

−4

−2

0

2

4

6

8

Qua

nize

r in

tege

r ou

tput

Quantizer analog input level

4−bit linear quantizer input to output transfer function

Converts analog voltages into Bbit

numbers.

Change in number by 1 is one

quanta.

One quanta change ↔ one ∆ voltage

change.

∆ = Vp/2B−1

Usually place A/D bits into com

puter word most significant bits.

Note the placement of the zero

input relative to the output count.

Plot’s xaxis is normalized.


Nonuniform quantization: mulaw companding

COMpression and exPANDing of digitized waveforms (companding).

◮ Originally developed for use in digital parts of the telephone

system.

◮ International Telecommunication Union ITUT

Recommendation G.711.

◮ Idea: progressive taxation

◮ Instead of using equal step sizes, use smaller steps for small

input values.◮ Why? What if you have a weak signal?


µlaw transfer function

How to implement?

◮ Idea one: come up with unequal step sizes for the entire range.

◮ idea two: let’s skew the signal instead.

◮ “stretch” the small values and “compress” the large values.◮ Now apply a uniform quantizer.◮ This has an equivalent effect of assigning small steps when

input is small, and large steps when input is large.

y = Qµ

(

sgn(x)ln(1+ µ|x|/V)

ln(1+ µ)

)

, µ = 255.

V normalizes the input signal.

◮ Implemented as logarithmic fixedpoint number sign, 3bit.

◮ characteristic and 4bit mantissa (8bit code word).

◮ Performance roughly equivalent to 14bit uniform (linear)

encoding.


A/D converter worries

The real world seems to always get in the way.

Offset Error

Gain Error

Differential Nonlinearity (DNL) Error

Integral Nonlinearity (INL) Error

Absolute Accuracy (Total) Error

Aperture Error

A good reference is TI’s Understanding Data Converters, SLAA013,

July 1995.


Errors introduced in A/D

Now let’s take a look at the amount of error we introduce in the

process of A/D.

◮ We know if we don’t sample fast enough we get into trouble;

details to come later.

◮ In quantization and encoding, analog values (uncountably infinite)

are converted into a finite number of values. Information is lost.

◮ Digital values are most often represented using binary

words.◮ Common A/D word sizes are 8, 10, 12, 14, 16 and 24 bits.◮ A word having B bits can represent 2B numeric values.◮ The more A/D bits the greater the quality of the sampled

data.


Quantizer model and assumptions

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◮ The quantization errors are

uniformly distributed over the

range from −∆/2 to ∆/2.

◮ The quantization errors are

independent of the waveform

being quantized.

◮ Quantization error values are

independent of each other. This

leads to the concept of a white

spectrum.

◮ The statistics of the

quantization errors are wide

sense stationary. A wide sense

stationary random process is

one whose first and second

moments are time invariant and

whose autocorrelation function

is invariant to time shift.


Uniformly quantized sinewave and error

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

−1

−0.5

0

0.5

1

Am

plitu

de

Sinewave period

Sinewave quantized using 4−bits

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

−1

−0.5

0

0.5

1

Qua

nta

Sinewave period

Sinewave quantization error using 4−bit quantizer


Really?

Do You Really Expect Me to Believe Those Assumptions?

No.

But you do have to start somewhere and these provide a relatively

simple starting point.

In actual practice these assumptions have proven to give

surprisingly good results. Systems designed based on them often

work as expected.

On occasion, when designers run into problems they often think it

is because of something they did. They forget that the theory is

only an approximation to reality. Don’t forget this!


Quantization noise model

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ñxåzHH

The noise mean and variance are:

µe = 0,

σ 2e =

∆2

12=

V2p

12 · 22B−2

Signaltonoise ratio:

SQNR =Px

Pe= Px

12 · 22B

3V2p

= 3Px

V2p

22B

SQNR(dB) = 10 log10 SQNR = 10 log10

3Px

V2p+ 10 log10 22B

= constant given Px + 6B


Peak to RMS worries

Most signals are much more unstructured than is a sinusoid and one

has to worry about the peaktorms ratio in order to minimize

clipping. This means using an rms level somewhat reduced from the

maximum safe sine wave value.

Basically one need to set the “normal” level and allocate some “head

room” for when the signal is large. For example working with a music

selection with soft passages and loud passages.

OFDM (orthogonal frequency division multiplexed) communication

systems generally have a significant peaktorms dynamic range

problem.

Choosing a maximum safe level is often done in a somewhat hand

wavy manner.


Now onto D/A . . .

Reversing the quantiza

tion is easy.

One of many ways: volt

age divider.

What’s the inputoutput

mapping?

Is there anything wrong

with this scheme?


Reversing the sampling process . . .

−3 −2 −1 0 1 2 3

x 104

0

0.1

0.2

0.3

0.4

0.5

Frequency (Hz)

Mag

nitu

de

Spectrum of the reconstructed waveform

◮ Theoretically we can perfectly reconstruct if we sample fast enough.

◮ In practice sampling itself is imperfect. Example D/A output:

◮ Three tones: 200 Hz, 1000 Hz, and 3500 Hz, fs = 8000 Hz.◮ Using a zeroorder hold D/A converter. The dashed line shows the

effects of the zerohold on the spectrum magnitude.◮ It possesses images of the baseband spectrum.


Antiimage filter

Zeroorder hold has weighted (shaded) the spectrum.

Low pass filter needed to attenuate/remove the images.

Might correct for the zeroorder hold amplitude shading.

Low pass cutoff will nominally be somewhat below fs/2.

May have concerns about phase distortion.

Filter may be solely analog or switched capacitor analog cascade.


Quick summary of A/D and D/A

◮ Basics of converting an analog signal to digital form.

◮ A/D: sampling and quantization.

◮ D/A: the reverse of the above processes.

◮ Next: the ADC and DAC on Spartan3 and their use in Lab 4.


Digilent Spartan3 family boards

Digilent sells a variety of design platforms based on Spartan3

variants. These differ in terms of

◮ Spartan3 subfamily, S3, S3E.

◮ Size of the FPGA used.

◮ The type of external memory, static RAM, DRR2, paged and so on.

◮ Connectors used to connect off board devices to the FPGA.

◮ The over voltage protection included on the FPGA lines.

◮ extra and/or different off board connectors.

These boards have in common

◮ Eight slide switches.

◮ Four digit seven segment display.

◮ Four push buttons.

◮ At least four 6pin PMod connectors. A special board (MIB) is

needed for the S3SB in order to add these.


Spartan3 Starter Board used by EECS 452

◮ FPGA : XC3S1000 (106 gates)

◮ Package : FT256 (a ball grid package)

◮ Speed: 4 (not the fast part)

◮ EPROM : XCF04S (larger than on base board)

◮ Board powered by 5 Volt supply.

◮ Regulated voltage : 3.3 Volts.

◮ Signal lines are NOT 5 Volt tolerant!!!!

◮ Three 40pin connectors, A1, A2 and B1.

◮ Supplied with Parallel Port JTAG programming cable. Cable

supported by IMPACT and ExPort.

◮ Connector A2 cabled to C5510 External Peripheral Interface

connector.

◮ Module Interface Board on B1 is used to convert 40pin

connector to 8 6pin PMod connection positions.


Some available PMod boards

◮ Dual 12bit A/D converter, AD1.

◮ Dual 12bit D/A converter, DA2.

◮ Four slide switches, SWITCH.

◮ Digital input, DIN1.

◮ Dual BNC, CON2.

◮ Speaker/headphone amplifier, AMP1.

◮ Rotary encoder, ENC.

◮ and many more.

Given sufficient lead time we can create our own project specific

boards.


Digilent D/A, A/D and MIB

P3

ADC

1Filter

Filter

AD1 Circuit Diagram

ADC

2P4

P2

P1

P1: CS

P2: Data1

P3: Data 2

P4: Clk

P5: GND

P6: Vcc

P5

P6J2 C

on

necto

r

J1 C

on

necto

r

From Digilent data sheets.

We have modified ourMIB boards to have sockets in positions J1, J3,J5, J7 and pins in theother positions. The UCFnaming is J1→pmod_a,J3→pmod_b, J5→pmod_cand J7→pmod_d.


Pmod, MIB and other connectors

◮ Pins on MIB connect to pins on PMod modules.

◮ We have installed sockets on alternate positions.

◮ Use socketsocket cables to connect pins.

◮ Make sure VB on MIB connects to VCC on PMod!

◮ Make connections with power OFF!

On the S3SB:

◮ For now connector A1 is “not” being used. (Actually is

connected to memory bus which is used by the XVGA

entity.)

◮ A2 is reserved for connecting to DSK peripheral interface

bus to the Spartan3 Starter Board.

◮ B1 is left for use by other devices. MIB goes here !

◮ The Spartan3 Starter Boards has provision for lots of

connections. This is the primary reason we chose it.


PMod pins

PMod pin names used on the MIB.

◮ IO1 — general I/O




◮ GND — power ground.

◮ V — never use any voltage other than 3.3 volts.

Names used on individual boards vary with the board.

Please try very hard to connect V to the V pin on the PMod being

plugged in. Things will often work better that way.


EECS 452 “standard” PMod placement

Our goal is to always place, one to all, the switch, A/D and D/A

PMod boards as follows.

◮ Four slide switch PMod goes J1 (PMod A).

◮ A/D PMod goes J3 (PMod B).

◮ available, J5 (PMod C).

◮ D/A PMod goes J7 (PMod D).

It makes life a bit simpler having some predictability.


Lab exercise 4

◮ Demonstrates:◮ interfacing the PMod DA2 D/A converter,◮ DDS using the S3SB,◮ interfacing the PMod AD1 A/D converter,◮ single supply level shifting,◮ S3SB electret microphone interface.◮ simple A/D in, D/A out loop,◮ S3SB/C5510 link, C5510 master,◮ metastability demonstration,◮ S3SB/C5510 link, S3SB master.

The exercise introduces the dualchannel A/D and D/A PMod

modules.


Combined topdown, bottomup design

The only real design effort was implementing the bit serial

interfaces for the D/A and A/D devices.

◮ Two chips mounted per PMod board.

◮ One converter per chip.

◮ Four lines: data 1, data 2, sync, clock.

◮ Max clock rates of 30 (D/A) and 20 (A/D) MHz.!

◮ 16bit data frames are used.

Low level entities were created first. Attention was given on

these would be used by higher levels. Tested using test VHDL.

These might be considered device drivers written in VHDL.


Starting with the D/A

A simple test is to run a counter and send the count values to

the D/A and observe the waveform. About as basic test you can

do.

Check the schematic and data sheet to

◮ determine the part number.

◮ see how the part is designed into the board.

◮ find the PMod pin signal assignments.

Check the D/A data manual to determine

◮ how it works. Actually, to learn how to make it work.

◮ the signal timings.

◮ the mapping from digital input values to output voltages.


The Digilent PModDA2 module

GND

VCC

DAC121S101D/A

Converter

DAC121S101D/A

Converter

D2

D1

2 Sync,Clock

Analog Outputs

J1 C

onnecto

r

J2 C

onnecto

r

The PModDA2 uses two National Semiconductor DAC121S101

12bit digitaltoanalog converters with railtorail output.

Uses a bitserial interface. Maximum serial clock rate is 30 MHz.

Operates using supply voltages in the range 2.7V to 5.5V.

Figure from the PMod Digilent data sheet.


The DAC121S101 D/A

Max serial clock : 30 MHz

Data uses offset binary.

Analog output updates on 16th

shift clock falling edge.

From the National Semiconductor data sheet.

20114906


How to make the D/A work

Here are some observations/guesses about the control of the

D/A. These are based on the timing diagram and written signal

descriptions contained in the data sheet. Use of a state machine

in the D/A control logic is assumed.

◮ sync_n can remain high between updates going low when a

serial transfer is to start.

◮ The start of a serial transfer is detected by sampling

sync_n using the rising edges of sclk.

◮ Data bits are sampled on the falling edges of sclk.

◮ There is a counter in the D/A that loads D/A holding

register from the input shift register. Possibly on the 16th

falling edge of sclk.

◮ After loading the DAC register the state machine waits for

the next high to low transition on sync_n


Going from now to next

if rising_edge(clk) then

what shall be <= depends upon what now is;

end if;

counter <= counter+1;

if counter = 15 then

whatever

end if;

What happens when entering this code segment with counter

containing 14? Does whatever happen or not?


D/A driver bodyentity pmod_dac0 is

Port ( go : in STD_LOGIC;da_a : in STD_LOGIC_VECTOR (11 downto 0);da_b : in STD_LOGIC_VECTOR (11 downto 0);pmod : out STD_LOGIC_VECTOR (3 downto 0);clk : in STD_LOGIC);

end pmod_dac0;

architecture Behavioral of pmod_dac0 is

signal sync_n, sclk : std_logic := ’1’;signal counter : std_logic_vector(3 downto 0);signal d_a, d_b : std_logic_vector(11 downto 0);signal sr_a, sr_b : std_logic_vector(15 downto 0);signal goo, clear_goo : std_logic := ’0’;signal mygoo : std_logic_vector(1 downto 0);type t_state is (s_idle, s_wait, s_run);signal state : t_state := s_idle;

beginpmod(0) <= sync_n; pmod(1) <= sr_a(15);pmod(2) <= sr_b(15); pmod(3) <= sclk;

process(go, clear_goo) is beginif clear_goo = ’1’ then goo <= ’0’;elsif rising_edge(go) then

d_a <= da_a; d_b <= da_b; copy input valuesgoo <= ’1’; note go happened

end if;end process;

main process goes here

end Behavioral;


D/A driver main processprocess(clk, da_a, da_b) isbegin

if rising_edge(clk) thensclk <= not sclk; generate clk/2 shift clockmygoo <= mygoo(0) & goo; sample go signalcase state is

when s_idle =>sclk <= ’1’; hold DA clock highif mygoo = "01" then rising edge test

sr_a <= "0000" & not d_a(11) & d_a(10 downto 0);sr_b <= "0000" & not d_b(11) & d_b(10 downto 0);counter <= (others => ’0’);sync_n <= ’0’;sclk <= ’0’;clear_goo <= ’1’;state <= s_wait;

end if;when s_wait =>

clear_goo <= ’0’;state <= s_run;

when s_run =>if sclk = ’0’ then

sr_a <= sr_a(14 downto 0) & ’0’;sr_b <= sr_b(14 downto 0) & ’0’;counter <= counter+1;if counter = 15 then

sync_n <= ’1’;state <= s_idle;

end if;end if;

end case;end if;

end process;


Initiating a conversion

◮ This entity is designed so that the go and the clk signal can

exist in different clock domains.

◮ Moving a signal between clock domains usually involves a

level in one domain whose change signals an event, and a

clock in a second domain that samples the event signal.

◮ If the setup time on the register being used to latch the

event is smaller than required, the register can enter a

metastable state.

◮ A metastable state is one where the latch knows that a

decision is needed about whether or not the event occurred,

but it can’t decide. In theory this can take forever.

◮ Metastable events cannot be avoided. However there are

things that one can do to minimize the probability of a

metastable state becoming a problem.


Walk through

◮ 50 MHz clock is assumed.

◮ 25 MHz SCLK is generated unless explicitly held high. 25

MHz is within the the D/A 30 MHz limit.

◮ GO pulses are assumed to be spaced at least 1 µs apart.

Only needs to be one 50 MHz clock period long.

◮ When GO is ’1’ then set fourbit counter to 0, copy 12bit a

and b values into 16bit shift registers with “normal” flag

bits. Send sync_m and SCLK low.

◮ Skip the low part of SCLK.

◮ Loop changing state only when SCLK is low. At the low to

high transition, shift data, increment the counter. However,

if the counter is 15 then also set sync_m high and go back

to idling state.

Recall that the values to be updated are updated on the NEXT

rising edge of the clk.


D/A timing diagram

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Simple test using rampsentity rampgen is

Port ( go : out STD_LOGIC;ramp_a : out STD_LOGIC_VECTOR (11 downto 0);ramp_b : out STD_LOGIC_VECTOR (11 downto 0);led : out STD_LOGIC_VECTOR(7 downto 0);clk : in STD_LOGIC);

end rampgen;

architecture Behavioral of rampgen issignal a_ramp, b_ramp : std_logic_vector(11 downto 0);signal counter : std_logic_vector(5 downto 0);

beginramp_a <= a_ramp;ramp_b <= b_ramp;process(clk) isbegin

if rising_edge(clk) thencounter <= counter+1;go <= ’0’;if counter = 0 then

go <= ’1’;a_ramp <= a_ramp+1;b_ramp <= b_ramp+3;

end if;end if;

end process;end Behavioral;


D/A test topentity DACtest0top is

Port ( pmod_d : out STD_LOGIC_VECTOR (3 downto 0);led : out STD_LOGIC_VECTOR (7 downto 0);mclk : in STD_LOGIC);

end DACtest0top;

architecture Behavioral of DACtest0top is

signal clk, go : std_logic;signal dclk : std_logic_vector(3 downto 0);signal pmod : std_logic_vector(3 downto 0);signal ramp_a, ramp_b : std_logic_vector(11 downto 0);

begin

pmod_d <= pmod;clk <= mclk;

reduce the clock when generating scope displayclk <= dclk(3); normally a big nono!

led <= ramp_b(11 downto 4);

dac : entity work.pmod_dac0port map(go => go, da_a => ramp_a, da_b => ramp_b,

pmod => pmod, clk => clk);

ramper : entity work.rampgenport map(go => go, ramp_a => ramp_a, ramp_b => ramp_b, clk => clk);

process(mclk) isbegin

if rising_edge(mclk) thendclk <= dclk+1;

end if;end process;

end Behavioral;


Using the D/A to create a sine wave DDS

Now that we have a D/A driver and know how to make a

counter let’s make a sine wave direct digital synthesizer!

The Xilinx CORE Generator provides modules for a sine/cosine

lookup table and for a DDS. We could use these. Some other

day. For now we will go DIY (using the DDS VHDL code we

showed in the previous lecture).

To create a DDS we need a ROM and we need to program the

ROM.


Working with block RAM

Something like 24 18K bit blocks of dual port memory on the

S3/1000 boards.

Divided into parity and data sections.

Word size is independently configurable for each port.

Are initialized upon the FPGA is programmed. Becomes a ROM

if one does not write to it.

Initialized using 256 bit vectors.

Can share a block RAM between ROM for a DDS and a delay

memory used by a FIR filter.

Use instantiation templates found in ISE. Not very difficult to

work with. RAM blocks are clocked, so one need to think a bit

about what happens when.


A simple DDS entity (1/2)

Uses two processes.

beginAC0 <= ACC0(31 downto 24);AC1 <= ACC1(31 downto 24);

process(clk, reset)begin

if reset = ’1’ thenelsif rising_edge(clk) then

counter <= counter_next;ACC0 <= ACC0_next;ACC1 <= ACC1_next;FTV0R <= FTV0R_next;FTV1R <= FTV1R_next;DAC_load <= DAC_load_next;

end if;end process;


A simple DDS entity (2/2)

process(FTV0_load, FTV1_load)begin

ACC0_next <= ACC0;ACC1_next <= ACC1;FTV0R_next <= FTV0R;FTV1R_next <= FTV1R;DAC_load_next <= ’0’;if counter = 49 then

ACC0_next <= ACC0+FTV0R;ACC1_next <= ACC1+FTV1R;DAC_load_next <= ’1’;counter_next <= "000000";

elsecounter_next <= counter+1;

end if;if FTV0_load = ’1’ then

FTV0R_next <= FTV0;end if;if FTV1_load = ’1’ then

FTV1R_next <= FTV1;end if;

end process;end Behavioral;


Sine table initialization

Address 0 to 255INIT_00 => X"2E112B1F2826252822231F1A1C0B18F915E212C80FAB0C8C096A064803240000",INIT_01 => X"584255F5539B51334EBF4C3F49B4471C447A41CE3F173C56398C36BA33DF30FB",INIT_02 => X"750473B5725470E26F5E6DC96C236A6D68A666CF64E862F160EB5ED75CB35A82",INIT_03 => X"7FF57FD87FA67F617F097E9C7E1D7D897CE37C297B5C7A7C79897884776B7641",INIT_04 => X"776B788479897A7C7B5C7C297CE37D897E1D7E9C7F097F617FA67FD87FF57FFF",INIT_05 => X"5CB35ED760EB62F164E866CF68A66A6D6C236DC96F5E70E2725473B575047641",INIT_06 => X"33DF36BA398C3C563F1741CE447A471C49B44C3F4EBF5133539B55F558425A82",INIT_07 => X"03240648096A0C8C0FAB12C815E218F91C0B1F1A2223252828262B1F2E1130FB",INIT_08 => X"D1EFD4E1D7DADAD8DDDDE0E6E3F5E707EA1EED38F055F374F696F9B8FCDC0000",INIT_09 => X"A7BEAA0BAC65AECDB141B3C1B64CB8E4BB86BE32C0E9C3AAC674C946CC21CF05",INIT_0A => X"8AFC8C4B8DAC8F1E90A2923793DD9593975A99319B189D0F9F15A129A34DA57E",INIT_0B => X"800B8028805A809F80F7816481E38277831D83D784A485848677877C889589BF",INIT_0C => X"8895877C8677858484A483D7831D827781E3816480F7809F805A8028800B8001",INIT_0D => X"A34DA1299F159D0F9B189931975A959393DD923790A28F1E8DAC8C4B8AFC89BF",INIT_0E => X"CC21C946C674C3AAC0E9BE32BB86B8E4B64CB3C1B141AECDAC65AA0BA7BEA57E",INIT_0F => X"FCDCF9B8F696F374F055ED38EA1EE707E3F5E0E6DDDDDAD8D7DAD4E1D1EFCF05",

256 values of 16bits. Used MATLAB to generate. Primary thing to

realize is that the least significant bit is on the right and the most

significant bit is on the left.


The Digilent PModAD1 module

P3

ADC

1Filter

Filter

AD1 Circuit Diagram

ADC

2P4

P2

P1

P1: CS

P2: Data1

P3: Data 2

P4: Clk

P5: GND

P6: Vcc

P5

P6

J2 C

on

necto

r

J1 C

on

necto

r

That was D/A. Now let’s take a look at the A/D PMod.

The PModAD1 uses two National Semiconductor ADCS7476 12bit

analogtodigital converters supporting railtorail input.

Uses a bitserial interface. Maximum serial clock rate is 20 MHz.

Operates using supply voltages in the range 2.7V to 5.25V.

Figure from the PMod Digilent data sheet.


The ADCS7476 A/D

Max serial clock : 20 MHz

Max sample rate: 1 MHz

Data uses offset binary.

Input switches from track to hold on

falling edge of the sync signal.

From the National Semiconductor data sheet.


Shifting the voltage: A/D input using a single supply

oN

oO

oQ

oP

oR

H

J

îáîç

îë

î~

Analysis of this is included in the lab writeup.

A common problem we’ll encounter is that our signals are “zero

referenced”: it is centered on zero and swing between positive and

negative voltage levels. Most of today’s signal sources are voltage

sources and DC coupled sources. The problem is that the ADC expects

voltages from 0 to Vcc. So we need to shift the signal voltage.


A/D driver body

entity pmod_adc0 isPort ( go : in STD_LOGIC;

ad_a : out STD_LOGIC_VECTOR (11 downto 0);ad_b : out STD_LOGIC_VECTOR (11 downto 0);pmod : inout STD_LOGIC_VECTOR (3 downto 0);clk : in STD_LOGIC);

end pmod_adc0;

architecture Behavioral of pmod_adc0 is

signal goo, clear_goo : std_logic := ’0’;signal sclk, cs_n : std_logic := ’1’;signal ad0, ad1 : std_logic;signal mygoo : std_logic_vector(1 downto 0);signal counter : std_logic_vector(3 downto 0);signal ar_a, ar_b : std_logic_vector(11 downto 0);

type t_state is (s_idle, s_convert);signal state : t_state;

beginpmod(0) <= cs_n and (not goo); ad0 <= pmod(1);ad1 <= pmod(2); pmod(3) <= sclk;

process(go, clear_goo) is beginif clear_goo = ’1’ then goo <= ’0’;elsif rising_edge(go) then

goo <= ’1’;end if;

end process;

main process goes here

end Behavioral;


A/D driver main process

process(clk) is beginif rising_edge(clk) then

sclk <= not sclk;mygoo <= mygoo(0) & goo;

case state iswhen s_idle =>

sclk <= ’1’;if mygoo = "01" then

cs_n <= ’0’;counter <= (others => ’0’);state <= s_convert;

end if;when s_convert =>

clear_goo <= ’1’;if sclk = ’1’ then

ar_a <= ar_a(10 downto 0) & ad0;ar_b <= ar_b(10 downto 0) & ad1;counter <= counter+1;if counter = 15 then

ad_a <= not ar_a(10) & ar_a(9 downto 0) & ad0;ad_b <= not ar_b(10) & ar_b(9 downto 0) & ad0;clear_goo <= ’0’;cs_n <= ’1’;state <= s_idle;

end if;end if;

end case;end if;

end process;


adc-dac-ppt

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