adaptive control methods for dc-dc switching power
TRANSCRIPT
ADAPTIVE CONTROL METHODS FOR DC-DC SWITCHING
POWER CONVERTERS
by
VARAPRASAD ARIKATLA
JABER ABU QAHOUQ, COMMITTEE CHAIR
TIM A. HASKEW
YANG-KI HONG
JEFF JACKSON
DANIEL J. FONSECA
A DISSERTATION
Submitted in partial fulfillment of the requirements
for the degree of Doctor of Philosophy in the
Department of Electrical and Computer Engineering
in the Graduate School of
The University of Alabama
TUSCALOOSA, ALABAMA
2011
ii
ABSTRACT
Tight regulation of the output voltage is often required in many power supply applications,
despite the highly dynamic nature of the loads. This is conventionally obtained by the design of
high bandwidth feedback loop or recently by using adaptive control methods. The control loop is
designed with specified safe bandwidth and gain and phase margins such that it maintains stable
operation under variable conditions and parameters. However, this results in a compromise
between achievable dynamic performance and robustness of control loop. The large variations in
operating points and load makes the system design challenging. The tight regulation
requirements, in addition to size and weight requirements, are getting stricter by time, which
makes it necessary to investigate new control concepts in order to meet these requirements. Not
meeting the tight regulation requirements may result in either the malfunctioning of the device
(load) being powered or the destruction of that device.
This work focuses on the development and implementation of adaptive control methods that
result in the improvement of the dynamic performance of power converter, by utilizing the
flexibility of digital controllers to realize advanced control schemes. Four different methods are
proposed that improve the dynamic performance of converter without compromising the steady-
state performance.
A Sensorless Adaptive Voltage Positioning (SLAVP) control scheme is proposed in Chapter
2, in order to realize Adaptive Voltage Positioning (AVP) control without the need for load or
inductor current sensing and high-resolution high-speed Analog-to-Digital Converter
iii
(ADC) sampling. The SLAVP control law utilizes the readily available error signal of the
conventional voltage-mode closed-loop compensated controller, or in other words the duty cycle
of a DC-DC buck converter, in order to realize AVP control. The elimination of the need for
high-speed and accurate sensing and sampling of currents using the proposed SLAVP control
reduces the size and cost of the digital controller, reduces the power losses associated with
current sensing and sampling, and simplifies hardware design, apart from improving dynamic
performance.
In Chapter 3, an Adaptive Digital PID (AD-PID) controller scheme is proposed. The
controller adaptively adjusts the integral constant (Ki) and the proportional constant (Kp) of the
compensator following a new control law. The control law is a function of the magnitude change
in the error signal, and its peak value during dynamic transients. The proposed AD-PID
controller adaptively detects the peak value of the error signal which is a function of the transient
nature and magnitude and utilize it in the control law such that no ocillations are generated as a
result of the adaptive operation. As a result, the dynamic output voltage deviation and the settling
time of the output voltage are reduced.
A novel Compensator Error Observe and Modulate method (CEO&M) for online closed-loop-
compensator auto-tuning of digital power controller is proposed in Chapter 4. The proposed
method is relatively simple, and does not require the knowledge and/or measurement of the
power stage or closed-loop frequency response. Moreover, the proposed method does not depend
on conventional design methods and the associated rule of thumb design criteria in order to tune
closed-loop feedback controllers of power converter for high, and possibly optimum, dynamic
performance.
iv
Furthermore, two approaches for dynamic variable switching frequency digital control scheme
under dynamic transients are proposed in Chapter 5 in order to improve the dynamic
performance of the DC-DC switching power converter. The proposed controller varies the
switching frequency of the converter, higher or lower than the steady-state frequency, during the
transient as a function of peak and magnitude of error signal depending on the amount and type
of the transient.
Finally, Chapter 6 summarizes this work and provides conclusions before discussing future
related research direction.
v
LIST OF ABBREVIATIONS AND SYMBOLS
AC Alternating Current
ADC Analog to Digital Converters
AD-PID Adaptive Digital PID
APWM
Analog PWM
ATerror
Controller
Auto-Tuning controller
AVP Adaptive Voltage Positioning
C Capacitor
CCM Continuous Conduction Mode
CEO&M Compensator Error Observe and Modulate
limitC Limit on the number of counts of the counter
D Duty cycle or Duty ratio
( )d s Laplace of duty cycle
1mxD Maximum duty cycle value
2mnD Minimum duty cycle value
vi
DC Direct Current
DCR Output inductor equivalent DC resistance
idealD Ideal duty cycle for a lossless DC-DC buck converter
DPWM Digital Pulse Width Modulators
DSP Digital Signal Processor
( )v drop oD I Additional duty cycle caused by resistive voltage drop
DVSF
Digital Variable Switching Frequency
ESL Equivalent series inductance of the output capacitors
ESR Equivalent Series Resistance of the output capacitors
clkf Clock frequency
DPWMf Frequency of DPWM
DPWM maxf Maximum Frequency of DPWM
DPWM minf Minimum frequency of DPWM
( )mF s PWM Modulator transfer function/gain
FPGA Field Programmable Gate Array
swf Switching frequency
Ve compf Frequency of e compV
vii
( )comG s Compensator transfer function
( )dgG s Input voltage to duty cycle transfer function
( )odiG s Output current to duty cycle transfer function
DPWMG Gain of DPWM
( )PIDG z Transfer function of a digital parallel PID controller
( )vdG s Duty cycle to output voltage transfer function
( )vgG s Input voltage to output voltage transfer function
( )H s Output voltage sensor transfer function/gain
HL Upper limit
ci Current through C
IC Integrated Circuits
oi Output current
o maxI Maximum load current value
o minI Minimum load current value
senseI Current sensed signal
K Gain of compensator
Kd Derivative gain constant
viii
Kd-steady Steady state value of Kd
KHz Kilo Hertz: Unit of Frequency
Ki Integral gain constant
Ki-steady Steady state value of Ki
Ki-trans Transient value of Ki
Kp Proportional gain constant
Kp-steady Steady state value of Kp
Kp-trans Transient value of Kp
L Inductor
LL Lower limit
mF Milli Farad: Unit of capacitance:
nH Nano Henry: Unit for inductance
NL Non-Linear
P1 Pole of compensator
PID Proportional Integral Differential
PWM Pulse Width Modulation
RAM Random Access Memory
.eqR Equivalent resistance
ix
esrR Output capacitor ESR
oR Load resistance
onR MOSFET ON state resistance
SLAVP Sensor Less Adaptive Voltage Positioning
LS Low side switch
SPC Switched power converters
US High side switch
AT Time period of ramp signal
( )dT s SLAVP loop gain
DPWM minT Minimum time period of DPWM
DPWM maxT Maximum time period of DPWM
DPWM steadyT Time period of DPWM at steady state
( )vT s Voltage loop gain
ADCV Resolution of ADC
cV Compensated error signal
Cv Voltage drop due to C
x
cAV Value of compensated error signal
e compV Compensated error signal
e ppV Peak-to-peak value of the compensated error signal
errorv Error signal
Verror(n) Value of error signal in nth switching cycle
Verror-peak Peak value of verror
ESLv Voltage drop due to ESL
ESRv Voltage drop due to ESR
( )gv s Laplace of input voltage
VID Voltage Identification Code
in nomV Nominal input voltage
2mnin nom DV Nominal input voltage of the power converter at which 2mnD value is measured
ov Output voltage
o maxV Maximum allowed output voltage
o midV Output voltage middle value
o minV Minimum allowed output voltage
o nomV Nominal output voltage
xi
2mno nom DV Nominal output voltage of the power converter at which 2mnD value is measured
o VIDV Desired nominal output voltage
peakAV Peak voltage of ramp signal
VR Voltage Regulators
Vref Reference Output Voltage
senseV Voltage sensed signal
Vthr Threshold voltage
( )oZ s Output current to output voltage transfer function
( )ocZ s Output impedance transfer function
x Absolute value of x
oI Load current variation
.eqR Change in .eqR
delt Delay in the response of the controller
transt Transient time
ESLv Transient voltage drop due to ESL
ESRv Transient voltage drop due to ESR
,L Cv Transient voltage deviation due to power stage output filter
xii
ov Transient output voltage drop
o specV Desired AVP control voltage window
tdelv Transient voltage due to closed loop control delay
c Cutoff frequency
xiii
ACKNOWLEDGEMENTS
The author would first like to express his heartfelt gratitude to his advisor Dr. Jaber Abu
Qahouq for his guidance, encouragement and support in conducting this research. Dr. Abu
Qahouq’s critical thinking and extensive vision has been the source of inspiration for the author
throughout his work.
The author is grateful to his committee members Dr. Tim A. Haskew, Dr. Jeff Jackson, Dr.
Yang-Ki Hong and Dr. Daniel J. Fonseca for their valuable time and support.
The author would also like to acknowledge the non-academic help of his friends, and his
roommates Dr. Pankaj S. Kolhe and Nandhakumar Kathiresshan.
Last but not least, the author is grateful to his family, whose love and support has enabled him
to accomplish this work.
xiv
CONTENTS
ABSTRACT .................................................................................................................................... ii
LIST OF ABBREVIATIONS AND SYMBOLS ............................................................................v
ACKNOWLEDGEMENTS ......................................................................................................... xiii
LIST OF TABLES ...................................................................................................................... xvii
LIST OF FIGURES ................................................................................................................... xviii
1. INTRODUCTION .....................................................................................................................1
1.1. Overview ...................................................................................................................................1
1.2. Digital Control of Power Converters ........................................................................................2
1.3. Main Motivations and Objectives of This Work ......................................................................5
1.4. Dissertation Outline ..................................................................................................................9
2. SENSOR LESS ADAPTIVE VOLTAGE POSITIONING (SLAVP) CONTROL ................11
2.1. Introduction .............................................................................................................................11
2.2. Sensorless Adaptive Voltage Positioning Control Basis ........................................................15
2.3. SLAVP Control Law Derivation and Hardware Realization ..................................................18
2.3.1. SLAVP Control Law with Fixed Input and Output Voltages ..............................................18
2.3.2. SLAVP Control Law with Variable Input Voltage..............................................................20
2.3.3. SLAVP Control Law with Variable Output Voltage ...........................................................23
2.4. Effects of Component DC Resistance Tolerance and Input Voltage Variation ......................26
2.4.1. Analysis of DC Resistance Tolerance Effect on the SLAVP Window ...............................26
2.4.2. Analysis of Input Voltage Variation Effect on the SLAVP Window ..................................28
xv
2.5. Proof-Of-Concept Experimental Prototype Results................................................................28
2.6. Dynamic Modeling Results .....................................................................................................35
2.7. Summary .................................................................................................................................40
3. ADAPTIVE DIGITAL PID (AD-PID) CONTROLLER ........................................................42
3.1. Introduction .............................................................................................................................42
3.2. Background for the Proposed AD-PID controller ..................................................................44
3.3. AD-PID Control Law and Algorithm .....................................................................................48
3.4. AD-PID Control Law Design Guidelines ...............................................................................52
3.5. Proof-Of-Concept Experimental Prototype Results................................................................55
3.6. Comparison Of AD-PID With Other Non-Linear PID Strategies ..........................................61
3.7. Summary .................................................................................................................................62
4. A NOVEL ADAPTIVE AUTO-DESIGN AND AUTO-TUNING METHOD FOR
CLOSED-LOOP CONTROLLERS OF POWER CONVERTERS ........................................63
4.1. Introduction .............................................................................................................................63
4.2. Bases of the Proposed Online Auto-Tuning Controller ........................................................... 66
4.3. Online Auto-Tuning Digital Controller Algorithm and Architecture .....................................72
4.4. Proof-Of-Concept Experimental Prototype Results................................................................75
4.4.1. Experimental Verification of the Auto-Tuning Controller Bases ........................................76
4.4.2. Experimental Operation and Results of the Online Auto-Tuning Controller ......................78
4.5. Summary .................................................................................................................................85
5. AN ADAPTIVE DIGITAL VARIABLE FREQUENCY CONTROL SCHEME ..................87
5.1. Introduction .............................................................................................................................87
5.2. Digital Pulse Width Modulation .............................................................................................. 89
5.3. Adaptive Switching Frequency Control Schemes ..................................................................91
xvi
5.3.1. DVSF I .................................................................................................................................92
5.3.2. DVSF II ................................................................................................................................94
5.4. Theoretical Analysis ...............................................................................................................97
5.5. Experimental Prototype Results ..............................................................................................99
5.5.1. DVSF I .................................................................................................................................99
5.5.2. DVSF II ..............................................................................................................................102
5.6. Summary ...............................................................................................................................104
6. CONCLUSIONS AND FUTURE WORK ............................................................................105
6.1. Summary of Conclusions ......................................................................................................105
6.1.1. Digital Sensor Less Adaptive Voltage Positioning Control Scheme .................................106
6.1.2. An Adaptive Digital PID Controller for Power Converters...............................................106
6.1.3. A Novel Adaptive Auto-Design and Auto-Tuning Method for Closed-Loop
Controllers of Power Converters .......................................................................................107
6.1.4. An Adaptive Digital Variable Frequency Control Scheme ...............................................108
6.1.5. Additional Comments on the Use of the Proposed Concepts ............................................108
6.2. Future Research Directions ...................................................................................................110
6.2.1. Application of Proposed Control Schemes for Multiphase Buck Converter .....................110
6.2.2. Application of Auto-Tuning and Auto-Design Technique for Pole and Zero Variation ...110
6.2.3. Combined Utilization of Proposed Control Schemes ........................................................110
6.2.4. Application of SLAVP Control Scheme for Multi-Sampled Implementation...................111
6.2.5. Optimization of the Digital Controller Realization and Implementation ..........................111
6.2.6. Application of Proposed Control Schemes for Other Topologies .....................................112
REFERENCES ............................................................................................................................113
xvii
LIST OF TABLES
3.1. Values of variables used in the design example .....................................................................55
5.1. Comparison of improvement in overshoot using different DVSF control methods .............104
xviii
LIST OF FIGURES
1.1. Block diagram of a power converter with digital controller ..................................................3
1.2. Illustration of DPWM functionality .......................................................................................4
1.3. Buck converter with consideration of circuit component parasitic ........................................5
1.4. Illustration of output voltage overshoot during step-down load transient..............................6
2.1. (a) DC-DC buck converter with one implementation type of conventional AVP
control and (b) Conventional AVP control waveforms .......................................................14
2.2. DC-DC buck converter duty cycle plots as a function of load current, input voltage,
and output voltage to illustrate duty cycle linearity (a) for different input voltages
and (b) for different output voltages ....................................................................................16
2.3. (a) A theoretical plot for the output voltage vs. load current for a DC-DC buck
power converter with AVP control and (b) a theoretical plot for the output voltage
vs. D for a DC-DC buck power converter with AVP control ..............................................17
2.4. Theoretical SLAVP control waveforms ...............................................................................18
2.5. Digital System Block Diagram for SLAVP control Hardware Realization .........................20
2.6. Digital System Block Diagram for SLAVP control Hardware Realization which
accounts for both variable input voltage and variable output voltage (a) SLAVP
controller with variable output voltage and (b) SLAVP with variable input and
output voltages .....................................................................................................................25
2.7. Experimental results to show the linear relationship (within the range of operation)
of duty cycle as a function of the input and output voltages and load current for the
experimental prototype (a) 2mnD as a function of input voltage at 1.5V output
voltage and 10A load current, (b) 2mnD as a function of output voltage at 9V input
voltage and 10A load current and (c) D as a function of load current at 9V input
voltage. .................................................................................................................................30
xix
2.8. Experimental results of the prototype with SLAVP under dynamic load transients
of 0A-10A-0A (full load range from minimum to maximum) with 1.5oV V and
SLAVP window of 50mV (a) at 9inV V and (b) at 10inV V ...........................................31
2.9. Experimental results of the prototype with SLAVP under dynamic load transients
of 0A-10A-0A (full load range from minimum to maximum) with 9inV V and
SLAVP window of 50mV (a) at 1.7oV V and (b) at 1.4oV V .......................................32
2.10. Experimental results of the prototype with SLAVP window of 50mv and under
dynamic load transients of (a) 4A-7A-4A at 1.5oV V and 9inV V and (b) 0A-
8A-0A at 1.3oV V and 8inV V .........................................................................................33
2.11. Experimental results of the prototype with SLAVP window of 50mv and under 0A-
10A-0A dynamic load transients showing zoomed in view of output voltage and
inductor current during (a) load step-up transient and (b) load step-down transient ...........34
2.12. Small signal control block diagram with SLAVP ................................................................36
2.13. Equivalent control block diagram to that shown in Figure. 2.12 .........................................36
2.14. Bode-plots for ( )vT s and ( )dT s ............................................................................................39
2.15. Output impedance plot .........................................................................................................40
3.1. DC-DC buck converter with digital controller .....................................................................43
3.2. A conventional digital PID controller realization diagram ..................................................44
3.3. Example bode-plots for different values of (a) Kp and (b) Ki and (c) Kp and Ki ...............46
3.4. A general Adaptive digital PID controller realization diagram ...........................................47
3.5. Illustration of the AD-PID controller operation ...................................................................49
3.6. Flowchart for the proposed adaptive controller ...................................................................50
3.7. Experimental results of the prototype with zoomed in view under dynamic load
step-down transient of 7A-0A (a) with conventional PID controller and (b) with
AD-PID controller ................................................................................................................56
3.8. Experimental results of the prototype with zoomed in view under dynamic load
step-up transient of 0A-7A (a) with conventional PID controller and (b) with AD-
PID controller .......................................................................................................................57
xx
3.9. Experimental results of the prototype with zoomed in view under dynamic load
step-down transient of 6A-2A (a) with conventional PID controller and (b) with
AD-PID controller ................................................................................................................58
3.10. Experimental results of the prototype with zoomed in view under dynamic load
step-up transient of 2A-6A (a) with conventional PID controller and (b) with AD-
PID controller .......................................................................................................................59
3.11. Experimental results of the prototype with zoomed in view under steady-state
operation (a) with PID controller with Kp-trans and Ki-trans and (b) with PID controller
with Kp-steady and Ki-steady .......................................................................................................60
4.1. A block diagram of a power converter system with closed loop control .............................66
4.2. Bode-plots for (a) different gain (K) values and (b) different pole (P1) locations ..............67
4.3. Simulation results of a DC-DC buck converter to demonstrate the basis of the
proposed CEO&M control concept based on several K values (Note that
.e conv e compV V ): (a) during steady-state and (b) during step-up load transient. ................68
4.4. Simulation results of a DC-DC buck converter to demonstrate the basis of the
CEO&M control concept (Note that .e conv e compV V ) based on several pole
locations (one pole is moved): (a) during steady-state, (b) during step-up load
transient and (c) during step-down load transient. ...............................................................69
4.5. An illustration of the compensated error signal behavior under different bandwidth
values with analog compensator ..........................................................................................71
4.6. An illustration of the compensated error signal behavior under different bandwidth
values with digital compensator ...........................................................................................71
4.7. DC-DC buck converter with digital closed-loop compensator and ATerror
Controller .............................................................................................................................72
4.8. General main implementation flowchart of the ATerror controller. ....................................74
4.9. Digital compensator used in the proof of concept experimental prototype .........................76
4.10. Experimental results of a DC-DC buck converter to demonstrate the basis of the
proposed CEO&M control concept when varying gain. (a) and (b): Lower gain
( 0.344TK ). (c) and (d): Medium gain ( 1.593TK ). (e) and (f): Higher
(Unstable) gain ( 2.531TK ). (a), (c) and (e): During Steady-State Operation. (b),
(d) and (f): Under 8A-0A-8A Load Current Transient.........................................................77
4.11. A flowchart for the detection of direction of gain change (increase/decrease) ....................79
xxi
4.12. A flowchart for the detection of frequency change and setting of gain ...............................82
4.13. Illustration of the controller operation to determine the variable under auto-tuning
(the gain here) required direction change and the detection of frequency change
condition ...............................................................................................................................83
4.14. Experimental waveforms of the prototype with the ATerror controller. (a): The
variation of gain until new optimized gain value is achieved.(b): Periodic tuning
operation of the ATerror controller ......................................................................................84
4.15. Dynamic response of the power converter during a load transient of 8A to 0A (a)
before auto-tuning (b) after auto-tuning ...............................................................................85
5.1. Block diagram of a Power Converter with Digital Controller .............................................88
5.2. Generation of duty cycle command signal with (a) analog controller (b) digital
controller ..............................................................................................................................89
5.3. DPWM operation principle illustration with fixed switching frequency during
(a) steady state (b) step-up load transient and (c) step-down load transient ........................90
5.4. Illustration of operational principle of DPWM with variable switching frequency
during (a) steady-state (b) step-up load transient which causes output voltage
undershoot and (c) step-down load transient which causes output voltage overshoot .........92
5.5. Illustration of Dynamic Variable Switching Frequency (DVSF) Controller
Operation ..............................................................................................................................93
5.6. Flowchart for the adaptive switching frequency controller..................................................94
5.7. Illustration of the adaptive switching frequency controller operation .................................95
5.8. Dynamic Digital Variable Switching Frequency Controller Flowchart ...............................96
5.9. Experimental results of the prototype with zoomed in view under dynamic load
step-down transient of 5A-0A (a) with fixed frequency DPWM and (b) with
variable frequency DPWM .................................................................................................100
5.10. Experimental results of the prototype with zoomed in view under dynamic load
step-down transient of 0A-5A (a) with fixed frequency DPWM and (b) with
variable frequency DPWM .................................................................................................101
5.11. Experimental results of the prototype with zoomed in view under dynamic load
step-down transient of 5A-0A (a) with fixed frequency DPWM and (b) with
adaptive frequency DPWM ................................................................................................102
xxii
5.12. Experimental results of the prototype with zoomed in view under dynamic load
step-up transient of 0A-5A (a) with fixed frequency DPWM and (b) with adaptive
frequency DPWM ..............................................................................................................103
6.1. Illustration of different adaptive concepts utilization ........................................................109
1
CHAPTER 1
INTRODUCTION
1.1. Overview
In the recent decade, the Switched Power Converters (SPC) have gained interest due to their
high efficiency, small size and increased reliability, among others. The SPC is used to provide
regulated power to many systems, including but are not limited to, microprocessors, FPGAs,
DSPs, RAMs, communication systems, optical networks, consumer electronics, vehicle
electronics, and wireless applications. The increased demand for providing tightly regulated
voltages or currents to the loads has sparked interest in advanced control algorithms for SPCs
[A1-A7]. For these loads, tight regulation of the output voltage is an important performance
constraint [A1-A23] under dynamic conditions of operations. For a standard fixed-frequency,
linear controller, tight regulation is conventionally achieved through the design of a high
bandwidth feedback loop at the expected operating point of the converter.
Though there are a wide range of load requirements, the most important dynamic output
specifications that need to be satisfied by SPCs are:
1. Overshoot or undershoot.
2. Settling time.
The most important causes of the transient conditions are:
a. Load Step.
2
b. Reference Step.
c. Input Voltage Step.
Overshoot and undershoot are defined as the deviation of the output from its final value.
Settling time is defined here as the time taken for the system transient to decay to within 1% of
its final value. The transients may lead to high load temperatures (power losses), damage or
reduced lifespan [A4-A13].
The goals of this dissertation are to investigate the stability issues related to the steady-state
performance of converters, and to develop adaptive digital controllers that optimize the dynamic
performance, in other words, to decrease the output voltage overshoot or undershoot and
decrease its dynamic settling time.
1.2. Digital Control of Power Converters
The digital control of power converters has gained popularity during recent years [A24-A29].
Figure 1.1 shows the block diagram of a power converter with digital controller enclosed with in
the dashed box. Analog to Digital Converters (ADC) are used to sense and digitize the voltage
and/or current and fed to the digital controller. These sensed voltage and/or current are utilized
by the closed loop voltage/current compensator of the digital controller to generate the
compensated error signal ( e compV ).This is then compared with the digital pulse width Modulator
(DPWM) to generate the required duty cycle (D) to maintain a regulated output voltage (in some
power converter also a regulated current or power). This is illustrated in Figure 1.2. The sensed
voltage and/or current may also be utilized to adaptively adjust parameters, including but are not
limited to switching frequency, duty ratio/cycle, and number of phases of the power converter
that result in improvement of efficiency and/or dynamic performances, among others [A4-A10,
A34-A44].
3
The considerations associated with the utilization of digital controllers for power converters
are
1. The limited resolution of Analog to Digital Converters (ADC) and Digital Pulse Width
Modulators (DPWM).
2. The size and power consumption of ADC(s).
3. The speed of ADC(s) and DPWM.
4. Power consumption incurred by the digital circuitry.
Sl
Lo
CoDrivers Latches
D
D1Io
+
-
Vo
iL
Vin
DPWMModulator
D
ADCClosed Loop Voltage/Current
Compensator
Su
ADC
Other Functions and Adaptive
Control
e compV
ADC
Figure. 1.1: Block diagram of a power converter with digital controller.
4
e compV
D
Digital Ramp
Figure. 1.2: Illustration of DPWM functionality.
However, the following advantages associated with the digital implementation of controller
compared with analog controllers, motivated the utilization of digital controllers for power
converters:
1. The digital controllers’ ability to implement sophisticated algorithms for efficiency and
dynamic performance improvement of power converters.
2. The flexibility of reconfiguration and scalability of the parameters of the control loop
without the need for significant changes in hardware.
3. The potential reduction or elimination of controller component variation and sensitivity
that effect the controller performance.
4. Decrease in the cost due to integration of multiple functionalities into a single digital
chip.
5. Increased flexibility with improved protection, health monitoring and non-linear control
techniques.
5
1.3. Main Motivations and Objectives of This Work
Before discussing the motivation for the research work presented in this Dissertation, it is
important to identify the dependence of the power converter voltage deviation from its steady
state value under different operating conditions and different design parameters of the converter.
The discussion is based on a non-isolated DC-DC buck topology and is applicable to many other
types of topologies, especially those that are buck derived. Similar relationships could also be
derived for other topologies that are boost derived for example.
Su
Sl
L
CDrivers
Latches
D
D1Io
+
-
Vo
iL
Vin
Closed Loop
Voltage/
Current
Compensator
PWM
Modulator
e compV
D
senseV
senseI
Ron
Ron
DCR
ESR
ESL
Figure. 1.3: Buck converter with consideration of circuit component parasitic.
Figure. 1.3 shows a buck converter with some of the component non-idealities taken in to
consideration.
onR is the MOSFET ON state resistance.
DCR is the output inductor equivalent DC resistance.
ESR is the equivalent series resistance of the output capacitors.
ESL is the equivalent series inductance of the output capacitors.
6
senseV and senseI are the voltages and currents sensed signals for control and protection.
Because of the ESR and ESL of the output capacitance, the output voltage is given by
0
( ) ( ) ( ) ( )
( ) 1( ) ( )
o ESR ESL C
t
cc c
v t v t v t v t
di ti t ESR ESL i t dt
dt C (1.1)
Figure. 1.4. shows an illustration of output voltage deviation during step down load current
transient [A31].
,L CV
tdelV
ESRV
ESLV
1I
2I
transtdelayt
oI
oI
oV
Figure. 1.4: Illustration of output voltage overshoot during step-down load transient.
The deviation in the output voltage due to a step down or step up load transient is given by
[A19, A31]
,o ESR ESL tdel L C
oo tdel o
trans
v v v v v
I LI ESR ESL v I
t C (1.2)
7
where
2 1oI I I is the load current variation
transt is the transient time
delt is the delay in the response of the controller and is proportional to the bandwidth of the
closed loop (assuming no adaptive scheme is used to reduce this delay).
tdelV is the voltage deviation associated with the delay in the response of the controller in the
loop to the load transient.
The transient voltage drop due to ESL is due to the inherent inductance of the capacitor and is
given by
oESL
trans
IV ESL
t (1.3)
The transient voltage drop due to the inherent resistance of the capacitor is given by
ESR oV I ESR
(1.4)
This voltage deviation is sufficiently large and cannot be ignored. This can be reduced by
selection of capacitors with very low ESR value.
The transient voltage deviation due to power stage output filter is given [A33] as follows
,L C o
LV I
C (1.5)
This can be reduced by selection of a large capacitor ( C ) or small inductor ( L ). However,
space limitations and cost limit the maximum capacitor value and cannot be increased further.
Also, the inductor cannot be reduced less than the value given by Eq. (1.6) which is the
minimum inductor value for the operation of buck converter in Continuous Conduction Mode
8
(CCM). Moreover, reducing the inductor value will result in increasing the power conduction
losses (lower efficiency).
( ,1 )
2
ocrit
o s
V max D DL
I f (1.6)
The transient voltage due to closed loop control delay ( tdelV ) is caused by the closed loop
control delay time which is the total delay time because of the controller bandwidth delay, and
the control logic component delays until the time when the appropriate switch is turned ON or
OFF.
The time delay delayt is a function of the switching frequency, controller bandwidth, delay and
controller and driver logic speed (assuming no adaptive scheme is used to reduce this delay). A
larger closed loop bandwidth results in a smaller time delay. This reduces the voltage deviation.
Thus, there is a motivation to increase the control loop performance without increasing the
switching frequency so that there is an improvement in dynamic performance without decrease
in efficiency, and without adding additional capacitors that increase the space and cost. This
dissertation research work proposes adaptive control techniques that improve the dynamic
performance of power converters without addition of extra capacitors (which would result in
increased size), and without increasing the steady state switching frequency of the power
converter (since increasing the steady-state switching frequency would reduce the efficiency).
Though the methods presented in this dissertation research work are discussed for a DC-DC
buck power converter, these methods can be expanded and applied to any switched power
converter topologies. Each chapter in this dissertation includes introduction section that is related
to the specific concept presented in that chapter.
9
1.4. Dissertation Outline
Chapter 2 proposes a Sensorless Adaptive Voltage Positioning (SLAVP) control scheme in
order to realize Adaptive Voltage Positioning (AVP) control without the need for load or
inductor current sensing and high-resolution high-speed ADC. The proposed control scheme
improves the dynamic performance of the converter with the elimination of the need for high-
speed and accurate sensing and sampling of currents. The dynamic modeling of the proposed
control scheme is also presented.
Chapter 3 proposes an adaptive digital Proportional Integral Differential (PID) compensator in
order to improve the dynamic performance of the converter. The control law is a function of the
magnitude change in the error signal and its peak value during dynamic transients. The proposed
AD-PID controller adaptively detects the peak value of the error signal which is a function of the
transient nature and magnitude, and utilize it in the control law such that no ocillations are
generated as a result of the adaptive operation. As a result, the dynamic output voltage deviation
and the settling time of the output voltage are reduced.
Chapter 4 proposes a novel Compensator Error Observe and Modulate method (CEO&M) for
online closed-loop-compensator auto-tuning of digital power controller. The proposed method is
relatively simple and does not require the knowledge and/or measurement of the power stage or
closed-loop frequency response. Moreover, the proposed method does not depend on
conventional design methods and the associated rule of thumb design criteria in order to tune
closed-loop feedback controllers of power converter for high, and possibly optimum, dynamic
performance.
10
Chapter 5 proposes two dynamic variable frequency control schemes that vary the frequency
of power converter as a function of the error signal. The proposed controller varies the switching
frequency of the converter, higher or lower than the steady-state frequency, during the transient
as a function of peak and magnitude of error signal depending on the amount and type of the
transient. The experimental results show the improvement in the dynamic performance of the
power converter.
A summary of the conclusions of this work and the directions of future related research work
are given in Chapter 6.
11
CHAPTER 2
SENSOR LESS ADAPTIVE VOLTAGE POSITIONING (SLAVP) CONTROL
2.1. Introduction
Adaptive Voltage Positioning (AVP) control has been used in DC-DC power converter
applications, especially in those converters powering high speed Integrated Circuits (ICs) such as
microprocessors, in order to achieve smaller dynamic output voltage deviation while at the same
time using less output filter capacitance for the power converter [B1, B2, B6-B10,B48]. The use
of AVP control has been motivated by the increased dynamic current slew rate and/or magnitude
of newly coming ICs and microprocessors, while at the same time requiring lower (down to less
than 1V) output voltage from the power converter with tighter output voltage regulation [B3-B5,
B41]. While the AVP control basic concept is relatively simple, its modeling and design for
optimal performance in order to achieve the maximum benefit is relatively complex [B6-B11].
Moreover, there are several proposed schemes presented in the literature to implement AVP
control along with their associated modeling and design guidelines [B6-B19].
The conventional AVP control schemes are based on sensing the load current value or the buck
converter’s inductor current value [B14-B19]. Figure. 2.1(a) shows an example of a conventional
AVP control realization assuming a closed loop digital controller implementation. As illustrated
in Figure. 2.1(b), the AVP control slightly adjust the output voltage of the power converter based
on the load current such that the output voltage is slightly higher when the load
12
current is lower and is slightly lower when the load current is higher. The AVP control sets the
output voltage to the maximum allowed output voltage ( o maxV ) when the load current is at its
minimum value ( o minI ), it sets the output voltage to the minimum allowed output voltage
( o minV ) when the load current is at its maximum value ( o maxI ), and it sets the output voltage to
its middle value ( o midV ) when the load current is at its middle point value ( max min 2o oI I )
[B10]. This provides a larger allowable margin for the output voltage to overshoot when a load
current step-down occurs, and provides a larger allowable window for the output voltage to
undershoot when a load current step-up occurs. Based on this behavior, even if the AVP control
design is not optimal, as long as the dynamic response of the output voltage is free of oscillations,
using the AVP control is advantageous, and will lead to reduced dynamic output voltage
deviation.
Nowadays, the AVP control is being used for special high end applications, mainly for buck
power converters that are used to power microprocessors, where the cost and design complexity is
tolerable. However, AVP control use is potentially advantageous to any power converter
application. Therefore, it is desired to obtain a lower cost and simpler realization that can be used
for wider range of applications.
The use of digital controllers, as an alternative to analog controllers, for power converter
applications have increased in the last few years because of several potential advantages. These
advantages include the digital controllers ability, and easiness to implement sophisticated
algorithms, and laws to improve dynamic and efficiency performances of power converters, they
are easier to be reconfigured and scaled compared to their analog counterpart, and they can
potentially reduce or eliminate the controller component variations and sensitivity that affect the
13
controller performance [B20-B37, B42-B45]. However, there are several challenges associated
with using digital controllers in power converters, to mention a few, the resolution limitation of
digital controllers and the size, cost and power consumption incurred from the required high-
speed high-resolution Analog-to-Digital Converters (ADCs) and Digital Pulse Width Modulators
(DPWMs). The technological advancement in digital circuit design and process features and
performance along with newly proposed digital control schemes is resulting in alleviating such
challenges with time.
As it can be observed from Figure. 2.1(a), AVP control realization as a part of a fully digital
controller implementation for a power converter requires a high-resolution and high-speed ADC
for the load or inductor current sampling. The performance of the current ADC will affect the
AVP control performance, and hence, it will affect the dynamic output voltage deviation. Several
sensorless control schemes have been discussed in the literature over the years such as those in
[B25, B33, B38-B40, B46, B47], among others. However, none of these is for AVP control.
In this chapter, a sensorless AVP (SLAVP) control scheme is presented. The SLAVP control
eliminates the need for load current sensing and the associated high-speed high resolution ADC in
digital controller implementation. It also does not require any additional voltage and/or current
sensing or ADC. The presented SLAVP control requires minor addition to an existing basic
digital controller with voltage-mode closed-loop control. Moreover, the low cost realization of the
presented SLAVP control makes it more possible to utilize the SLAVP in a wider range of power
converter applications with lower cost and simpler design.
14
Su
Sl
Lo
CoDrivers
Latches
D
D1Io
+
-
Vo
iL
Vin
Closed Loop
Compensator
DPWM
Modulator
Vref
e compV
D
Digital Controller with Conventional AVP
(Example of a Conventional Method)
+-
ADC1
ADC 2Gain/
Compensation
(a)
maxoI
minoI
maxoV
minoV
o m idV
Output Current
Output Voltage
Without AVP
Output Voltage
With AVP
o m idV
(b)
Figure. 2.1: (a) DC-DC buck converter with one implementation type of conventional AVP
control and (b) Conventional AVP control waveforms.
Section 2.2 introduces the basis of the SLAVP control. Section 2.3.1 presents the basic
SLAVP control law derivation and hardware realization. Section 2.3.2 and Section 2.3.3 present
the control laws of the SLAVP under variable input and output voltages of the power converter.
15
The effect and analysis of components’ DC resistance tolerances and input voltage change on the
SLAVP control are discussed in Section 2.4. A proof-of-concept experimental prototype results
are presented in Section 2.5, and dynamic modeling analysis is discussed in Section 2.6. The
summary is given in Section 2.7.
2.2. Sensorless Adaptive Voltage Positioning Control Basis
The controller duty cycle D , or equivalently the compensator’s output error signal e compV , is a
function of the power converter’s load current. For a DC-DC buck converter, the duty cycle of the
controller increases as the load current increases because of the additional voltage drop between
the input and the output at higher load current, and in order to deliver the necessary energy for a
regulated output voltage. This behavior can be approximated by the following equation assuming
that the power converter has an equivalent resistance, .eqR , between the input and the output:
. .( )
o o eq o eqoideal v drop o
in in in
V I R I RVD D D I
V V V
(2.1)
Where inV is the input voltage of a DC-DC buck converter, .eqR is the equivalent resistance
between the ideal input voltage source and the output voltage at the output capacitor, idealD is the
ideal duty cycle for a lossless DC-DC buck converter and ( )v drop oD I is the additional duty cycle
caused by resistive voltage drop which is a function of the output current.
16
(a)
(b)
Figure. 2.2: DC-DC buck converter duty cycle plots as a function of load current, input voltage,
and output voltage to illustrate duty cycle linearity (a) for different input voltages and (b) for
different output voltages.
Figure. 2.2 shows plots of Eq. (2.1) for an example design with . 30eqR m . The plots shows
the duty cycle as a function of the load current, input voltage and output voltage variables. It can
be observed that the duty cycle is linear as a function of the three variables. Figure. 2.3(a) shows a
theoretical plot for the output voltage vs. load current for a power converter with AVP control,
which agrees with what is described in the previous section and Figure. 2.1. Figure. 2.3(b) shows
a theoretical plot for the output voltage vs. D for a power converter with AVP control which
17
agrees with the above description of the relation between the load current and D It can be
observed that a sensorless AVP (SLAVP) control can potentially be realized if the appropriate
SLAVP control law as a function of D (or e compV ) is derived. Such SLAVP control law is
expected to have the theoretical waveforms as shown in Figure. 2.4.
oV
o LI or I
maxoV
minoV
maxoIminoI
(a)
oV
e compD V
maxoV
minoV
1mxD 2mnD
(b)
Figure. 2.3: (a) A theoretical plot for the output voltage vs. load current for a DC-DC buck
power converter with AVP control and (b) a theoretical plot for the output voltage vs. D for a
DC-DC buck power converter with AVP control.
18
1mxD
2mnD
maxoI
minoI
maxoV
minoV
Output Current
Duty Cycle
Or
Compensator Error Signal
Output Voltage
With SLAVPo m idV
Figure. 2.4: Theoretical SLAVP control waveforms.
2.3. SLAVP Control Law Derivation and Hardware Realization
This section shows the SLAVP control law under different input and output voltage
conditions.
2.3.1. SLAVP Control Law with Fixed Input and Output Voltages
It can be shown that based on Figure. 2.3(b), the following basic SLAVP control law can be
obtained:
min max1 1 max
2 1
1 max
2 1
1 max
( ) ( )
( )
( )
o oo SLAVP mx o
mn mx
o spec
mx o
mn mx
mx o
V VV D D D V
D D
VD D V
D D
D D V
(2.2)
Where min max
2 1 2 1
o speco o
mn mx mn mx
VV V
D D D D, min maxo o nom oV V V and 1 2mx mnD D
maxoV and o minV values are known based on given specifications and requirements for a design.
They are given by:
19
max minmax
2 2
o speco oo o nom o nom
VV VV V V (2.3)
max minmin
2 2
o speco oo o nom o nom
VV VV V V (2.4)
Where o specV is the desired AVP control voltage window centered around o nomV based on
design specifications.
The relationship between Eq. (2.2) and the load current is as explained earlier in Figure. 2.3
and Figure. 2.4. All the parameters in Eq. (2.2) are known constants for a given design except D
which is an available variable in any conventional controller of a power converter. D value varies
as a function of the load current.
As apparent from Figure. 2.3 and Figure. 2.4, 2mnD can be obtained by setting the operating
point of the power converter at o maxI and o minV and 1mxD can be obtained by setting the
operating point of the power converter at o minI and o-maxV .
As the load current varies from o minI (which is usually zero amperes) to o maxI , the duty
cycle D varies from 1mxD to 2mnD . This will cause the result of Eq. (2.2) to vary from o minV to
o maxV , resulting in SLAVP control realization.
20
Su
Sl
Lo
CoDrivers
Latches
D
D1Io
+
-
Vo
iL
Vin
Closed Loop
Compensator
DPWM
Modulator
ADC
Vref
e compV
D
SLAVP
Controller
Digital Controller with SLAVP
Figure. 2.5: Digital System Block Diagram for SLAVP control Hardware Realization.
Figure. 2.5 shows the block diagram of the SLAVP hardware realization by using a digital
controller. The SLAVP control loop simply adjusts the closed loop voltage reference based on
Eq. (2.2) and as a function of e compV which is used to generate the DPWM duty cycle D . It can
also be observed that the current sensing and sampling and high-resolution high-speed ADC is
eliminated, resulting in less hardware requirements and hence lower size and cost. The SLAVP
controller in Figure. 2.5 involves Eq. (2.2) and it also involves setting limits on Eq. (2.2) results.
If for some reason the result of Eq. (2.2) is larger than maxoV , the controller will limit the value
of the voltage reference ( refV ) that is provided to the voltage mode compensator to a value that is
equal to o maxV . Similarly, if for some reason the result of Eq. (2.2) is smaller than o minV , the
controller will limit refV to a value that is equal to o minV . Therefore, refV will always satisfy
min maxo ref oV V V .
2.3.2. SLAVP Control Law with Variable Input Voltage
There are two types of power converters in terms of input voltage. The first type is constant
input voltage power converters and the second type is variable input voltage (either with narrow
21
range or wide range) power converters. A given system, such as a computing platform system, for
example and not for limitation, may include both types.
The SLAVP control law that is presented in the previous section, namely Eq. (2.2), is
apparently suitable for power converters with fixed input voltage. This limits the application of
Eq. (2.2) to converters with fixed input voltage. If the input voltage is varied within significant
range, the output voltage will be limited by the SLAVP controller to o maxV or o minV . If the input
voltage is slightly varied, the SLAVP controller with Eq. (2.2) may still work to a certain degree
(see Section 2.4.2) but it will not perform as expected. The input voltage change impacts Eq. (2.2)
mainly because for different input voltage values, there are different sets of 1mxD and 2mnD
values.
For a DC-DC buck converter, the duty cycle is a linear function of the input voltage as
discussed in Section 2.2. For practical converters with variable input voltage, including those with
conventional AVP control, the input voltage is sensed and sampled by an ADC that is relatively
slower than the one used to sample the output voltage when digital controller is used. Such
sensing is usually needed for reasons such as protection and/or feed forward control.
If 1mxD and 2mnD are obtained at the nominal input voltage in nomV , then the new values of
1mxD and 2mnD at any input voltage value can be obtained as follows:
1 1( ) ( )in nommx in mx in nom
in
VD V D V
V
2 2( ) ( )in nommn in mn in nom
in
VD V D V
V
Therefore, the SLAVP equation for any input voltage value becomes:
22
2 ( )o SLAVPV Dmin max
1 max
2 1
( )o o in nommx o
in nom in nom inmn mx
in in
V V VD D V
V V VD D
V V
min max1 max
2 1
( )o omx o
mn mx
V VD D V
D D
1 max( )mx oD D V
1 max( )mx oD D V
min max1 max
2 1
( )( )
o o in nomin mx o
in nom mn mx in
V V VV D D V
V D D V
1 maxin in nom mx oV D V D V
2 ( )o SLAVPV D maxin oV D V
(2.5)
Where in nom inV V , in nomV is the nominal input voltage of the power converter at which
1mxD and 2mnD values are measured, inV is the actual input voltage of the power converter,
1 in in nomV V , min max
2 1 2 1( ) ( )
o speco o
in nom mn mx in nom mn mx
VV V
V D D V D D, and 1in nom mxV D .
The SLAVP control law of Eq. (2.5) with the input voltage consideration is relatively simple
since , and maxoV are constants for a given design even under variable input voltage and
variable load current. Eq. (2.5) becomes equal to Eq. (2.2) when the input voltage is constant and
satisfies in in nomV V .
23
2.3.3. SLAVP Control Law with Variable Output Voltage
Some applications such as Voltage Regulators (VRs) for powering microprocessors have
adjustable output voltage for example via the Voltage Identification Code (VID). In such
applications, the output voltage varies within a given range.
If 1mxD and 2mnD are obtained at the nominal output voltage o nomV and at the nominal input
voltage in nomV , then the new values of 1mxD and 2mnD at any output voltage and input voltage
values can be obtained as follows:
1 1( , ) ( , )o in nommx in o mx in nom o nom
in o nom
V VD V V D V V
V V
2 2( , ) ( , )o in nommn in o mn in nom o nom
in o nom
V VD V V D V V
V V
Therefore, the SLAVP equation for any output voltage and input voltage values becomes:
1
12 1
2 1
3 1 max
2 1
( ) ( )mx
mxmn mx
mn mx
in nom Do spec oo SLAVP mx o
in o nom Din nom D in nom Domn mx
in o nom D o nom D
VV VV D D D V
V VV VVD D
V V V
1
12 1
2 1
1 max
2 1
( )mx
mxmn mx
mn mx
in nom Do specin omx o
o in o nom Din nom D in nom D
mn mx
o nom D o nom D
VVV VD D V
V V VV VD D
V V
1
1
1 maxmx
mx
in nom Dinmx o
o o nom D
VVD D V
V V
max
ino
o
VD V
V
24
2
o specino VID
o
VVD V
V
3( )o SLAVPV D in
o
VD
V (2.6)
Where
2 1
2 1
2 1mn mx
mn mx
o spec
in nom D in nom D
mn mx
o nom D o nom D
V
V VD D
V V
, 1
1
1mx
mx
in nom D
mx
o nom D
VD
V,
2
o spec
o VID
VV ,
1mxo nom DV and 1mxin nom DV are the nominal output voltage and nominal
input voltage of the power converter at which 1mxD value is measured, 2mno nom DV and
2mnin nom DV are the nominal output voltage and nominal input voltage of the power converter at
which 2mnD value is measured, and o VIDV is the desired nominal output voltage.
The SLAVP control law of Eq. (2.6) with the input voltage and output voltage consideration is
relatively simple since and are constants for a given design even under variable output
voltage, variable input voltage and variable load current. is just the value of the output voltage
( o o VIDV V ) plus half the value of the allowed SLAVP window ( o specV ). Eq. (2.6) becomes
equal to Eq. (2.2) when the input voltage is constant and satisfies in in nomV V and when the
output voltage is constant and satisfies o o nomV V .
Consider an example power converter design with output voltage range 1.3V - 1.8V and input
voltage 8V – 10V. Then o nomV can be selected to be equal to 1.5V and in nomV can be selected
to be equal to 9V. At these values, 1mxD and 2mnD values can be determined and also with the
25
knowledge of o specV , and values can be obtained. Eq. (2.6) can be used and will be valid
when the input voltage and output voltage values are not at their nominal values. This is because
the equation is scaled (adapted) as a function of the input and output voltages.
Su
Sl
Lo
CoDrivers
Latches
D
D1Io
+
-
Vo
iL
Vin
Closed Loop
Compensator
DPWM
Modulator
ADC
Vref
e compV
D
SLAVP
Controller
Digital Controller with SLAVP
Vo-VID
(a)
Su
Sl
Lo
CoDrivers
Latches
D
D1Io
+
-
Vo
iL
Vin
Closed Loop
Compensator
DPWM
Modulator
ADC
Vref
e compV
D
SLAVP
Controller
Digital Controller with SLAVP
Vo-VID
ADC
(b)
Figure. 2.6: Digital System Block Diagram for SLAVP control Hardware Realization which
accounts for both variable input voltage and variable output voltage (a) SLAVP controller with
variable output voltage and (b) SLAVP with variable input and output voltages.
26
Based on SLAVP Eq. (2.6), which accounts for both variable input voltage and variable
output voltage, Figure. 2.5 block diagram is adjusted as shown in Figure. 2.6.
2.4. Effects of Component DC Resistance Tolerance and Input Voltage Variation
2.4.1. Analysis of DC Resistance Tolerance Effect on the SLAVP Window:
Power stage components DC resistances values have tolerances. These tolerances may affect
the performance of the AVP control loop. As mentioned earlier, the digital controller with the
proposed SLAVP controller clips and limits the output voltage to a window between maxoV and
minoV even if the SLAVP control law equation resulted in a voltage outside this window, which
may result because of components resistive tolerances. While the voltage is not allowed to go
outside this limited window under such condition, the AVP control loop performance may be
degraded. The performance degradation is because the output voltage may not be exactly at the
desired value, within the AVP window, for given load current values.
It should be noted here that the same issue also exists in conventional current sensing based
AVP controllers. For example, the tolerances in the DC resistance (DCR) of the inductor may
affect the accuracy of the sensed current and as a result may affect the AVP control accuracy and
degrade its performance. Other sources that may affect the current sensing accuracy (in
conventional current sensing based AVP controllers) is the current processing circuits (current
amplifiers) accuracy and mismatches and noise. Calibration and using components with lower
tolerances are usually the way to reduce this possible performance degradation.
27
In the SLAVP control, a change in .eqR ( .eqR ) will cause a change in the duty cycle with an
amount of:
.( )o eq
in
I RD
V (2.7)
By using Eq. (2.7) and Eq. (2.6), it can be shown that the error in the SLAVP window as a
result of .eqR is given by:
.
.
( )( )
o eq
error eq
o
I RSLAVP R
V (2.8)
Eq. (2.8) indicates that the maximum error because of a .eqR will occur at the maximum
load current when the output voltage is near to minoV and the error decreases to zero as the load
current decreases to zero and the output voltage approaches maxoV .
For example, for a DC-DC buck power converter with 1.5oV V , SLAVP window of 50mV
and 10% tolerance in .eqR of 30m , the maximum error at maximum load of 10A is about
2.4mV . Note that in this calculation 0.11 is used from the experimental section design
(see Section 2.5) as an example.
Given the fact that in SLAVP control, the current sensing and high-speed high-accuracy
analog to digital sampling is eliminated in a fully digital controller implementation, the SLAVP
control performance is acceptable even under large tolerance values. Moreover, the error caused
by these tolerances can be estimated based on Eq. (2.8) and can be accounted for in the design
with a design safety margin in the AVP window.
28
2.4.2. Analysis of Input Voltage Variation Effect on the SLAVP Window:
As mentioned earlier, especially for power converter applications with wide input voltage
variation range, the input voltage is usually sensed for functions such as feed forward control in
order to maintain optimized dynamic performance at different input voltage values.
The second and third forms of the SLAVP law, Eq. (2.5) and Eq. (2.6), can take care of the
input voltage variation effect on the SLAVP window based on input voltage sensing. However, if
the input voltage variation range is narrow, the SLAVP controller could be used without the need
for sensing the input voltage if some error in the SLAVP window is acceptable especially if the
input voltage range is narrow. It can be shown that the error in the SLAVP window as a result of
input voltage variation from its nominal value is given by:
.( ) ( )( )
( ) ( )
in nom in o o eq
error in
in nom in
V V V I RSLAVP V
V V (2.9)
For example, in the design given in the experimental section of this chapter (Section 2.5), the
error in the SLAVP window as a result of input voltage change to 9.5V from its nominal value of
9V while using Eq. (2.2) in the controller (which does not account for input voltage variation) is
approximately 6mV (assuming .eqR of 30m as an example). Eq. (2.9) has been verified
experimentally.
2.5. Proof-Of-Concept Experimental Prototype Results
A proof of concept prototype is built in the laboratory for verification and test of the SLAVP
control concept. The power stage is a single-phase DC-DC buck converter with the following
design specifications: Input voltage range of 8V-10V and nominal output voltage of 1.5V, output
29
inductor of 440nH , output capacitance of 3mF , switching frequency of 350KHz and full load
current of 10A.
Fully digital control hardware is used to implement the voltage mode feedback controller with
SLAVP control. The ADC has 7-bit resolution and takes 2.8M sample/second. The DPWM used
is with 10-bit resolution. The controller is implemented using Altera FPGA “Altera Cyclone II
EP2C35F672C6”. The voltage mode controller is with a PID (Proportional-Integral-Derivative)
digital compensator and the SLAVP control is realized as described earlier in this chapter.
The desired SLAVP window is 50mV. Based on this, the following values are obtained:
1 0.168mxD , 2 0.24mnD , 0.11 , 0.991,and 0.025o VIDV .
In order to verify the linear relationship of the duty cycle as a function of the input voltage
and output voltage for the prototype, 2mnD values are measured for input voltage range of 8V-
10V and output voltage range of 1.3V-1.8V. The results are plotted as shown in Figure. 2.7(a)
and Figure. 2.7(b), respectively. Note that there is only one 2mnD value and one 1mxD value used
in the digital controller and Eq. (2.6) will scale automatically for different input and output
voltages, however, Figure. 2.7 is shown here in order to verify the bases used to obtain Eq. (2.6).
Moreover, Figure. 2.7(c) shows a plot of the duty cycle as a function of the load current. As
expected, the relationship between the duty cycle and the load current is linear.
30
(a) (b)
(c)
Figure. 2.7: Experimental results to show the linear relationship (within the range of operation)
of duty cycle as a function of the input and output voltages and load current for the experimental
prototype (a) 2mnD as a function of input voltage at 1.5V output voltage and 10A load current,
(b) 2mnD as a function of output voltage at 9V input voltage and 10A load current and (c) D as
a function of load current at 9V input voltage.
Figure. 2.8 through Figure. 2.11 show experimental results of the prototype under dynamic
load transients for different input and output voltages for the controller with SLAVP.
Figure. 2.8(a) shows the experimental results under the nominal input voltage and output
voltage values (9V, 1.5V) and under dynamic load transients from zero load to full load.
31
Figure. 2.8(b) shows the experimental results when the input voltage is increased to 10V. It can
be observed that the SLAVP controller performs as expected with 50mV SLAVP window.
50mV
10A
(a)
50mV
10A
(b)
Top Trace: Output Voltage (50mV/div, 2ms/div., AC coupled) and Bottom Trace: Load Current
(3A/div., 2ms/div.).
Figure. 2.8: Experimental results of the prototype with SLAVP under dynamic load transients of
0A-10A-0A (full load range from minimum to maximum) with 1.5oV V and SLAVP window of
50mV (a) at 9inV V and (b) at 10inV V .
32
50mV
10A
(a)
50mV
10A
(b)
Top Trace: Output Voltage (50mV/div, 2ms/div., AC coupled) and Bottom Trace: Load Current
(3A/div., 2ms/div.).
Figure. 2.9: Experimental results of the prototype with SLAVP under dynamic load transients of
0A-10A-0A (full load range from minimum to maximum) with 9inV V and SLAVP window of
50mV (a) at 1.7oV V and (b) at 1.4oV V .
Figure. 2.9 shows the experimental results when the output voltage is varied from 1.5V to
1.7V and 1.4V. The results show that the SLAVP controller is able to perform as expected under
different output voltage values.
33
Figure. 2.10 shows the results when the load transient is not from zero load (0A) to full load
(10A), but when it is from 4A-7A-4A and 0A-8A-0A for a given input voltage and output
voltage values. The results show that the SLAVP controller is able to perform as expected under
different input voltage values.
15mV
3A
(a)
40mV
8A
(b)
Top Trace: Output Voltage (50mV/div, 2ms/div., AC coupled) and Bottom Trace: Load Current
(3A/div., 2ms/div.).
Figure. 2.10: Experimental results of the prototype with SLAVP window of 50mv and under
dynamic load transients of (a) 4A-7A-4A at 1.5oV V and 9inV V and (b) 0A-8A-0A at
1.3oV V and 8inV V .
34
50mV
10A
(a)
50mV
10A
(b)
Top Trace: Output Voltage (50mV/div, 20µs/div., AC coupled) and Bottom Trace: Inductor
Current (3A/div., 20µs /div.).
Figure. 2.11: Experimental results of the prototype with SLAVP window of 50mv and under 0A-
10A-0A dynamic load transients showing zoomed in view of output voltage and inductor current
during (a) load step-up transient and (b) load step-down transient.
Figure. 2.11 shows a time-scale zoomed in view (with 20µs/div. time scale) during load step-
up and load step-down transients. The figure shows the results for the output voltage and
inductor current. It can be observed that for the design of this chapter, the output voltage reaches
35
the new output voltage value in about 10µs to 20µs (less than 7 switching cycles). Different
designs, for example a design with smaller inductor value and/or higher switching frequency,
may result in a faster speed. The results indicate that the performance of the SLAVP controller
are comparable to those presented in [B6] and [B7] for the conventional AVP control. This can
be achieved with appropriate control loops design.
It can be observed from the experimental results that the SLAVP controlled output voltage
scales within the SLAVP window according to the load current value without the need to sense
the load or inductor current.
It may be necessary to mention that Figure. 2.8 through Figure. 2.11 show only the AC
component and not the DC component of the output voltage waveforms as indicated on the
figures in order to make the SLAVP window clear and any change in it visible. This is because
the SLAVP window represented by the AC component is much smaller (50mV) than the DC
component (1.3V – 1.7V).
2. 6. Dynamic Modeling Results
This section presents dynamic modeling work results for power converter with SLAVP
control. Figure. 2.12 shows the small signal control block diagram with SLAVP control. An
equivalent small signal control block diagram with SLAVP control to that of Figure. 2.12 is
shown in Figure. 2.13. In order to obtain and simplify the two equivalent block diagrams, the
concept presented in [B7] is utilized. It can be observed from the block diagrams how the duty
cycle is fed back to the input of the compensator and used as the reference for the voltage loop,
forming the SLAVP control loop. This loop replaces the current loop in conventional AVP
control.
36
io
d
vc
vo
β
Z0
Gvg
Gvd
Fm
Gdio
Gdg
Gcom
H
vg=vin
Figure. 2.12: Small signal control block diagram with SLAVP.
io
vg=vin
d
vc
vo
Z0
Gvg
Gvd
Fm
Gdio
Gdg
Gcom
1+Gcom-1β
Td
Tv
H
Figure. 2.13: Equivalent control block diagram to that shown in Figure. 2.12.
The transfer functions used in the small signal model are as shown below.
- Output current to output voltage transfer function:
. 2
2
(1 ).(1 )( )
( )( )
1
o L esro eq
o
o o
s s
v sZ s R
i s s s
Q
- Input voltage to output voltage transfer function:
37
2
2
(1 )( )
( )( )
1
o esrvg
g
o o
s
v sG s D
v s s s
Q
- Duty cycle to output voltage transfer function:
2
2
(1 )( )
( )( )
1
o esrvd g
o o
s
v sG s V
d s s s
Q
- Output current to duty cycle transfer function:
(1 )( )
( )( )
(1 )o
o esrdi
o g
R
s
Rd sG s
si s V
- Input voltage to duty cycle transfer function:
( )( )
( )(1 )
o odg
g g
R
D R C sd sG s
sv s V
- Compensator transfer function: ( )comG s .
- PWM Modulator transfer function/gain: ( )mF s .
- Output voltage sensor transfer function/gain: ( )H s .
38
Where 2( )
oo o
o o o esr
Rf
L C R R,
12
.R R
o o
fR C
, 1
2esr esr
esr o
fR C
,
.2
eq
L L
o
Rf
L, and
1
( )oo esr o
o
QL
R CR
.
esrR is the output capacitor ESR and o o oR V I is the load resistance.
From Figure. 2.13, the voltage loop gain and the SLAVP loop gain can be obtained as:
( ) ( ) ( ) ( ) ( )v m vd comT s F s G s H s G s
( ) ( ) 1 ( )d m comT s F s G s
The output impedance transfer function is given by:
( ) (1 ( )) ( ) ( ) ( ) ( ) 1 ( )( )
1 ( ) ( )
oo d m di vd com
oc
d v
Z s T s F s G s G s H s G sZ s
T s T s (2.10)
In order to achieve a constant impedance design with 50mV window and 10A load range, it is
desired to achieve ( ) 50 10 5ocZ s mV A m . All the other terms in Eq. (2.10) are known since
they can be calculated from the power stage and controller parameters. Therefore, it is desired to
design a compensator ( )comG s that will result in ( ) 5ocZ s m . Note that value is based on
Eq. (2.6).
The design of this compensator is relatively simple. A single-zero two-pole compensator is
sufficient. The zero is placed at the resonant frequency of and one of the two poles is placed at
zero frequency (integrator) or at low frequency in order to boost the low frequency gain. The
second pole is placed at frequency that is much higher than esrf . The location of the second pole
39
is flexible and can be used together with the compensator gain to control the bandwidth and
phase margin. For the design example presented in Section 2.5, 354of Hz and with
5esrR m , 10.61esrf kHz . Therefore, the compensator zero can be placed at 354Hz and the
non-zero pole can be placed at 55.7kHz. ( )dT s crossover frequency should be placed close to the
crossover frequency of ( )vT s or higher.
0.1 1 10 100 1 103
1 104
1 105
1 106
1 107
100
0
100
180
135
90
45
0
|Tv (s)|
|Td (s)|
Phase of Tv (s)
Phase of Td (s)
20 log Tv i n
20 log Td i n
arg Tv i n
deg
arg Td i n
deg
n
2
0.1 1 10 100 1 103
1 104
1 105
1 106
1 107
180
140
100
60
20
20
60
100
140
180
Angle of Zoc (s)
arg Zoc i n
deg
n
2
Figure. 2.14: Bode-plots for ( )vT s and ( )dT s .
Figure. 2.14 shows the bode-plots for ( )vT s and ( )dT s and Figure. 2.15 shows the output
impedance plot. It can be observed that a constant impedance design is achieved. The crossover
frequencies of ( )vT s and ( )dT s are about 90kHz with phase margin of 30º, and 200kHz with
phase margin of 100º, respectively. Note that the 200kHz crossover frequency of ( )dT s for the
SLAVP control loop is comparable to (about the same) the crossover frequency of the AVP
current loop in [B7] for the 300kHz switching frequency design (see Figure. 19(b) in [B7]).
40
0.1 1 10 100 1 103
1 104
1 105
1 106
1 107
0
1 103
2 103
3 103
4 103
5 103
6 103
7 103
8 103
50
25
0
25
50
75
100
|Zoc (s)|
Angle of Zoc (s)
Zoc i n
arg Zoc i n
deg
n
2
Figure. 2.15: Output impedance plot
2.7. Summary
The chapter presents a method to realize adaptive voltage positioning control for power
converters with no need for current sensing, namely, the SLAVP control. Moreover, the
presented SLAVP control eliminates the need for high-speed and accurate current sensing and
eliminates the need for high-resolution high-speed ADC in a digital controller implementation,
and therefore, it reduces the associated size and cost and it reduces sensing and sampling power
losses. Moreover, the presented SLAVP control simplifies the design and implementation of
AVP control and therefore it can be used for wide range of applications and not only for high-
end applications like powering microprocessors. In addition, SLAVP control can be easily added
to controllers with conventional voltage mode closed loop control without significant hardware
requirements and cost increase unlike conventional AVP controllers.
The SLAVP control laws (equations) are derived for several power converter design cases.
These are power converters with fixed input and output voltages, power converters with a range
of variable input voltage and fixed output voltage, and power converters that have a range of
41
variable input voltage and output voltage. The SLAVP control law and controller adjust the
output voltage of the power converter within a specified range based on the readily available
controller’s duty cycle or compensated error signal/voltage. This is possible because the duty
cycle of a switching power converter is a function of load current.
The SLAVP control theoretical analysis and design are presented in this chapter and
experimentally verified by preliminary proof-of-concept prototype experimental results that
strongly agree with the theoretical analysis. Future work includes implementation to high-current
multiphase power converters and other power converter topologies and more thorough dynamic
modeling and analysis.
42
CHAPTER 3
ADAPTIVE DIGITAL PID (AD-PID) CONTROLLER
3.1. Introduction
Digital power control has made the implementation of many sophisticated control strategies
easier and possible, which can result in significant improvement in the dynamic performance and
efficiency of power converters [C1-C6, C27]. Digital power control offers the flexibility of
adjusting the parameters of the control loop without the need for significant changes in the
hardware. Moreover, the digital controller’s components aging effects are negligible compared
with analog controllers. The aforementioned advantages, among others, have made digital power
controller a strong competitor to analog controllers in many power converter applications [C7-
C12].
The dynamic performance of power converters is critical in many applications. Modern
Digital Signal Processors (DSPs) including microprocessors operate with low supply voltages.
During the transients, the voltage deviation should be minimized for proper and safe operation.
This requires a very well designed closed loop controller which can respond quickly to the
dynamic transients and limit the overshoot/undershoot [C13-C17].
Figure. 3.1 shows a block diagram of a power converter with a digital controller. Figure. 3.2
shows the block diagram of a conventional Proportional-Integral-Derivative (PID) controller
[C18-C25]. The conventional PID controller parameters are usually designed using either the
43
bode-plot based methods or root-locus diagram based methods [C26]. Usually, a PID controller
is designed for particular power stage parameters [C27]. The PID controller is designed with a
specific safe bandwidth and gain and phase margins such that it maintains stable operation under
varying conditions and parameters such as load current, input voltage and components’ parasitic
variations. Such a safe design may affect and limits the dynamic performance of the system.
Sl
Lo
CoDrivers
Latches
D
D1Io
+
-
Vo
iL
Vin
DPWM
Modulator
e compV
D
ADC
Vref
Compensator
errorv
Su
Figure. 3.1: DC-DC buck converter with digital controller.
The values of Kp and Ki (in addition to Kd , the derivative constant) in the PID controller of
Figure. 3.2 determine the bandwidth, phase margin and gain margin of the power converter
closed loop system and hence the stability. In general, as Kp and Ki increase, the gain and
bandwidth of the system increase. Increasing the gain and bandwidth of the system above certain
values may cause instability during steady state operation and dynamic operation [C23].
However, during the dynamic transient time period, the allowable bandwidth can be increased in
order to achieve improved dynamic response [C23].
44
Vout
To
DPWM
dK
iK
pK
-1Z -1
Z
Vref
ADCerrorv
( )e compV z
Figure. 3.2: A conventional digital PID controller realization diagram.
Adjusting the compensator design or constants during transients may cause additional output
voltage ringing and overshoots/undershoots if not carefully implemented and if appropriate
adaptive strategy is not used. Moreover, the amount of improvement is based on the strategy
used in the adaptive PID scheme.
3.2. Background for The Proposed AD-PID Controller
The transfer function of a digital parallel PID controller as shown in Figure. 3.2 is as follows:
1
1( ) (1 )
1
iPID p d
KG z K K z
z (3.1)
The values of Kp , Ki and Kd determine the controller design, performance and stability. A
large proportional gain (Kp) results in a large change in the output of the PID controller for a
small change in error. In terms of the frequency response, it increases the gain of all frequency
components. The integral constant (Ki) decreases the settling or recovery time and helps in
reducing the steady state error. In terms of frequency response, it is equivalent to a low pass
filter, i.e., it has high gain at low frequencies and low gain at high frequencies. The derivative
term (Kd) slows the rate of change of the PID controller output. In terms of frequency response, it
has high gain at higher frequencies and low gain at lower frequencies [C31]. Figure. 3.3(a)
45
shows example bode plots for different values of Kp . From this it can be observed that as Kp
increases, the bandwidth of the system increases. Figure. 3.3(b) shows the example bode plots
for different values of Ki . From this, it can be observed that as Ki increases, the low frequency
component gain increases. Figure 3.3(c) shows example bode plots when both Kp and Ki values
increase simultaneously.
In general, the higher the loop bandwidth, the better the transient performance of the closed
loop system given that stability is still maintained [C12]. The theoretical limit on the bandwidth
is half (50%) of the switching frequency. However, in practical designs, the bandwidth of the
loop is usually designed to be not more than 20-30% of the switching frequency, because a
bandwidth higher than this has very low noise susceptibility and may lead to instabilities [C23].
During transients, the bandwidth can be increased to a higher value such that the transient
response is faster [C23]. If the higher bandwidth is used in steady state, the system may be
unstable.
Therefore, a better PID controller is the one which can have a higher bandwidth during the
transient to improve the transient performance (lower voltage deviation and shorter settling time)
of the system and yet maintain a lower bandwidth which makes the system stable during the
steady state operation. This concept is implemented in the proposed adaptive PID controller with
a special strategy.
46
(a) (b)
(c)
Figure. 3.3: Example bode-plots for different values of (a) Kp and (b) Ki and (c) Kp and Ki.
Figure. 3.4 shows a general diagram of an adaptive digital PID controller. Ki and Kp values are
adjusted by adjusting the values of α and β respectively. The equation for this Adaptive PID
controller is as follows:
1
1( ) (1 )
1e comp error error d errorV z v v K z v
z (3.2)
47
The values of and are not constant and are adaptively varied as a function of the error
signal value and its peak value as discussed in the next section. Section 3.3 presents the adaptive
control strategy used by the proposed AD-PID controller which smoothly transitions the PID
parameters between steady state period values and dynamic transient period values, thus
avoiding ringing and multiple overshoots/undershoots while reducing the power converter output
voltage deviation and settling time.
Vout
To
DPWM
dK
iK
pK
-1Z
Vref
ADC
-1Z
errorv
( )e compV z
Figure. 3.4: A general Adaptive digital PID controller realization diagram.
Several methods are discussed in the literature in order to adaptively regulate a PID
compensator or adaptively control the switching actions during dynamic transients [C18, C23,
C28-C30]. The complexity and practicality of these methods vary as the amount of improvement
varies. In addition, some of these methods are more sensitive to power stage parameters and
parasitic compared to others. Many of these methods pre assume given specific transient
magnitude and behavior which limits the achievable improvement to certain dynamic conditions.
This chapter presents an Adaptive Digital PID (AD-PID) controller that result in dynamic
performance improvement. The AD-PID uses a control strategy which smoothly transitions the
PID parameters between steady state period values and dynamic transient period values, thus
48
avoiding ringing and multiple overshoots/undershoots while reducing the power converter output
voltage deviation and settling time. This is achieved by dynamically detecting the peak value of
the error signal, which is a function of the transient magnitude and nature, and utilizes it together
with the error signal magnitude on cycle by cycle bases in a new adaptive PID control law.
Moreover, the AD-PID controller adaptive operation does not require sensing parameters that
does not exist in any conventional power controller. It only requires the knowledge of the output
voltage, nothing more, and it is not sensitive to power stage characteristics because of its
operation nature as will be discussed in this chapter. While other existing methods that are more
complicated and depend on sensing several parameters may result in larger dynamic response
improvement under given conditions, the AD-PID controller combines the simplicity and the
ability to achieve dynamic transient improvement.
Section 3.3 discusses the proposed AD-PID controller background. Section 3.3 presents the
AD-PID control law and algorithm. Section 3.4 presents the guidelines to determine the values of
parameters (Kp-trans, Ki-trans and Vthr ) for AD-PID algorithm implementation. Section 3.5 presents
the experimental prototype results while Section 3.6 presents a comparison with other non-linear
PID controllers. The summary is given in Section 3.7.
3.3. AD-PID Control Law and Algorithm
Figure. 3.5 shows theoretical waveforms that illustrate the proposed AD-PID controller
operation. The controller flowchart shown in Figure. 3.6 observes the error (verror) caused by the
difference between the output voltage of the power converter and the reference voltage as shown
in Figure. 3.1. Once verror is outside a very small window around zero (determined by the value
of threshold voltage, Vthr ), as a result of transient, the values of α and β (whose values are
Ki-steady and Kp-steady respectively before the start of transient or in other words during steady state)
49
are increased abruptly to a large value ( determined by Ki-trans and Kp-trans respectively, the
selection criteria of which will be given in Section 3.4) in order to increase the bandwidth and
speed of the closed loop system. The controller then watches the verror in order to detect its peak
value (Verror-peak) and the instant when it starts to decrease back towards zero as shown in Figure.
3.5 and Figure. 3.6.
0
error peakV
( )errorv n
( )errorv
( )errorv
i steadyK
i transK
p steadyK
p transK
error peakV
maxoI
minoI
Output Current
Output Voltage
out peakV
out peakV
( )outv t
Figure. 3.5: Illustration of the AD-PID controller operation.
50
No
Yes
Yes No
Start
i steadyK
p steadyK
i transK
p transK
i steadyK
p steadyK
( ).( )
errori trans i steady i steady
error peak
v nK K K
V
( ).( )
errorp trans p steady p steady
error peak
v nK K K
V
( 1) ( )error errorv n v n
( 1) ( )error errorv n v n
( )error thrv n V
Obtain the
value of error
signal
( )errorv n
( )error peak errorV v n
Figure. 3.6: Flowchart for the proposed adaptive controller.
51
, ( )
( ) , ( ) ( 1) ( )
( )( ) , ( ) ( 1) ( )
i steady error thr
error i trans error thr error error
error
i trans i steady i steady error thr error error
error peak
K v n V
v K v n V and v n v n
v nK K K v n V and v n v n
V
(3.3)
, ( )
( ) , ( ) ( 1) ( )
( )( ) , ( ) ( 1) ( )
p steady error thr
error p trans error thr error error
error
p trans p steady p steady error thr error error
error peak
K v n V
v K v n V and v n v n
v nK K K v n V and v n v n
V
(3.4)
The AD-PID controller starts to adjust α and β values gradually toward their original steady
state values (Ki-steady and Kp-steady respectively) by using Eq. (3.3) and Eq. (3.4), which utilize the
detected peak value of the verror (Verror-peak) in addition to its magnitude on a cycle by cycle bases.
It should be noted that Verror-peak value is different for different transient magnitudes and types
(ex. load current transient 1A-3A, load current transient 0A-7A, input voltage transient 8V-12V,
etc.), which is a unique aspect of the AD-PID controller. It means that the AD-PID controller law
adapts to different transient magnitudes and types. By this way, dynamic performance is
improved at different transient types and magnitudes without the need to sense any additional
variables other than the output voltage, which is readily sensed in any power controller.
From Eq. (3) and Eq. (4), it can be noted that the rate of change of α and β values are inversely
proportional to Verror-peak. Moreover, Verror-peak is detected adaptively in order to have a smooth
52
transition from high bandwidth (during transient-state) to low bandwidth system (during steady-
state).
It should be noted that if a fixed Verror-peak is used in Eq. (3) and Eq. (4) rather than a variable
Verror-peak that is adaptively detected, the values of α and β may not be equal to the desired (by
design) Ki-trans and Kp-trans at the peak instant of the error signal (observe the last part of each
equation, this is because |Verror(n)|/ |Verror-peak| will not be equal to one for all transient
conditions), which may result in instabilities and/or oscillation during transients and thereafter in
steady-state. But in the proposed method when Verror-peak is adaptively detected and varied in Eq.
(3) and Eq. (4), α and β will always be equal to the desired Ki-trans and Kp-trans at the peak instant
of the error signal. This provides the AD-PID controller with the ability to adapt and work well
under different magnitudes and types of transients. This is in fact one of the unique
characteristics of the proposed AD-PID controller in addition to the smooth transition it provides
between the transient-state and the steady-state operation.
3.4. AD-PID Control Law Design Guidelines
This section provides the design guidelines for the AD-PID control law constants.
Specifically, the selection of Kp-trans , Ki-trans and Vthr in Eq. (3.3) and Eq. (3.4) for a given design
of a conventional PID with Kp-steady , Ki-steady and Kd-steady . The guidelines are summarized as
follows:
(1) A given conventional PID design for a switching power converter usually has a bandwidth
of 5%-30% of the switching frequency and a phase margin of 45º-70º [C19,C20,C32]. This
results in a set of Kp-steady , Ki-steady and Kd-steady values.
53
(2) In order to compute Kp-trans , Kp-steady obtained in step 1 should be adjusted until a higher
bandwidth is achieved with additional 10%-20% of the switching frequency. For example, if the
design in step 1 result in a closed loop with 8% bandwidth , Kp-trans is selected in order to have
20% bandwidth.
(3) In order to compute Ki-trans , Ki-steady obtained in step 1 should be adjusted until the low
frequency loop gain is increased by 20%-30%.
(4) The threshold voltage, Vthr , should be selected to be larger than that of the output voltage
ripple of the power converter with a safe margin. A suitable value for Vthr is twice the output
voltage ripple.
(5) The values of Kp-trans, Ki-trans and Vthr are used in Eq. (3.3) and Eq. (3.4). These are the only
three values that need to be predetermined for the AD-PID since Verror-peak and verror(n) values are
dynamically and adaptively detected during the operation.
(6) It should be noted that the PID with Kp-trans and Ki-trans may not be stable in steady state (as
will be shown in the next section) and cannot be used to replace the original conventional PID
with Kp-steady , Ki-steady . The Kp-trans and Ki-trans values are only used during the transients by Eq.
(3.3) and Eq. (3.4) and based on Figure. 3.6 AD-PID controller algorithm.
The Kp-trans and Ki-trans values selected based on the above design guidelines should satisfy the
following theoretical restrictions.
(1) The selected Kp-trans and Ki-trans should not make the loop bandwidth more than half the
switching frequency. While the Kp-trans and Ki-trans values can be selected such that the bandwidth
is close to half the switching frequency, they should be selected such that the AD-PID bandwidth
during dynamic transients is less than half the switching frequency with a sufficient safety
54
margin to account for component non-idealities, modeling errors, linearization errors of transfer
functions among others.
(2) The selected Kp-trans and Ki-trans values should result in negative closed loop poles in the s-
plane or closed loop poles inside the unit circle in the z-plane.
It should be noted that for the same power converter, there are several possible conventional
(not adaptive) compensator designs, and this affects the coefficients selection of the AD-PID and
its performance.
Based on the above design guidelines and the power stage design given in Section 5 next,
first, a conventional PID controller is designed with 4.5625p steadyK , 0.078125i steadyK and
1.015625d steadyK to yield a bandwidth of 29KHz and a phase margin of 045 . The switching
frequency used is 350KHz. The value of Kp-trans is selected to be 8.46875 to yield an additional
~12% bandwidth. The value of Ki-trans is selected to be 0.218125 to yield a 20% increase in the
low frequency gain from 53dB to 64 dB. The value of Vthr is selected to be 16.2mV, which is
twice the ripple voltage. The selected Kp-trans and Ki-trans values result in a system bandwidth of
70KHz (during transients) which is below the half of switching frequency limit. In Figure. 3.2(c)
shown earlier in this chapter, the bode-plot with lowest bandwidth represent the bode-plot with
Kp-steady and Ki-steady values, and the bode-plot with highest bandwidth is the bode-plot with Kp-trans
and Ki-trans values. Table I summarizes the values of different parameters used in the
implementation of PID compensator and AD-PID controller algorithm in this chapter. With these
values, Eq. (3.3) and Eq. (3.4) now become Eq. (3.5) and Eq. (3.6), respectively.
55
0.078125, ( ) 0.0162
( ) 0.218125, ( ) 0.0162 ( 1) ( )
( )0.14 0.078125, ( ) 0.0162 ( 1) ( )
error
error error error error
error
error error error
error peak
v n V
v v n V and v n v n
v nv n V and v n v n
V
(3. 5)
4.5625, ( ) 0.0162
( ) 8.46875, ( ) 0.0162 ( 1) ( )
( )3.90625 4.5625, ( ) 0.0162 ( 1) ( )
error
error error error error
error
error error error
error peak
v n V
v v n V and v n v n
v nv n V and v n v n
V
(3. 6)
Table 3.1: Values of variables used in the design example.
Variable Value Bandwidth Low frequency gain
Kp-steady 4.5625
29KHz
53dB Ki-steady 0.078125
Kd-steady 1.015625
Kp-trans 8.46875
70KHz
64dB Ki-trans 0.218125
Vthr 16.2mV
3.5. Proof-Of-Concept Experimental Prototype Results
A proof of concept experimental prototype is built in the laboratory for verification and test of
the proposed AD-PID controller. The power stage is a single-phase DC-DC buck converter with
input voltage range of 8V-10V and nominal output voltage of 1.5V. The output inductor is 440nH
56
and the output capacitance is1mF . The switching frequency of 350KHz is used. The digital
controller is implemented using Altera FPGA, “Altera Cyclone II EP2C35F672C6”.
Figure. 3.7 through Figure. 3.11 shows the experimental results. Figure. 3.7(a) shows the
results with the conventional PID with optimized design for a load transient from 7A to 0A while
Figure. 3.7(b) shows the results with the proposed AD-PID for the same load transient conditions.
57mV
7A
50µs
(a)
45mV
7A
22µs
(b)
Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor
Current (5A/div., 20µs/div.).
Figure. 3.7: Experimental results of the prototype with zoomed in view under dynamic load step-
down transient of 7A-0A (a) with conventional PID controller and (b) with AD-PID controller.
57
Figure. 3.8(a) shows the results with the conventional PID for a load transient from 0A to 7A
while Figure. 3.8(b) shows the results with the proposed AD-PID for the same load transient
conditions. Figure. 3.9 and Figure. 3.10 show the results with conventional PID, and proposed
AD-PID under load step-down and step-up transients of 6A to 2A and 2A to 6A, respectively.
65mV
7A
50µs
(a)
48mV
7A
22µs
(b)
Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor
Current (5A/div., 20µs/div.).
Figure. 3.8: Experimental results of the prototype with zoomed in view under dynamic load step-
up transient of 0A-7A (a) with conventional PID controller and (b) with AD-PID controller.
58
32mV
4A
30µs
(a)
25mV
4A
21µs
(b)
Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor
Current (5A/div., 20µs/div.).
Figure. 3.9: Experimental results of the prototype with zoomed in view under dynamic load step-
down transient of 6A-2A (a) with conventional PID controller and (b) with AD-PID controller.
59
40mV
4A
30µs
(a)
33mV
4A
20µs
(b)
Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor
Current (5A/div., 20µs/div.).
Figure. 3.10: Experimental results of the prototype with zoomed in view under dynamic load
step-up transient of 2A-6A (a) with conventional PID controller and (b) with AD-PID controller.
60
(a)
(b)
Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor
Current (5A/div., 20µs/div.).
Figure. 3.11: Experimental results of the prototype with zoomed in view under steady-state
operation (a) with PID controller with Kp-trans and Ki-trans and (b) with PID controller with
Kp-steady and Ki-steady.
It can be observed from the results that the AD-PID controller results in reduction in the output
voltage dynamic deviation and in shorter settling time. Moreover, this is achieved with no
additional oscillations or ringing during the AD-PID operation. The output voltage with the AD-
PID controller looks similar in shape to that with conventional PID controller, but with less output
61
voltage dynamic deviation and with shorter settling time. For this specific design example, the
overshoot is reduced by 15mV (about 26%), the undershoot is reduced by 15mV (about 26%) and
the settling time is reduced by more than 25µs (> 50%) in the case of 0A-7A load transient range.
In the case of 2A-6A load transient range, the overshoot is reduced by 7mV (about 18%), the
undershoot is reduced by 6mV (about 15%) and the settling time is reduced by 9µs (about 30%).
As mentioned earlier in the chapter, if the Kp-trans and Ki-trans values are used during the steady
state operation, the closed loop system will be unstable. Figure. 3.11(a) shows the experimental
results for this case where the instability can be observed since Kp-trans and Ki-trans values are used
in steady state. Figure. 3.11(b) shows the steady state experimental results with Kp-steady , Ki-steady
values where the stable operation can be observed.
3.6. Comparison of AD-PID with Other Non-Linear PID Strategies
The non-linear PID strategy proposed in [C23] uses hysteretic control to switch abruptly
between two predetermined compensators. This type of action may cause ringing and instability
problems when switching between transient and steady state operations. Moreover, the
performance may be affected for different transient types and magnitudes.
The non-linear PID strategy proposed in [C18] varies the PID parameters smoothly. However,
the strategy requires a complicated design and it requires selection of several variables that
affects performance under different transient types and magnitudes. It has two threshold levels
for the variation of error signal namely “a” and “b”. Also, for different PID constants, the values
of “a” and “b” can be different. The criteria for smooth variation of constants within the window
between “a” and “b” is not specified.
62
The AD-PID controller utilizes a scheme that makes sure that the transition between the
steady state and transient operation modes is smooth and free of additional oscillations and
ringing. Moreover, the AD-PID controller design and operation do not depend on any additional
assumption of the transient magnitudes or types. It is able to adjust and adapt its operation for
different transient magnitude and type since it always detects the peak value of the voltage error
signal and utilizes it in its control low as discussed earlier in this chapter.
3.7. Summary
The chapter presents an adaptive digital PID controller in order to improve the dynamic
performance of power converters’ closed loop system. The AD-PID reduces the dynamic output
voltage deviation and settling time by using a simple strategy and without the need to sense any
additional information other than the output voltage of the power converter. The AD-PID
controller utilizes a scheme that makes sure that the transition between the steady state and
transient operation modes is smooth, and free of additional oscillations and ringing. Moreover, the
AD-PID controller design and operation do not depend on any additional assumption of the
transient magnitudes or types. It is able to adjust its operation for any transient magnitude and
type since it always detect the peak value of the voltage error signal and utilize it in its control
law. The operation principle and experimental results of the AD-PID controller are presented and
discussed in this chapter and compared with conventional PID controller.
63
CHAPTER 4
A NOVEL ADAPTIVE AUTO-DESIGN AND AUTO-TUNING METHOD FOR
CLOSED-LOOP CONTROLLERS OF POWER CONVERTERS
4.1. Introduction
The design and tuning of the closed-loop feedback control of power converters for stable
operation with high dynamic performance over variable and wide operating conditions is critical
in many applications [D1-D4]. In the design process, the power stage transfer function and design
parameters are used to design the closed-loop compensator [D4-D9]. The inaccuracy in the
knowledge of the power stage components and their parasitic values in addition to the
approximations used in the transfer functions affect the design accuracy and performance of the
designed compensator. Additional sources of inaccuracy include the delay of the switches’
drivers, the digital logic component delays, and the Analog-to-Digital Converter (ADC) delays
when a digital controller is used.
The control loop design is usually based on conventional methods with rule of thumb design
guidelines such as gain and phase margins with bode-plots and/or root-locus pole-zero locating
[D7-D10]. The drawbacks of using these methods include one or more of the following: (1) they
require the knowledge of the power stage transfer function (frequency response), (2) their results
are sensitive to design approximations and power stage components’ parasitic values, (3) the
theoretical design is usually not sufficient and additional adjustment or tuning is usually required
for the implemented hardware. All this makes the design of a high performance closed
64
loopcompensator a non-easy task and requires a tedious manual tuning in the theoretical design
and in the experimental hardware.
The advantages of digital controllers in power converter applications have made them
stronger competitors and alternative to their analog counterpart in several applications [D10-
D19]. These advantages include the digital controllers’ ability and easiness to implement
sophisticated algorithms and laws to improve dynamic and efficiency performances of power
converters, they are easier to be reconfigured and scaled compared to their analog counterpart,
and they can potentially reduce or eliminate the controller component variations and sensitivity
that affect the controller performance [D10-D19]. On the other hand, the limited resolution, the
size, cost and power consumption incurred from the required high-speed high-resolution Analog-
to-Digital Converters (ADCs) and Digital Pulse Width Modulators (DPWMs) are among the
challenges in designing and utilizing digital controllers in power converter applications.
In order to alleviate the challenges and difficulties in closed-loop compensator design
discussed earlier, researchers have utilized digital controllers’ ability to auto-tune and/or
calibrate the compensator [D20-D28]. In [D5-D7, D20, D23, D28] auto-tuning controller
schemes, the closed loop is perturbed using a test signal and the response to that signal is
obtained to find the frequency characteristics of the loop. The phase margin and gain margin are
obtained and the necessary adjustment of compensator parameters is made to attain the desired
phase margin and gain margin. In [D21], an auto-tuning controller scheme based on Model
Reference Impulse Response is presented. This auto-tuning controller compares the measured
system response with a reference system response and adjusts a compensator parameter
accordingly to minimize the error function. In [D22], an auto-tuning controller based on the relay
feedback method is presented. It tunes the proportional-integral-derivative parameters of the
65
compensator based on a desired phase margin and control loop bandwidth. In [D26], a self-
tuning analog current-mode controller is presented. The presented method is based on the
insertion of nonlinear (NL) blocks in the control loop and measurement of the closed-loop
properties such as gain margin, phase margin, and crossover frequency by perturbing the output
voltage. The controller is then tuned according to desired set of specifications.
The power converter closed-loop auto-tuning schemes discussed in the literature, such as the
examples discussed above, usually have one or more of the following characteristics: (1) they are
relatively complicated and require adding significant hardware, (2) they require breaking the
control loop, interrupting the power converter system operation and/or injecting signal
(disturbance) that affects the output voltage regulation, and (3) their operation is based on
conventional design methods and the associated rule of thumb design criteria.
In this chapter, an online closed-loop-compensator auto-tuning digital power controller
(ATerror controller for abbreviation) is proposed. The proposed method is relatively simple and
does not require the knowledge and/or measurement of the power stage or closed-loop frequency
response and does not depend on conventional design methods and the associated rule of thumb
design criteria.
Section 4.2 discusses the bases for the proposed concept of the ATerror controller, which is
called Compensator Error Observe and Modulate method (CEO&M Method). Section 4.3
presents the ATerror controller digital implementation algorithm and architecture. The proof-of-
concept experimental prototype results are presented in section 4.4 and the conclusion is given in
Section 4.5.
66
4.2. Bases of the Proposed Online Auto-Tuning Controller
The proposed online auto-tuning controller is based on observing the compensated error signal
time domain characteristics, which is readily available in any compensated closed-loop feedback
controller. This method is referred to as CEO&M method.
Figure. 4.1 shows a block diagram of a power converter system with voltage-mode closed-
loop feedback control. Transfer function notation for each part of the system is indicated on the
figure. The difference between the reference voltage and the output voltage (the uncompensated
error) is applied to a compensator, such as PID (Proportional-Integral-Derivative) compensator
to result in a compensated error signal ( e compV ). e compV has a DC component and an AC
component and is used to generate the controller duty cycle using a Pulse Width Modulator
(PWM).
Power Converter oVinV
Closed Loop
Compensator
refV
PWM
e compV
( )pG s
( ) ( )c cG s or G z
( )MG s
Figure. 4.1: A block diagram of a power converter system with closed loop control.
The CEO&M will first be introduced using simulation results of a design example. The design
example is a DC-DC buck converter closed-loop system with a three-pole two-zero compensator
(one pole is at zero), 12V input voltage, 1.5V output voltage, 0.1µH output inductor, 350µF
output capacitor, and 1MHz switching frequency ( swf ). Figure. 4.2 shows the system bode-plots
67
(for ( ) ( ) ( )p c MG s G s G s ) for different gain (K) values and different pole (P1) locations (one
pole location is varied).
(a)
(b)
Figure. 4.2: Bode-plots for (a) different gain (K) values and (b) different pole (P1) locations.
68
(a)
(b)
Figure. 4.3: Simulation results of a DC-DC buck converter to demonstrate the basis of the
proposed CEO&M control concept based on several K values (Note that .e conv e compV V ):
(a) during steady-state and (b) during step-up load transient.
The power converter system is simulated using Matlab®/Simulink® software package. The
simulation results are shown in Figure. 4.3 and Figure. 4.4 that correspond to Figure. 4.2(a) and
Figure 4.2(b), respectively. Figure. 4.3 and Figure. 4.2(a) show that as the compensator gain K
increases, which corresponds to increase in bandwidth and system speed, the peak-to-peak value
69
of the compensated error signal ( e ppV ) increases and the dynamic performance is improved
(smaller output voltage dynamic deviation and shorter settling time). This occurs up to a point
where the system becomes unstable and the frequency of e compV ( Ve compf ) becomes lower than
the switching frequency. Similarly, Figure. 4.4 and Figure. 4.2(b) show the same behavior as the
pole location P1 is moved in a direction that results in increasing the system bandwidth and
improving the system dynamic performance.
(a)
(b) (c)
Figure. 4.4: Simulation results of a DC-DC buck converter to demonstrate the basis of the
CEO&M control concept (Note that .e conv e compV V ) based on several pole locations (one pole is
moved): (a) during steady-state, (b) during step-up load transient and (c) during step-down load
transient.
70
Therefore, the following conclusion can be drawn from the previous discussion: A closed loop
controller’s compensator can be tuned or optimized by perturbing one or more of the
compensator parameter values such as gain, poles and/or zeros in a direction that will increase
e ppV as long as Ve comp swf f , or until a maximum possible e ppV value is obtained while
Ve comp swf f is still maintained.
The theoretical verification to the fact that e ppV is larger for closed-loop with higher
bandwidth is relatively simple. For simplicity, assume that the compensator is a simple low pass
filter with a gain (K) and a cutoff frequency c as follows:
( ) ( ) ( ) ( )
1 1
c e comp c e comp
c c
K KG s V s G s V s
s s
(4.1)
Eq. (4.1) indicates that the magnitude of ( )e compV s ( ( )e compV s ) increases as K (the gain)
increases and as c (the pole) increases, which indicates a faster system. Similar behavior is
expected with a higher order low-pass filter type (several poles in addition to several zeros).
As illustrated in Figure. 4.5, as the bandwidth is increased (by increase of gain), e ppV
becomes larger up to a point where the closed-loop system becomes unstable, and the frequency
of e compV ( Ve compf ) becomes lower and not equal to the digital ramp switching frequency. This
will cause the PWM output to have a frequency that is lower than the switching frequency (or the
ramp signal frequency). This point is likely to occur as the bandwidth becomes closer to half of
the switching frequency [D30- D34].
71
Lower
Bandwidth
Unstable
Higher Bandwidth
Figure. 4.5: An illustration of the compensated error signal behavior under different bandwidth
values with analog compensator.
Lower
Bandwidth Unstable
e comp LBWVe comp UV
Ve comp LBWD
Ve comp HBWD
Ve comp UD
DigitalRamp
e comp HBWVHigher
Bandwidth
Figure. 4.6: An illustration of the compensated error signal behavior under different bandwidth
values with digital compensator.
Even though the previous discussion and example is based on a compensator transfer functions
in analog domain, it should be obvious that the same argument is valid when a digital
compensator implementation is used. An example digital equivalent to Figure 4.5 is shown in
Figure 4.6. Figure 4.6 shows a digital ramp and digitally compensated error signal assuming
72
multisampling operation per switching cycle (multiple ADC samples used for multiple
calculations per switching cycle) [D31, D32]. In a conventional digital controller, the duty cycle
command can be calculated either once (single sample) each switching cycle or multiple times
(multisampling rate) [D31] in order to generate a compensated error signal.
Figure. 4.7 shows a DC-DC buck converter with digital closed-loop compensator and a
proposed auto-tuning controller (ATerror) block diagram. Based on the previous discussion, by
observing e ppV and Ve compf , the closed-loop compensator parameters can be tuned to achieve a
closed-loop converter system with better dynamic performance by tuning one or more of the
compensator parameters to a more near to optimum value for a given power converter design.
This is discussed further in the Section 4.3.
Su
Sl
Lo
CoDrivers
Latches
D
D1Io
+
-
Vo
iL
Vin
Closed Loop
Compensator
DPWM
Modulator
Vref
e compV
D
ADC
ATerror Online
Auto-Tuning
Controllerswf
Figure. 4.7: DC-DC buck converter with digital closed-loop compensator and ATerror
Controller.
4.3. Online Auto-Tuning Digital Controller Algorithm and Architecture
As shown in Figure. 4.7, the main input to the ATerror controller is e compV . The only other
input is the switching frequency ( swf ) which is the DPWM (Digital Pulse Width Modulation)
73
frequency in order to synchronize the operation of the ATerror controller when its e ppV and
Ve compf are measured. These two inputs are readily available in the controller, and therefore, no
additional voltage or current sensors are needed.
Figure. 4.8 shows a general implementation flowchart of the ATerror Controller. The controller
finds e ppV value several times, over “H” switching cycles in order to confirm steady-state
operation and the accuracy of e ppV . Since auto-tuning is performed during a steady-state
operation, it is necessary to confirm the steady-state operation of the power stage.
If the e ppV value is stable over the “H” switching cycles (note that one e ppV value is recorded
in the digital controller every one switching cycle), the controller will adjust the closed-loop
compensator parameter(s) (such as gain, pole or zero) in a direction that will increase or decrease
the e ppV value (which result in increase or decrease in the closed-loop bandwidth) after
confirming the Ve comp swf f condition. Note that Ve comp swf f condition can be verified, for
example, every switching cycle by measuring the time between two compensated error signal
peaks in two or more consecutive switching cycles (this will be detailed in the next section). The
Ve comp swf f condition is considered satisfied if the consecutive peak values of e ppV are equal
or within a specified error range (to account for digital resolution errors). The increase/decrease
decision of the compensator parameter being tuned is based on the comparison between the new
value of e ppV ( ( )e ppV r ) and the previous value of e ppV ( ( 1)e ppV r ). If ( ) ( 1)e pp e ppV r V r
is satisfied, the ATerror controller will adjust the closed-loop compensator parameter(s) in a
direction that will increase the e ppV (and hence closed-loop bandwidth). Taking the compensator
gain (K) as an example here, K value is increased. The ATerror controller will then wait “Y”
74
switching cycles to ensure new steady-state operation before repeating the process again. If
( ) ( 1)e pp e ppV r V r is not satisfied, the ATerror controller will repeat the process starting from
recording e ppV again.
Yes
Start
Increment Counter SC
by one
Obtain . ( )e compV n
( ) ( 1)e comp e compV n V n
( 1) ( )e comp e compV n V n
min ( )e e compV V n
No
( ) ( 1)e comp e compV n V n
max min( )e pp e eV m V V
Ve comp swf f
Change a compensator
parameter in a direction that
decreases bandwidth
ex. gain “k”, Pole “p” and/or
Zero “z”
Stop tuning or
Wait Z
switching cycles
to restart
No
Reset SC Counter ( 1) ( )e pp e ppV r V r
( ) ( 1)e pp e ppV r V r
Yes
Yes
Change a compensator parameter in
a direction that increases bandwidth
ex. gain “k”, Pole “p” and/or Zero “z”
Wait Y
switching cycles
( ) ( 1)e pp e ppV m V m
SC > H
Yes
Yes
No
( ) ( )e pp e ppV r V m
No
No
SC > HNo
Yes
max ( )e e compV V n
Yes
Figure. 4.11
Figure. 4.12
Figure. 4.8: General main implementation flowchart of the ATerror controller.
If the value of e ppV is not the same or not stable over the “H” switching cycles, the controller
will check if this condition is because Ve comp swf f . If it is the case, the ATerror controller will
vary the appropriate parameter (in this example, reduce K) in a direction that will reduce e ppV
75
(and hence closed-loop bandwidth) until the condition Ve comp swf f is satisfied and then stops
its operation for “Z” switching cycles assuming that a more near to optimum value for the
parameter (K value, in this example) has been reached before starting the new auto-tuning process
again (the new auto-tuning and calibration cycle). The new auto-tuning process can be performed
periodically or when a change is detected that requires a new auto-tuning operation.
It should be noted that there may be several possible ATerror controller
algorithms/implementations based on the CEO&M concept, and one of them is described in the
next section. Also, more specific implementation details for the parts of Figure. 4.8 controller
flowchart are presented in Figure. 4.11 and Figure. 4.12.
4.4. Proof-Of-Concept Experimental Prototype Results
This section is divided into two parts. In the first part an experimental verification for the
CEO&M concept is presented, and in the second part, the experimental results of the ATerror
controller (which is based on the CEO&M concept) are presented and discussed.
A proof of concept experimental prototype is built in the laboratory in order to verify the
proposed concept and controller. The prototype is a single phase buck converter with a nominal
input voltage of 9V and a nominal output voltage of 1.5V, output inductor of 440nH , output
capacitance of 2.8mF , switching frequency of 342kHz and full load current of 8A.
Fully digital control hardware is used to implement the closed-loop voltage-mode feedback
compensator and the ATerror controller. The output voltage ADC has an 8-bit resolution and
takes 2.8M sample/second of the output voltage. However, only 4 ADC samples are utilized to
obtain (calculate) 4 values of e compV and the duty ratio update is sent to the DPWM once each
switching cycle. The DPWM used is with 10-bit resolution. The digital controller is implemented
using Altera FPGA “Altera Cyclone II EP2C35F672C6”.
76
The digital compensator architecture used is as shown in Figure. 4.9, where 1.39pK ,
0.0195iK , 0.008dK and TK is the gain which is varied for optimization by the ATerror
controller.
To
DPWM
dK
iK
pK
-1Z
-1Z
Vref
ADC
errorv
( )e compV z
outvTK
-1Z
1
1( ) ( (1 ))
1
ic T p d
KG z K K K z
z
Figure. 4.9: Digital compensator used in the proof of concept experimental prototype.
4.4.1. Experimental Verification of the Auto-Tuning Controller Bases
The gain of the compensator ( TK ) is varied in order to investigate the effect on e compV .
Figure. 4.10 shows the experimental results of the output voltage and e compV under three different
example values of TK as indicated in Figure. 4.10 caption. The three different gain values
correspond to three different bandwidth values. The lower gain value results in a lower
bandwidth, the medium gain value results in a medium bandwidth, and the higher gain value
results in a higher bandwidth that causes the system to start becoming unstable as shown in the
figure. It could be observed from Figure. 4.10 results that as the gain is increased (and hence
bandwidth is increased), e ppV is increased and the dynamic output voltage deviation and settling
time are reduced, up to a TK value that makes the system unstable. It can also be observed from
Figure 4.10(e) that, in this unstable case, the frequency of the compensated error signal is not
equal to the switching frequency ( Ve comp swf f ).
77
20mV
95mV
220µs 100mV
220µs
(a) (b)
90mV
38mV
100µs 40mV
100µs
(c) (d)
160mV
30mV
90µs 35mV
90µs
(e) (f)
Time: 2.5µs/div. Time:100µs/div.
Top Trace (Output Voltage, AC Coupled):
30mV/div.
Bottom Trace (Compensated Error Signal,
e compV , AC Coupled): 50mV/div.
Trace (Output Voltage, AC Coupled):
60mV/div.
Figure. 4.10: Experimental results of a DC-DC buck converter to demonstrate the basis of
the proposed CEO&M control concept when varying gain. (a) and (b): Lower gain
( 0.344TK ) . (c) and (d): Medium gain ( 1.593TK ). (e) and (f): Higher (Unstable) gain
( 2.531TK ). (a), (c) and (e): During Steady-State Operation. (b), (d) and (f): Under 8A-0A-8A
Load Current Transient.
78
These results agree with the theoretical assumptions of the CEO&M concept presented earlier.
The same behavior using other several commercially available power converter prototypes with
analog controllers is also verified. These results show that CEO&M concept is valid, and it can be
utilized for the auto-tuning of the compensator’s parameters.
4.4.2. Experimental Operation and Results of the Online Auto-Tuning Controller
The ATerror controller is used to auto-tune the gain, TK , of the compensator as an example
parameter. A general implementation flowchart of the ATerror controller is discussed in the
previous section (Figure. 4.8). More ATerror controller operation details are given in this section.
At the beginning of the auto-tuning cycle, the ATerror controller adjusts the gain of the
compensator and identifies the direction of gain change (increase or decrease) that results in an
increase in e ppV , while maintaining Ve comp swf f , as shown in Figure. 4.11 flowchart.
The ATerror controller first decrements (increments) the gain of the compensator (as
illustrated in Mode A1 of Figure. 4.13, for decrementing the gain TK ) and compares the e ppV
under the current gain value ( ( )e ppV r ), with the e ppV under the previous gain value
( ( 1)e ppV r ). If there is an increase in e ppV ( ( ) ( 1)e pp e ppV r V r ), the controller identifies
this decrement (increment) direction of gain as the correct direction to adjust the gain to increase
e ppV . Otherwise, increment (decrement) direction of gain is identified by the controller as the
correct direction to adjust the gain to increase e ppV . This process of decrement (increment) of
gain occurs for “S” steps. After the end of “S” steps, the gain is once again incremented
(decremented), until it reaches the initial gain (which takes S-1 steps), when the process of gain
change started (as illustrated in Mode A2 of Figure. 4.13, for incrementing the gain TK ).
79
Detection = 1NoYes
Start
DC Counter = 1
Direction = Sign(p)
Sign(p) = Not Sign(p-1)Sign(p) = Sign(p-1)
Yes No
( ) ( 1)e pp e ppV r V rYes No
Sign(p) = Not Sign(p-1)Sign(p) = Sign(p-1)
( ) ( 1)e pp e ppV r V r
DC Counter < SNo
Yes
Increment
Sign(p) = 1TK
Decrement
Sign(p) = 0TK
DC Counter < 2S
Yes
Detection = 0
No
Increment DC Counter
Mode A1Mode A2
Direction = 1NoYes
Decrement TK IncrementTK
Ve comp swf f
Yes No
Ve comp swf f
Yes No
Increment TKDecrement TK
Figure. 4.12
Wait for
Z
cycles
Figure. 4.11: A flowchart for the detection of direction of gain change (increase/decrease).
The duration of the direction detection process is determined by “S”. The ATerror controller
initializes the detection process by setting “Detection=1”, and initializing “DC Counter=1” as
shown in Figure. 4.11. The variable “Sign” is set to be equal to “0”, the gain TK is decremented
80
and the corresponding change in e ppV is observed. If e ppV s increased ( ( ) ( 1)e pp e ppV r V r ),
then the variable “Direction” is set to “0” through the variable “Sign”. Otherwise, “Direction” is
set to “1” by taking the complement of “Sign”. At the end of the operation cycle of setting
“Direction” value, “DC Counter” is incremented. This process repeats until the “DC Counter”
value is greater than “S” (as illustrated in Mode A1 of Figure. 4.13). When “DC Counter” is
greater than “S”, the gain TK is incremented, and the change in e ppV is observed (as shown in
Figure. 4.11 and illustrated in Mode A2 of Figure. 4.13). Based on the change in e ppV , the
“Direction” is set through the variable “Sign” as described earlier. When the “DC counter” value
is equal to twice “S”, the gain change direction is set in “Direction ” (0 or 1) and the value of
“Detection” is set to “0” to indicate that the gain direction detection process is completed. The
value of “Direction” is set to “1” if an increase in the gain (or any other variable to be tuned such
as a zero or a pole) increases e ppV .Otherwise it is set to “0”.
Once the correct/required direction of gain change to increase e ppV is identified, the ATerror
controller adjusts the gain in that direction and observes e compV for any instability as described
in Figure. 4.8 flowchart, or in other words, it watches for the condition when Ve comp swf f The
controller flowchart for the detection of the condition Ve comp swf f is shown in Figure. 4.12. In
this experiment, instead of measuring Ve compf in order to compare it with swf , the condition
Ve comp swf f is detected/identified by observing the difference between the consecutive e ppV
values over several switching cycles, for simplicity. If this difference is above a preferment
value, the controller determines that Ve comp swf f . In other words, Ve comp swf f is identified
(indicating an unstable output voltage) if the deviation between two consecutive values of e ppV
81
( ( ) ( 1)e pp e ppV r V r ) is greater than an upper limit value ( HL ). The gain is first adjusted in
the direction identified earlier until the deviation between two consecutive cycles is greater than
HL ( ( ) ( 1)e pp e ppV r V r HL ). Mode B in Figure. 4.13 illustrates the increase of gain until
( ) ( 1)e pp e ppV r V r HL is satisfied. Once this condition is detected, the controller starts
adjusting the gain value in the opposite direction that decreases e ppV (as illustrated in Mode C
of Figure. 4.13) until the difference ( ( ) ( 1)e pp e ppV r V r ) is less than a lower limit
( LL ),which is considered a stable condition. At this stable condition, the controller sets the gain
value and waits for a predetermined amount of time (Z switching cycles) before another auto-
tuning process is initiated.
As shown in Figure. 4.12, at the beginning of the frequency change detection process, the
variable “Flag” is set to be equal to “1”, which indicates that Ve comp swf f . Depending on the
value of “Direction”, the gain, TK , is incremented or decremented. When “Direction = 0
(Direction = 1),” the gain TK is incremented (decremented) until the deviation between the
values of e ppV ( ( ) ( 1)e pp e ppV r V r ) is larger than HL (as illustrated in Mode B of
Figure. 4.13). When the deviation in e ppV exceeds HL , “Flag” is set to “0” indicating the
frequency change condition ( Ve comp swf f ). The gain is then decremented (incremented) until it
reaches the value where the deviation between e ppV values is less than LL (as illustrated in
Mode C of Figure. 4.13). For this experiment, 20HL mV and 16LL mV are selected.
82
Start
Flag = 1
Obtain Direction
Direction = 1
YesFlag = 1
No
No
Flag = 0
Yes
Increment TK
Yes
No
( ) ( 1)e pp e ppV r V r LL
Decrement TK
Yes
No
( ) ( 1)e pp e ppV r V r HL
Mode C
Wait for
Z
cycles
YesFlag = 1
No
No
Flag = 0
Yes
Decrement TK
Yes
No
( ) ( 1)e pp e ppV r V r LL
Increment TK
( ) ( 1)e pp e ppV r V r HL
Wait for
Z
cycles
Mode B
Figure. 4.12: A flowchart for the detection of frequency change and setting of gain.
83
1
Mode A1 Mode B Mode C
2
S
S+1
S+2
2S-1
( ) ( 1)e pp e ppV r V r HL
( ) ( 1)e pp e ppV r V r LL
TK
Mode A2
Figure. 4.13: Illustration of the controller operation to determine the variable under auto-tuning
(the gain here) required direction change and the detection of frequency change condition.
Figure. 4.14 shows the experimental waveforms of the prototype during auto-tuning
operation. Figure. 4.14(a) shows an auto-tuning cycle starting from an initial gain value until the
ATerror controller converges to new gain value, for demonstration purposes. As it can be
observed from Figure. 4.14 (a), the ATerror controller initially identifies the correct direction of
the gain change, followed by adjusting the gain and the detection and confirmation of the
frequency condition (as described earlier) before setting the new optimized gain value. Figure.
4.14(b) shows the periodic re-auto-tuning operation of the controller (the optimized gain value
stays same since it is for the same converter design and operating conditions).
Figure. 4.15 shows the comparison in the transient response of the converter, before auto-
tuning and after auto-tuning. Figure. 4.15(a) shows the response of the controller before auto-
tuning due to a step-down load transient of 8A to 0A. Figure. 4.15(b) shows the response of
controller after auto-tuning is complete with ATerror controller for the same load variation of 8A
to 0A.
84
(a)
Time: 50ms/div.
(b)
Time: 100ms/div.
Top Trace (Output Voltage, AC Coupled): 60mV/div.
Bottom Trace (gain): 0.3125/div.
Figure. 4.14: Experimental waveforms of the prototype with the ATerror controller. (a): The
variation of gain until new optimized gain value is achieved.(b): Periodic tuning operation of the
ATerror controller.
85
75mV
210µs
(a)
31mV
90µs
(b)
Time: 50µs/div.
Output Voltage, AC Coupled: 60mV/div.
Figure. 4.15: Dynamic response of the power converter during a load transient of 8A to 0A
(a) before auto-tuning (b) after auto-tuning.
4.5. Summary
This chapter proposes a method to tune the power converter closed-loop compensator
parameters to improve the dynamic performance. The CEO&M concept observes the time domain
characteristics of the compensated error signal ( e compV ), namely the peak-to-peak value ( e ppV )
and frequency ( Ve compf ) to tune the compensator. This method eliminates several drawbacks of
86
the conventional auto-tuning schemes as discussed in this chapter. The proposed method does not
require the knowledge of the power stage frequency response, does not depend on any
conventional rule of thumb control design criteria such as gain and phase margins, and is
dependent only on the time domain parameters of the compensated error signal. A proof of
concept experimental prototype results are presented for verification.
The proposed CEO&M concept is then utilized to implement an online closed-loop-
compensator auto-tuning digital controller (ATerror controller). The ATerror controller does not
require the knowledge and/or measurement of the power stage or closed-loop system frequency
response(s). The digital implementation algorithm, architecture, and a proof-of-concept
experimental prototype results are presented for the ATerror controller. While in this chapter’s
experiment, the compensator gain is auto-tuned, the method could also be used to auto-tune other
parameters of the compensator such as pole and zero locations.
87
CHAPTER 5
AN ADAPTIVE DIGITAL VARIABLE FREQUENCY CONTROL SCHEME
5.1. Introduction
DC-DC switching power converters are widely used in many low power to high power
applications [E1-E6]. In order to regulate the output voltage of these power converters, analog
controllers or digital controllers can be used [E6-E12, E30, E31]. These controllers generate the
appropriate control command [E7], which is the duty cycle and/or switching frequency here,
under steady-state and dynamic operations.
Digital power control has made the implementation of complex and sophisticated algorithms
that result in the power converter performance improvement [E13–E15]. Also, the aging effects of
the digital controllers are negligible compared to the analog controllers. Figure. 5.1 shows the
block diagram of digital controller implementation for a power converter.
The dynamic performance of the power converter is critical in many applications [E16-E22].
Two of the most important parameters that are measures of transient performance of power
converter are the output voltage overshoot/undershoot and the settling time. The dynamic
performance can be improved by means of adaptive control techniques. The method in [E23]
utilizes an analog control law that varies the amplitude of the ramp signal dynamically while
maintaining constant switching frequency in order to improve the dynamic performance of a
power converter. The methods in [E24] and [E25] utilize the adjustment of the PID controller
88
constants in order to improve the transient performance. The methods in [E26] utilizes a hysteretic
control that switches the compensators used during the steady state and transient in order to
improve the performance of the converter during transient.
SL
Lo
CoDrivers
Latches
D
D1Io
+
-
Vo
iL
Vin
DPWM
Modulator
cV
D
ADC
Vref
Compensator
errorV
SU
Figure. 5.1: Block diagram of a Power Converter with Digital Controller.
In this chapter, two control methods/laws are proposed in order to improve the dynamic
performance of power converters, and the improvement in their dynamic performance is
compared. The proposed control methods do not require sensing any other additional parameters
that are not already available in any conventional controller, and it is relatively simple to realize.
Next section reviews the operational principle of conventional DPWM (Digital Pulse Width
Modulation) schemes. Section 5.3 presents the proposed dynamic switching frequency variation
control methods/laws and algorithms. Section 5.4 presents the theoretical proof for the proposed
methods. Section 5.5 presents experimental results obtained for a proof-of-concept experimental
prototype. The conclusion is given in Section 5.6.
89
5.2. Digital Pulse Width Modulation
The output of the converter is maintained at a desired value by varying the ON/OFF condition
of the switches ( US and LS ). This is achieved by generating a control command signal
( AD or D ) by comparing the compensated error signal ( cV ) to a reference ramp signal. This
process is referred to as PWM (Pulse Width Modulation), which is illustrated in Figure. 5.2
during a steady state operation of a power converter. Figure. 5.2(a) shows the Analog PWM
(APWM) case while Figure. 5.2(b) shows the Digital PWM (DPWM) case [E9, E10, E27-E30].
In digital control, the DPWM can be implemented using different architectures: Counter-
comparator based DPWM, delay line based DPWM, ring oscillator DPWM, and hybrid
segmented DPWM [E4-E8], among others.
( )cV t
Duty
Cycle
( )cV n
Duty
Cycle
peakAV
AT
(a) (b)
Figure. 5.2: Generation of duty cycle command signal with (a) analog controller (b) digital
controller.
Consider the counter-comparator based DPWM implementation as an example. Figure. 5.3(a)
shows the DPWM operation principle illustration during steady-state. The compensated error
signal ( cV ) value is compared with the counter value, and when the value of cV is greater than
the value of the counter, the switch US control is set to high or turned ON as shown in Figure
5.3(a). Otherwise it is turned OFF.
90
( )cV n
Duty Cycle
( )cV n
Duty
Cycle
Duty
Cycle
( )cV n
(a)
(b)
(c)
Figure. 5.3: DPWM operation principle illustration with fixed switching frequency during
(a) steady state (b) step-up load transient and (c) step-down load transient.
During transient operation, the compensated error signal value is greater than or less than its
steady-state value depending on whether the transient is a step-up load transient or a step-down
load transient, respectively. This results in a duty cycle value greater than or less than the steady-
state value during the dynamic operation. Illustrations of these two conditions are shown in
Figure. 5.3(b) and Figure. 5.3(c), respectively.
Section 5.3 gives the details of the proposed control law and algorithm for its implementation.
91
5.3. Adaptive Switching Frequency Control Schemes
The proposed Dynamic Variable Switching Frequency (DVSF) control is based on adjusting
the switching frequency of the controller as a function of the uncompensated error signal ( errorV )
during the controller dynamic operation. The variable switching frequency operation can be
realized by adjusting the maximum counts in a counter-comparator based DPWM for example.
The frequency of the DPWM is a function of the counter clock frequency, and the limit on the
number of counts of the counter. If clkf is the clock frequency, and limitC is the limit on the
number of counts of the counter, then the switching frequency of the DPWM is given by
Eq. (5.1)
1
clkDPWM
limit
ff
C (5.1)
In DPWM, when the frequency is varied using the number of counts as discussed above, the
gain ( DPWMG ) of the DPWM also varies as given by Eq. (5.2), where ADCV is the resolution of
Analog to Digital Converter (ADC).
1
(1 )DPWM
limit ADC
GC V
(5.2)
The DVSF controller increases the switching frequency during output voltage undershoots
and decreases the switching frequency during output voltage overshoots. The variation of duty
cycle as a result of variation of switching frequency is illustrated in Figure. 5.4. Two methods for
variation of switching frequency are proposed. These methods are referred to as DVSF I and
DVSF II.
92
( )cV n
Duty
Cycle
( )cV n
Duty
Cycle
( )cV n
Duty
Cycle
(a)
(b)
(c)
Figure. 5.4: Illustration of operational principle of DPWM with variable switching frequency
during (a) steady-state (b) step-up load transient which causes output voltage undershoot and
(c) step-down load transient which causes output voltage overshoot.
5.3.1. DVSF I
Figure. 5.5 shows the theoretical waveforms that illustrate the proposed adaptive switching
frequency controller operation. The controller observes the value of error signal ( errorV ) which is
a measure of output voltage deviation from a desired reference voltage. When errorV is outside a
small window (defined by a threshold value, thrV ) around zero, as a result of transient, the value
of DPWMf is increased or decreased depending on whether the value of errorV is positive or
negative respectively as given by Eq. (5.3). Figure 5.6 shows the controller flowchart for the
implementation of DVSF I control law. It can be observed that the direction of change in the
93
duty cycle, and the direction of change in the digital ramp peak value as a result of varying the
switching frequency work together in a way to reduce the output voltage deviation, overshoot
and undershoot.
, ( )
( ) ( ), ( )
( ), ( )
DPWM steady error thr
DPWM DPWM steady error error thr
DPWM steady error error thr
f V n V
f n f V n V n V
f V n V n V
(5.3)
0 ( )errorV n
DPWM steadyf
maxoI
minoI
Output Current
Output Voltage( )outV n
( )DPWMf n
( )DPWMT n
Figure. 5.5: Illustration of Dynamic Variable Switching Frequency (DVSF) Controller
Operation.
94
( )error thrV n V
No
Start
DPWM DPWM steadyf f
Yes
No
Obtain the value
of error signal
( )errorV n
( )error thrV n V
( ) ( )DPWM DPWM steady errorf n f V n
( ) ( )DPWM DPWM steady errorf n f V n
( )DPWM DPWM steadyf n f
Yes
(b)
Figure. 5.6: Flowchart for the adaptive switching frequency controller.
5.3.2. DVSF II
Figure. 5.7 shows the theoretical waveforms that illustrate the proposed adaptive switching
frequency controller operation. The controller observes the value of errorV which is a measure of
output voltage deviation from a desired reference voltage as shown in Figure. 5.1. When errorV is
outside a small window (defined by a threshold value, thrV ) around zero as a result of transient,
the value of DPWMf is increased abruptly to a large value ( DPWM maxf ) or a small value
95
( DPWM minf ) depending on whether the value of errorV is positive (e.g. under load step-up
transient) or negative (e.g. under load step-down transient), respectively. This provides the
necessary duty cycle variation to drive the output voltage back to its steady state value faster and
with less deviation. The controller then observes the value of errorV and finds the peak value of
errorV ( error peakV ) and the time instant this value is reached.
0
error peakV
( )errorV n
DPWM steadyf
DPWM maxf
error peakV
maxoI
minoI
Output Current
Output Voltage
out peakV
out peakV
( )outV n
DPWM minf
( )DPWMf n
DPWM steadyT
DPWM maxT
DPWM minT
( )DPWMT n
Figure. 5.7: Illustration of the adaptive switching frequency controller operation.
96
NoYes
Start
Yes
Yes No( 1) ( )error errorV n V n
Yes
No
( ) ( 1)error errorV n V n
No
( ).
( )
errorDPWM DPWM steady
error peak
DPWM steady DPWM min
V nf f
V
f f
Obtain the value of error signal ( )errorV n
( ).
( )
errorDPWM DPWM steady
error peak
DPWM max DPWM steady
V nf f
V
f f
DPWM DPWM minf f
( )error peak errorV V n
DPWM DPWM maxf f
( )error peak errorV V n
( ) 0errorV n
( )error thrV n V
DPWM DPWM steadyf f
DPWM DPWM steadyf f
( 1) ( )error errorV n V n
Figure. 5.8: Dynamic Digital Variable Switching Frequency Controller Flowchart.
The value of error peakV is used to vary the value of DPWMf gradually towards its steady-state
value ( DPWM steadyf ) as given by Eq. (5.4). DPWM steadyT , DPWM minT and DPWM maxT are the time
periods corresponding to DPWM steadyf , DPWM maxf and DPWM minf , respectively. Figure. 5.8
shows the controller flowchart for the implementation of adaptive switching frequency controller
law. It should be noted that the value of error peakV changes for different values and types of
transients and hence the proposed control law adapts to different transient types and magnitudes.
This improves the dynamic performance of converter for different magnitudes and types of
transients.
97
0 ( )
( ) 0 ( ) ( 1)
( )( )
( ) ( ) 0 ( ) ( 1)
( )
DPWM steady error thr
DPWM max error error error
errorDPWM steady DPWM max DPWM steady
error peak
DPWM error error error
DPWM min error
f if V n V
f if V n and V n V n
V nf f f
V
f n if V n and V n V n
f if V n 0 ( ) ( 1)
( )( )
( ) 0 ( ) ( 1)
error error
errorDPWM steady DPWM steady DPWM min
error peak
error error error
and V n V n
V nf f f
V
if V n and V n V n
(5.4)
5.4. Theoretical Analysis
If peakAV is the peak voltage, AT is the time period of the ramp signal and cAV is the value of
compensated error signal, as illustrated in Figure. 5.2(b) ( cA cV V ), then the duty ratio is given
by Eq. (4.5).
cAA
peakA
VD
V (5.5)
In the case of constant frequency DPWM, with 1AT and 1peakAV as the time period and peak
value of ramp signal, respectively. If cAV is the change in compensated error signal value, then
the new duty cycle due to the change in compensated error signal is given by Eq. (5.6)
1 11 1
1
cA cAA A
peakA
V VD D
V (5.6)
The relative change in duty cycle is given by Eq. (5.7)
98
11
1 1
cAA
A cA
VD
D V (5.7)
Similarly, consider the DVSF case. Let the change in the time period be given by
2 1A AT T k V , and the change in peak value as a result of this is given by
2 1 1peakA peakAV V k V , where V is the deviation in output voltage relative to reference
voltage ( ref outV V ). k and 1k are constants that determine the change in the time period and
peak value of ramp signal, respectively.
Therefore, the change in duty cycle is given by Eq. (5.8)
1 12 2
1 1
cA cAA A
peakA
V VD D
V k V (5.8)
The relative change in duty cycle is given by Eq. (5.9)
1 1 1 12
2 1 1 1
11 1
1 1
1 1 1
11 1
11
1 1 1
( )
cA peakA cAA
A cA peakA
cApeakA
cA cA
cA peakA
cApeakA
cAA
A peakA
V V k V VD
D V V k V
VV k V
V V
V V k V
VV k V
VD
D V k V
(5.9)
11 1 1 1
1
1 1 1 1
1 1
0, 0
cApeakA peakA
cA
cA cA
cA cA
VNumerator Denominator V k V V k V
V
V Vk V V since k
V V
Numerator Denominator
99
2 1
2 1
A A
A A
D D
D D (5.10)
From Eq. (5.10), it can be observed that the relative change in the duty cycle is more in the
case of Variable Switching Frequency compared to constant switching frequency. In other
words, the deviation in error signal required to bring about the same change in duty cycle value
is less in case of Variable Switching Frequency Case, compared to the Constant Switching
Frequency case. Hence, the dynamic performance is improved with the implementation of
Variable Switching Frequency.
5.5. Experimantal Prototype Results
A proof of concept experimental prototype is developed in the laboratory in order to verify the
proposed dynamic switching frequency variation control. The prototype is a single-phase DC-DC
buck converter with a nominal input of 10V and a nominal output voltage of 1.5V. The power
stage output filter capacitance is 1mF and the output power inductor value is 440nH . The
steady-state switching frequency is 342KHz . The controller and the control law are implemented
using an FPGA (Field Programmable Gate Array) “Altera Cyclone II EP2C35F672C6”.
5.5.1. DVSF I
The experimental results with DVSF I controller are shown in Figure 5.9 and Figure. 5.10.
Figure. 5.9(a) shows the variation of output voltage during a 5A to 0A step-down load transient
with a constant switching frequency. Figure. 5.9(b) shows the response during the same load
conditions when using the DVSF I controller. Figure. 5.10(a) shows the variation of output
voltage during a 0A to 5A step-up load transient with a constant switching frequency.
100
Figure 5.8(b) shows the response during the same load conditions when using the DVSF I
controller.
70mV
5A
(a)
50mV
5A
(b)
Top Trace: Output Voltage (50mV/div, 50µs/div.) and Bottom Trace: Inductor Current (5A/div.,
50µs/div.).
Figure. 5.9: Experimental results of the prototype with zoomed in view under dynamic load step-
down transient of 5A-0A (a) with fixed frequency DPWM and (b) with variable frequency
DPWM.
It can be observed from the experimental results of Figure. 5.9 and Figure. 5.10 that the
DVSF I control results in dynamic performance improvement. For this particular design
101
example, there is an improvement of 8.5mV (about 13%), during step up load transients and an
improvement of 19.5 mV (about 27%), during step down load transient.
70mV
5A
(a)
63mV
5A
(b)
Top Trace: Output Voltage (50mV/div, 50µs/div.) and Bottom Trace: Inductor Current (5A/div.,
50µs/div.).
Figure. 5.10: Experimental results of the prototype with zoomed in view under dynamic load
step-down transient of 0A-5A (a) with fixed frequency DPWM and (b) with variable frequency
DPWM.
102
5.5.2. DVSF II
The experimental results for the DVSF II controller are shown in Figure. 5.11 and Figure.
5.12. Figure. 5.11(a) shows the output voltage response during a 5A to 0A load step-down
transient without the DVSF II controller being activated while Figure. 5.11(b) shows the
response under the same load conditions when the DVSF II controller is activated. Figure. 5.12
shows similar results under 0A to 5A load step-up transient.
70mV
5A
(a)
50mV
5A
(b)
Top Trace: Output Voltage (50mV/div, 50µs/div.) and Bottom Trace: Inductor Current (5A/div.,
50µs/div.).
Figure. 5.11: Experimental results of the prototype with zoomed in view under dynamic load
step-down transient of 5A-0A (a) with fixed frequency DPWM and (b) with adaptive frequency
DPWM.
103
It can be observed from the experimental results of Figure. 5.11 and Figure. 5.12 that the
DVSF II control law results in dynamic performance improvement. For this particular design
example, there is an improvement of 14 mV (about 22%) during load step-up transient, and an
improvement of 20mV (about 27%), during load step-down load transient.
70mV
5A
(a)
60mV
5A
(b)
Top Trace: Output Voltage (50mV/div, 50µs/div.) and Bottom Trace: Inductor Current (5A/div.,
50µs/div.).
Figure. 5.12: Experimental results of the prototype with zoomed in view under dynamic load
step-up transient of 0A-5A (a) with fixed frequency DPWM and (b) with adaptive frequency
DPWM.
104
The comparison in the improvements of dynamic performance using DVSF I and DVSF II is
shown in Table 5.1. From Table 5.1, it can be observed that the improvement in the dynamic
performance is relatively better using DVSF II compared to DVSF I. Hence, it can be concluded
that DVSF II is superior compared to DVSF I.
Table 5.1 : Comparison of improvement in overshoot using different DVSF control methods
Control
method
Improvement in
Overshoot
(% improvement)
Improvement in
Undershoot
(% improvement)
DVSF I 19.5mV (27%) 8.5mV (13%)
DVSF II 20mV (27%) 14mV (22%)
5.6. Summary
This chapter proposes and compares two dynamic digital variable switching frequency control
schemes (DVSF I and DVSF II), in order to improve the dynamic performance of DC-DC power
converters. The proposed control laws dynamically vary the switching frequency depending on
the magnitude and type of transient as a function of error signal. This results in output voltage
overshoot/undershoot reduction during transients. The principle of operation, algorithm,
theoretical proof, hardware implementation, and experimental results of the dynamic digital
switching frequency controllers are proposed in this chapter, and compared with the fixed
switching frequency case. From the experimental results, it can be noticed that the improvement
achieved using DVSF II is more compared to the improvement obtained using DVSF I.
105
CHAPTER 6
CONCLUSIONS AND FUTURE WORK
6.1. Summary of Conclusions
Tight regulation of the output voltage of power converters is critical and has very strict
requirements in many applications. The tight regulation requirements, in addition to size and
weight requirements, are getting stricter by time, which makes it necessary to investigate new
control concepts in order to meet these requirements. Not meeting the tight regulation
requirements may result in either the malfunctioning of the device (load) being powered, or the
destruction of that device.
In this dissertation research work, several control concepts and techniques have been proposed
in order to improve the dynamic performance (tighter dynamic regulation) of the power
converter. The contribution of this work include the research and development of the following
concepts: (1) Sensorless adaptive voltage positioning control scheme that does not require the
sensing of the inductor’s current or output/load current [F1]; (2) Adaptive Digital PID control
scheme that improve the dynamic performance of power converters without the need to increase
the size of the power converter (no need to add additional filter capacitors), and without reducing
the power converter efficiency (no need to increase the switching frequency) [F2, F3, F6]; (3)
Compensated Error Observe and Modulate (CEO &M) method for the optimal design, and auto
tuning of closed-loop compensator in order to obtain an initial closer-to-optimal closed-loop
106
controller design (for better dynamic performance) and be able to adaptively auto-tune the design
under non-ideally varying component characteristics (e.g. parasitic capacitances and resistances)
and varying operating conditions (load and line) and (4) Dynamic digital Variable Switching
Frequency (DVSF) control schemes to improve the dynamic performance of power converters
without increasing the size and weight of the power converter [F4, F5]. The performance of these
concepts and schemes were evaluated and verified experimentally.
6.1.1. Digital Sensorless Adaptive Voltage Positioning Control Scheme
The work presented in this dissertation proposes a digital sensorless adaptive voltage
positioning control scheme that does not require sensing inductor current or output current for
the implementation of Adaptive Voltage Positioning control. The controller utilizes the duty
cycle value of the power converter for the sensorless implementation of AVP. The proposed
method eliminates the need for any sensing circuitry, and therefore, the losses associated with
them. Moreover, it reduces the hardware that is required for the AVP implementation and
therefore cost is also reduced. Different operating conditions like fixed input voltage, variable
input voltage, fixed nominal output voltage, variable nominal output voltage conditions are
analyzed, and the necessary equations for the SLAVP implementation at these operating
conditions are derived. The experimental results demonstrate the effectiveness of the proposed
control scheme.
6.1.2. An Adaptive Digital PID Controller for Power Converters
The work presented in this dissertation proposes an adaptive digital PID controller method
that improves the dynamic performance of power converter. The limitations of the fixed
bandwidth compensators are discussed, and the control law for the implementaion of the AD-
107
PID controller is given. The AD-PID reduces the dynamic output voltage deviation and settling
time by using a relatively simple strategy and without the need to sense any additional
information other than the output voltage of the power converter. The AD-PID controller
adaptively varies the parameters of PID compensator as a fucntion of the error signal and adjusts
it self to different transients’ magnitudes and types. The theoratical and practical guidelines for
the design and selection of various parameters of AD-PID controller are discussed. The
experimental results show that there is an improvement in the dynamic performance of power
converter with AD-PID controller compared to conventional PID compensator. This
improvement is achived (a) without adding any additional components such as filter capacitors
and switches, and (b) without reducing the power converter efficiency such as by increasing the
switching frequency or reducing the power inductor value which will increase power losses.
6.1.3.A Novel Adaptive Auto-Design and Auto-Tuning Method for Closed-Loop
Controllers of Power Converters
The closed-loop controller design is based on conventional rule of thumb design methods and
guidelines such as phase and gain margin with bode-plot based methods. The work presented in
this dissertation has proposed the CEO&M method in order to be able to design and adaptively
auto-tune the closed-loop compensator of power converter for a closer-to-optimal dynamic
performance under varying load and line conditions, and under varying component
characteristics. The CEO&M concept is based on time domain characteristics of the
compensated error signal. The CEO&M observes the peak-to-peak value ( e ppV ) and frequency
( Ve compf ) of compensated error signal to tune the parameters of the compensator. The proposed
method does not require the knowledge of the power stage frequency response (transfer
function), does not depend on any conventional rule of thumb control design criteria such as gain
108
and phase margins, and depends only on the time domain characteristics of the compensated
error signal. The experimental results demonstrate that the CEO&M method is valid and can be
used for design of compensator.
An online closed-loop-compensator auto-tuning digital controller (ATerror controller) based
on the CEO&M method is also proposed. The digital implementation algorithm, architecture,
and a proof-of-concept experimental prototype results are presented for the ATerror controller.
The ATerror Controller resulted in a close to optimum design with improved dynamic
performance without additional power stage components.
6.1.4. An Adaptive Digital Variable Frequency Control Scheme
The work presented in this dissertation has proposed control methods that adaptively vary the
switching frequency of power converters in order to improve the dynamic performance.
Additional power stage components are not needed. The proposed control laws dynamically vary
the switching frequency depending on the magnitude and type of transient as a function of error
signal. This results in output voltage overshoot/undershoot reduction during transients. The
control law, principle of operation, algorithm, theoretical proof, and hardware implementation of
the adaptive digital variable frequency controllers are presented and compared with the fixed
switching frequency case.
6.1.5. Additional Comments on the Use of the Proposed Concepts
The SLAVP adjusts the voltage value within a window and the AD-PID concept can be used
to reduce the output voltage overshoot/undershoot outside the SLAVP window, and therefore,
they can be combined together to achieve combined dynamic response improvement. The
ATerror controller based on the CEO&M concept can be used during the power converter
109
operation with the SLAVP concept, with the AD-PID concept, and with the DVSF concept in
order to auto-tune the closed-loop compensator parameters under varying conditions and
component values, and it also can be used during the initial design of the compensator. Figure
6.1 illustrates how these concepts may be used together. The combinations of these concepts are
part of a future work. The choice of how many of these concepts should be combined will be
based on the specific application, power converter topology, requirements, complexity, size, and
controller cost, among others. The combination between the AD-PID concept, and the DVSF
concept is more complex and requires significant additional investigation that may result in a
newly modified concept based on the two original concepts.
maxoI
minoI
maxoV
minoV
Output Current
CEO&M
Concept
SLAVP Controller
AD-PID
and/or
DVSF
Controller
Figure 6.1: Illustration of different adaptive concepts utilization.
110
6.2. Future Research Directions
The following subsections provide a brief outlook on some possible future research directions
that are related to the work presented in this dissertation.
6.2.1. Application of Proposed Control Schemes for Multiphase Buck Converter
The application of proposed SLAVP, ADPID, auto-tuning and DVSF control schemes for
multiphase buck converters needs further investigation in future. Some of the possible
considerations that are related to this include the conservation of current sharing during adaptive
operation and phases synchronization during the adaptive operation.
6.2.2. Application of Auto-Tuning and Auto-Design Technique for Pole and Zero Variation
The auto-tuning and auto-design scheme proposed in this work is utilized to vary the gain of
the compensator. The variation of poles and/or zeros alone or variation of multiple variables
(gain, pole, zero) of the compensator based on the proposed control scheme need further
investigation in future. The development of algorithms for the variation of multiple variables and
the optimum value recognition, among others, is needed. This may need further insight into
optimization theory that determines the possible ways to achieve the optimum performance in
least number of steps.
6.2.3. Combined Utilization of Proposed Control Schemes
The work presented in this dissertation proposes several adaptive control concepts to improve
the dynamic performance of power converters. The combined utilization and implementation of
proposed control schemes is a future research direction. The initial design of the compensator
can be accomplished by utilizing CEO&M concept. The Adaptive Voltage Positioning can be
111
implemented with SLAVP control scheme. The overshoot/undershoot reduction beyond the
SLAVP window can be achieved by using the AD-PID concept and/or the DVSF concept. This
is illustrated in Figure. 6.1. The considerations involved with this combination are (1) CEO&M
concept utilizes multi-sampled output voltage for its implementation whereas SLAVP control
concept is implemented by utilizing a single sample per switching cycle. Therefore, SLAVP
control scheme need to be adapted to multi-sampled implementation as discussed in Section
6.2.4. (2) AD-PID and DVSF control schemes can be implemented for either single sampled or
multi-sampled output voltage. However, when DVSF is utilized for overshoot/undershoot
reduction, the duty cycle value varies (in digital controller) depending on the switching
frequency. A scheme needs to be developed in the future to address this nature.
6.2.4. Application of SLAVP Control Scheme for Multi-Sampled Implementation
The proposed SLAVP controller utilizes one sample of duty ratio (D) per switching cycle for
its implementation. However, the response of the compensator improves with the multi-sample
implementation. Therefore, the SLAVP control scheme for multi-sample utilization of
compensated error signal need to be investigated. The possible challenges with this include the
dependence/variation of values of control variables based on the sample being used and the
limitations of the clock speed of the digital controller to make the necessary calculations, among
others.
6.2.5. Optimization of the Digital Controller Realization and Implementation
The concepts presented in this dissertation are realized by a digital implementation for
verification. Future research direction may consider the optimization of the digital
112
implementation to decrease the size (e.g. less number of logic gates), reduce controller power
consumption, and increase speed.
6.2.6. Application of Proposed Control Schemes for Other Topologies
The application of proposed SLAVP, ADPID, auto-tuning and DVSF concepts for other
isolated and non-isolated topologies including and not limited to isolated buck, isolated and non-
isolated boost, and buck-boost converters need to be investigated in the future. Applying these
concepts to other power converter topologies may require some modifications to the concepts
and related control laws presented in this work.
113
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[B28] Yoichi Ishizuka, Masao Ueno, Ichiro Nishikawa, Akira Ichinose, and HirofumiMatsuo,
“A Low-Delay Digital PWM Control Circuit for DC/DC converters”, IEEE Applied
Power Electronics Conference, APEC 2007 - Feb. 25 2007-March 1 2007, pp.579 – 584.
[B29] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, “Digital pulse width modulator
architectures” IEEE Power Electronics Specialists Conference, PESC’04, Vol. 6, pp.
4689-4695.
[B30] L. Corradini, A. Costabeber, P. Mattavelli, and S. Saggini, “Time optimal, parameters-
insensitive digital controller for VRM applications with Adaptive Voltage Positioning”,
Control and Modeling for Power Electronics, 2008. COMPEL 2008. 17-20 Aug. 2008 pp.
1 - 8 .
[B31] A. V. Peterchev, Jinwen Xiao, and S.R. Sanders, “Architecture and IC implementation of
a digital VRM controller,” IEEE Transactions on Power Electronics, Vol. 18, No.1, pp.
356-364, 2003.
[B32] B. Miao, R. Zane, and D. Maksimović, “Automated Digital Controller Design for
Switching Converters,” 36th Annual IEEE Power Electronics Specialists Conference,
PESC'05, pp. 2729 – 2735, 2005.
[B33] Jaber Abu-Qahouq, Lilly Huang, and Douglas Huard, “Sensor-less Current Sharing
Analysis and Scheme for Multiphase Converters,” IEEE Transactions on Power
Electronics, Vol. 23, No. 5, pp. 2237-2247, 2008.
[B34] L. Corradini, A. Costabeber, P. Mattavelli, and S. Saggini, “Parameter-Independent
Time-Optimal Digital Control for Point-of-Load Converters”, IEEE Transactions on
Power Electronics, Vol. 24, No. 10, pp. 2235 – 2248, 2009.
[B35] L. Corradini, E. Orietti, P. Mattavelli, and S. Saggini, “Digital hysteretic voltage-mode
control for DC-DC converters based on asynchronous sampling,” IEEE Transactions on
Power Electronics, Vol. 24, No. 1, pp. 201–211, 2009.
[B36] Z. Zhao, and A. Prodic, “Continuous-time digital controller for high-frequency DC-DC
converters,” IEEE Transactions on Power Electronics, Vol. 23, No. 2, pp. 564–573, 2008.
120
[B37] Jaber Abu-Qahouq, Wisam Al-Hoor, Wasfy Michael, Lilly Huang and Issa Batarseh,
“Analysis and Design of an Adaptive-Step-Size Digital Controller For Switching
Frequency Auto-Tuning,” IEEE Transactions on Circuits and Systems I - Regular Papers,
Vol. 56, No. 12, pp. 2749 - 2759, 2009.
[B38] P. Midya, P. T. Krein, and M. F. Greuel, “Sensorless current mode control—An
observer-based technique for DC–DC converters,” IEEE Transactions on Power
Electronics, Vol. 16, No. 4, pp. 522–526, 2001.
[B39] M. Ferdowsi, and A. Emadi, “Estimative current mode control technique for DC–DC
converters operating in discontinuous conduction mode,” IEEE Transactions on Power
Electronics, Vol. 2, No. 1, pp. 20–23, 2004.
[B40] A. Kelly, and K. Rinne, “Sensorless current-mode control of a digital deadbeat DC–DC
converter,” in Proc. 19th Annu. IEEE APEC, Feb. 2004, Vol. 3, pp. 1790–1795.
[B41] S. Mishra, and X. Zhou, “Design Considerations for a Low-Voltage High-Current
Redundant Parallel Voltage Regulator Module System”, IEEE Transactions on Industrial
Electronics, Vol. 58, No. 4, pp. 1330-1338, 2011.
[B42] Jianping Xu, Guohua Zhou and Mingzhi He, “Improved Digital Peak Voltage Predictive
Control for Switching DC–DC Converters”, IEEE Transactions on Industrial Electronics,
Vol. 56, No. 8, pp. 3222 – 3229, 2009.
[B43] Y.-S. Lai, and C.-A. Yeh, “Predictive Digital-Controlled Converter With Peak Current-
Mode Control and Leading-Edge Modulation,” IEEE Transactions on Industrial
Electronics, Vol. 56, No. 6, pp. 1854-1863, 2009.
[B44] F. Luo, and D. Ma, "Design of Digital Tri-mode Adaptive-Output Buck Boost Power
Converter for Power-Efficient Integrated Systems," IEEE Transactions on Industrial
Electronics, Vol. 57, No. 6, pp.2151 - 2160, 2010.
[B45] F. Gonzalez-Espin, E. Figueres, G. Garcera, R. Gonzalez-Medina, and M. Pascual,
"Measurement of the Loop Gain Frequency Response of Digitally Controlled Power
Converters," IEEE Transactions on Industrial Electronics, Vol. 57, No. 8, pp. 2785 -
2796, 2010.
[B46] G. Foo, and M. F. Rahman, “Sensorless Sliding-Mode MTPA Control of an IPM
Synchronous Motor Drive Using a Sliding-Mode Observer and HF Signal Injection,”
IEEE Transactions on Industrial Electronics, Vol. 57, No. 4, pp. 1270 - 1278, 2010.
[B47] F. Genduso, R. Miceli, C. Rando, and G. R.Galluzzo, , "Back EMF Sensorless-Control
Algorithm for High-Dynamic Performance PMSM," IEEE Transactions on Industrial
Electronics, Vol. 57, No. 6, pp.2092 - 2100, 2010.
[B48] A. De Nardo, N. Femia, G. Petrone, G. Spagnuolo, “Optimal Buck Converter Output
Filter Design for Point-of-Load Applications,” IEEE Transactions on Industrial
Electronics, Vol. 57, No. 4, pp. 1330 - 1341, 2010.
121
CHAPTER 3
[C1] W. Y. Wang, H. H. C. Iu, W. Du, and V. Sreeram, “Multiphase dc-dc converter with high
dynamic performance and high efficiency,” IET Power Electronics, Vol. 4, No. 1, pp.
101-110, 2011.
[C2] A. Yazdani, and R. Iravani, “Control of high-performance switched-mode rectifier
system,” IET Power Electronics, Vol. 152, No. 6, pp. 1451-1458, 2005.
[C3] C. E. Carrejo, E. Vidal-Idiarte, R. Giral, and L. Martinez-Salamero, “Predictive digital
interpolation current control for DC-DC power converters,” IET Power Electronics, Vol.
2, No. 5, pp. 545-554, 2009.
[C4] L. Corradini, A. Costabeber, P. Mattavelli, and S. Saggini, “Time optimal, parameters-
insensitive digital controller for VRM applications with adaptive voltage positioning,”
11th Workshop on Control and Modeling for Power Electronics, pp. 1-8, 2008.
[C5] A. H. Bhat, and P. Agarwal, “DSP-based implementation of capacitor voltage balancing
strategy for a three-phase three-level bidirectional rectifier,” IET Power Electronics, Vol.
2, No. 4, pp. 375-386, 2009.
[C6] D. Maksimovic, R. Zane, and R. Erickson, “Impact of digital control in power
electronics,” Proceedings of the 16th International Symposium on Power Semiconductor
Devices and ICs, 2004, pp. 13-22.
[C7] T. W. Martin, and S. S. Ang, “Digital control for switching converters,” Proceedings of
the IEEE International Symposium on Industrial Electronics, 1995, pp. 480-484.
[C8] D. Trevisan, P. Mattavelli, P. Tenti, “Digital control of single-inductor multiple-output
step-down DC–DC converters in CCM,” IEEE Transactions on Industrial Electronics,
Vol. 55, No. 9, pp. 3476-3483, 2008.
[C9] Ye-Then Chang, and Yen-Shin Lai “Effect of sampling frequency of A/D converter on
controller stability and bandwidth of digital-controlled power converter,” 7th
International Conference on Power Electronics, 2007, pp. 625-629.
[C10] A. J. Forsyth, and Y. K. E.: Ho, “High performance control of the series-parallel
resonant converter,” IET Power Electronics, Vol. 144, No. 2, pp. 131-139, 1997.
[C11] A. E. Leon, J. A. Solsona, and M. I. Valla, “Exponentially convergent estimator to
improve performance of voltage source converters,” IET Power Electronics, Vol. 3, No.
5, pp. 668-680, 2010.
[C12] Kaiwei Yao, Yuancheng Ren, and F. C. Lee “Critical bandwidth for the load transient
response of voltage regulator modules,” IEEE Transactions on Power Electronics, Vol.
19, No. 6, pp. 1454-1461, 2004.
122
[C13] S. Chen, Y. M. Lai, S. -C. Tan, and C. K. Tse, “Fast response low harmonic distortion
control scheme for voltage source inverters,” IET Power Electronics, Vol. 2, No. 5, pp.
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[C14] V. Yousefzadeh, and S. Choudhury, “Nonlinear digital PID controller for DC-DC
converters,” Twenty-Third Annual IEEE Applied Power Electronics Conference and
Exposition, 2008, pp. 1704-1709.
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[C17] Liping Guo, J. Y. Hung, and R. M. Nelms “PID controller modifications to improve
steady-state performance of digital controllers for buck and boost converters,”
Seventeenth Annual IEEE Applied Power Electronics Conference and Exposition, 2002,
pp. 381-388.
[C18] D. Garcia, A. Karimi, and R. Longchamp, “Robust PID controller tuning with
specification on modulus margin,” Proceedings of the 2004 American Control
Conference, 2004, Vol. 4, pp. 3297-3302.
[C19] W. K. Ho, O. P. Gan, E. B. Tay, and E. L. Ang: ‘Performance and gain and phase
margins of well-known PID tuning formulas’, IEEE Transactions on Control Systems
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[C20] Y. Duan, and H. Jin, “Digital controller design for switch mode power converters,”
Fourteenth Annual Applied Power Electronics Conference and Exposition, 1999, pp.
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[C21] Liping Guo, J. Y. Hung, and R. M. Nelms, “Evaluation of DSP-based PID and fuzzy
controllers for DC–DC converters,” IEEE Transactions on Industrial Electronics, Vol. 56,
No. 6, pp. 2237-224, 2009.
[C22] Haitoa Hu, V. Yousefzadeh, and D. Maksimovic, “Nonlinear control for improved
dynamic response of digitally controlled DC-DC converters,” 37th IEEE Power
Electronics Specialists Conference, 2006, pp. 1-7.
[C23] R. C.Loxton, K. L. Teo, V. Rehbock, and W. K. Ling, “Optimal switching instants for a
switched-capacitor DC/DC power converter,” Automatica, Vol. 45, No. 4, pp. 973-980,
2009.
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123
[C25] Robert W. Erickson, Dragan Maksimovic, “Fundamentals of power electronics,” 2nd
edition, Springer, 2001.
[C26] V. Arikatla, and J. A. Abu Qahouq, “An Adaptive Digital PID controller scheme for
power converters,” IEEE Energy Conversion Congress and Exposition, 2010, pp. 223-
227.
[C27] J. A. Abu Qahouq, V. Arikatla, Thanukamalam Arunachalam, “Modified Digital Pulse
Width Modulator for Power Converters with Reduced Modulation Delay,” Journal of
Power Electronics, Accepted in October 2011 for Publication.
CHAPTER 4
[D1] M. Castilla, L. G. de Vicuna, J. M. Guerrero, J. Matas, and J. Miret, “Designing VRM
hysteretic controllers for optimal transient response,” IEEE Transaction on Industrial
Electronics, Vol. 54, No. 3, pp. 1726–1738, 2007.
[D2] S. Lim, J. Fan, and A. Huang, “Transient Voltage Clamp (TVC) Circuit Design Based on
Constant Load Line Impedance for Voltage Regulator Module (VRM)”, IEEE
Transactions on Industrial Electronics, Vol. 57 , No. 12, pp. 4085 – 4094, 2010.
[D3] J. A. Abu Qahouq, V. P. Arikatla, “Power Converter with Digital Sensorless Adaptive
Voltage Positioning Control Scheme,” IEEE Transactions on Industrial Electronics, Vol.
58, No. 9, pp. 4105 - 4116, 2011.
[D4] S.K. Mishra, “ Design-Oriented Analysis of Modern Active Droop-Controlled Power
Supplies”, IEEE Transactions on Industrial Electronics, Vol. 56, Vo. 9, pp. 3704 – 3708,
2009.
[D5] F. Zhang, and Y. Yan, "Start-Up Process and Step Response of a DC¨CDC Converter
Loaded by Constant Power Loads," IEEE Transactions on Industrial Electronics, Vol. 58,
No. 1, pp. 298 – 304, 2011.
[D6] M. Jinno, P.-Y. Chen, Y.-C. Lai, and K. Harada, “Investigation on the Ripple Voltage
and the Stability of SR Buck Converters With High Output Current and Low Output
Volt,” IEEE Transactions on Industrial Electronics, Vol. 57, No. 3, pp. 1008-1016.
[D7] G. Feng , E. Meyer, and Y.-F. Liu, "A new digital control algorithm to achieve optimal
dynamic performance in DC-to-DC converters," IEEE Transactions on Power
Electronics, Vol. 22, No. 4, pp. 1489 – 1498, 2007.
[D8] Z. Lukić, Z. Zhao, S. M. Ahsanuzzaman, and A. Prodić, “Self-Tuning Digital Current
Estimator for Low-Power Switching Converters,” IEEE Applied Power Electronics
Conference and Exhibition, APEC’2008, pp. 529 - 534.
124
[D9] B. Miao, R. Zane, and D. Maksimović, “Automated Digital Controller Design for
Switching Converters,” 36th Annual IEEE Power Electronics Specialists Conference,
PESC'05 Record. , 2005, pp. 2729 – 2735.
[D10] D. Maksimovic, R. Zane, and R. Erickson, “Impact of digital control in power
electronics,” The 16th International Symposium on Power Semiconductor Devices and
ICs 2004, Proceedings ISPSD '04, pp. 13-22.
[D11] Liping Guo, J.Y. Hung, and R.M. Nelms, “Evaluation of DSP-Based PID and Fuzzy
Controllers for DC–DC Converters,” IEEE Transactions on Industrial Electronics, Vol.
56, No. 6, pp. 2237 – 2248, 2009.
[D12] T.W. Martin, and S.S. Ang, “Digital control for switching converters,” Proceedings of the
IEEE International Symposium on Industrial Electronics, 1995, pp. 480-484.
[D13] D. Trevisan, P. Mattavelli, and P. Tenti, “Digital control of single-inductor multiple-
output step-down DC–DC converters in CCM,” IEEE Transactions on Industrial
Electronics, Vol. 55, No. 9, pp. 3476-3483, 2008.
[D14] Sanbao Zheng, and D. Czarkowski, “Modeling and Digital Control of a Phase-Controlled
Series–Parallel Resonant Converter,” IEEE Transactions on Industrial Electronics, Vol.
54, No. 2, pp. 707-715, 2007.
[D15] Y. Qiu, H. Liu, X. Chen, “Digital Average Current-Mode Control of PWM DC-DC
Converters Without Current Sensors,” IEEE Transactions on Industrial Electronics, Vol.
57 , No. 5, pp. 1670 – 1677, 2010.
[D16] Jianping Xu, Guohua Zhou, and Mingzhi He, “Improved Digital Peak Voltage Predictive
Control for Switching DC–DC Converters,” IEEE Transactions on Industrial Electronics,
Vol. 56, No. 8, pp. 3222 - 3229, 2009.
[D17] Ye-Then Chang, and Yen-Shin Lai, “Effect of sampling frequency of A/D converter on
controller stability and bandwidth of digital-controlled power converter,” 7th
International Conference on Power Electronics 2007, pp. 625-629.
[D18] Feng Luo, Dongsheng Ma, “Design of Digital Tri-mode Adaptive-Output Buck–Boost
Power Converter for Power-Efficient Integrated Systems,” IEEE Transactions on
Industrial Electronics, Vol. 57, No. 6, pp. 2151 - 2160, 2010.
[D19] A. Costabeber, P. Mattavelli, S. Saggini, and A. Bianco, “Digital Autotuning of dc-dc
Converters Based on Model Reference Impulse Response,” IEEE Applied Power
Electronics Conference and Exhibition, APEC’2010, pp. 1287 - 1294.
[D20] W. Stefanutti, P. Mattavelli, S. Saggini, and M. Ghioni, “Autotuning of digitally
controlled buck converters based on relay feedback,” IEEE Transactions on Power
Electronics, Vol. 22, No. 1, pp. 199–207, 2007.
125
[D21] J. Morroni, R. Zane, and D. Maksimovic, “Design and implementation of an adaptive
tuning system based on desired phase margin for digitally controlled DC-DC converters,”
IEEE Transactions on Power Electronics, Vol. 24, No. 2, pp. 559–564, 2009.
[D22] S. Saggini, W. Stefanutti, E. Tedeschi, and P. Mattavelli, “Digital Deadbeat Control
Tuning for dc-dc Converters Using Error Correlation,” IEEE Transactions on Power
Electronics, Vol. 22, No. 4, pp. 1566 - 1570, 2007.
[D23] S. Saggini, A. Costabeber, and P. Mattavelli, “A Simple Digital Autotuning For Analog
Controller in SMPS,” IEEE Transactions on Power Electronics, Vol. 25, No. 8, pp. 2170
- 2178, 2010.
[D24] A. Costabeber, P. Mattavelli, S. Saggini, and A. Bianco, “Digital Autotuning of dc-dc
Converters Based on Model Reference Impulse Response,” IEEE Transactions on Power
Electronics, Vol. 26, No. 10, pp. 1287 – 1294, 2011.
[D25] J. Morroni, L. Corradini, R. Zane, and D. Maksimovic, “Adaptive Tuning of Switched-
Mode Power Supplies Operating in Discontinuous and Continuous Conduction Modes,”
IEEE Transactions on Power Electronics, vol. 24, No. 11, pp. 2603 - 2611, 2009.
[D26] Yang Qiu, Kaiwei Yao, Yu Meng, Ming Xu, F.C. Lee, and Mao Ye, “Control-loop
bandwidth limitations for multiphase interleaving buck converters,” Annual IEEE
Applied Power Electronics Conference and Exposition, 2004. APEC '04., Vol. 2, No. 2,
pp. 1322 - 1328.
[D27] Yang Qiu, Ming Xu, Kaiwei Yao, Yu Meng, J. Sun, and F.C. Lee, “Multifrequency
Small-Signal Model for Buck and Multiphase Buck Converters,” IEEE Transactions on
Power Electronics, Vol. 21, No. 5, pp. 1185 - 1192, 2006.
[D28] Yang Qiu, Juanjuan Sun, Ming Xu, Kisun Lee, and F.C. Lee, “Bandwidth Improvements
for Peak-Current Controlled Voltage Regulators,” IEEE Transactions on Power
Electronics, Vol. 22, No. 4, pp. 1253 - 1260, 2007.
[D29] J. Quintero, A. Barrado, M. Sanz, C. Raga, and A. Lazaro, “Bandwidth and Dynamic
Response Decoupling in a Multi-phase VRM by applying Linear-Non-Linear Control,”
IEEE International Symposium on Industrial Electronics, 2007. ISIE 2007., pp. 3373 -
3378.
[D30] Kaiwei Yao, Yu Meng, and F.C. Lee, “Control bandwidth and transient response of buck
converters,” IEEE 33rd Annual Power Electronics Specialists Conference, 2002. pesc
02., pp. 137 - 142.
[D31] L. Corradini, P. Mattavelli, E. Tedeschi, and D. Trevisan, “High-bandwidth multisampled
digitally controlled DC–DC converters using ripple compensation,” IEEE Transactions
on Industrial Electronics, Vol. 55, No. 4, pp. 1501-1508, 2008.
[D32] VaraPrasad Arikatla, and Jaber Abu Qahouq, “Multisampled Digital Controller
Simulation Model and Adaptive Design for DC-DC Power Converters,” the Journal of
126
International Review on Modelling and Simulations (I.RE.MO.S.), Vol. 4, No.4, August
2011.
CHAPTER 5
[E1] Xunwei Zhou, Pit-Leong Wong, Peng Xu, F.C. Lee, and A. Q. Huang, “Investigation of
candidate VRM topologies for future microprocessors,” IEEE Transactions on Power
Electronics, Vol. 15, No. 6, pp. 1172 – 1182, 2000.
[E2] G. Ortiz, D. Bortis, J. Biela, and J. W. Kolar, “Optimal Design of a 3.5-kV/11-kW DC–
DC Converter for Charging Capacitor Banks of Power Modulators,” IEEE Transactions
on Plasma Science, Vol. 38, No. 10, pp. 2565 - 2573, 2010.
[E3] A. Dolgov, R. Zane, and Z. Popovic, “Power Management System for Online Low Power
RF Energy Harvesting Optimization,” IEEE Transactions on Circuits and Systems I, Vol.
57, No. 7, pp. 1802 - 1811, 2010.
[E4] Hui Li, Fang Zheng Peng, and J. S. Lawler, “A natural ZVS medium-power bidirectional
DC-DC converter with minimum number of devices,” IEEE Transactions on Industry
Applications, Vol. 39, No. 2, pp. 525 - 535, 2003.
[E5] A. Emadi, S. S. Williamson, and A. Khaligh, “Power electronics intensive solutions for
advanced electric, hybrid electric, and fuel cell vehicular power systems,” IEEE
Transactions on Power Electronics, Vol. 21, No. 3, pp. 567 - 577, 2006.
[E6] Y. S. Lee, S. J. Wang, and S. Y. R. Hui, “Modeling, Analysis, and Application of Buck
Converters in Discontinuous-Input-Voltage Mode Operation,” IEEE Transactions on
Power Electronics, Vol. 12, No. 2, pp. 350–360, 1997.
[E7] Jean Paulo Rodrigues, Samir Ahmad Mussa, Marcelo Lobo Heldwein, and Arnaldo Jos´e
Perin, “Three-Level ZVS Active Clamping PWM for the DC–DC Buck Converter,”
IEEE Transactions on Power Electronics, Vol. 24, No. 10, pp. 2249–2258, 2009.
[E8] B.J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM
controller IC for DC-DC converters”, IEEE Transactions on Power Electronics, Vol. 18,
No. 1, Part 2, pp. 438 – 446, 2003.
[E9] V. Yousefzadeh, T. Takayama, and D. Maksimovic, “Hybrid DPWM with Digital Delay-
Locked Loop,” 2006 IEEE Computers in Power Electronics Workshop, 2006, pp. 142-
148.
[E10] A. Syed, E. Ahmed, E. Alarcon, and D. Maksimovic, “Digital Pulse Width Modulator
Architectures,” 35th Annual IEEE Power Electronics Specialist Conference, 2004, pp.
4689-4695.
127
[E11] O. Trescases, Guowen Wei, and Wai Tung Ng, “A Segmented Digital Pulse Width
Modulator with Self-Calibration for Low-Power SMPS,” IEEE Conference on Electronic
Devices and Solid-State Circuits, 2005, pp.367-370.
[E12] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, “An ultra-low-power digitally-
controlled buck converter IC for cellular phone applications,” Nineteenth Annual IEEE
Applied Power Electronics Conference and Exposition, APEC 2004, 2004, pp. 383–391.
[E13] D. Trevisan, P. Mattavelli, and P. Tenti, “Digital control of single-inductor multiple-
output step-down DC–DC converters in CCM,” IEEE Transactions on Industrial
Electronics, Vol. 55, No. 9, pp. 3476-3483, 2008.
[E14] C. E. Carrejo, E. Vidal-Idiarte, R. Giral, and L. Martinez-Salamero, “Predictive digital
interpolation current control for DC-DC power converters,” IET Power Electronics, Vol.
2, No. 5, pp. 545-554, 2009.
[E15] W. Y. Wang, H. H. C. Iu, W. Du, and V. Sreeram, “Multiphase dc-dc converter with
high dynamic performance and high efficiency,” IET Power Electronics, Vol. 4, No. 1,
pp. 101-110, 2011.
[E16] Guang Feng, E. Meyer, and Yan-Fei Liu, “A new digital control algorithm to achieve
optimal dynamic performance in DC-to-DC converters,” IEEE Transactions on Power
Electronics, Vol. 22, No. 4, pp. 1489-1498, 2007.
[E17] Kaiwei Yao, Yuancheng Ren, and Lee F.C. “Critical bandwidth for the load transient
response of voltage regulator modules,” IEEE Transactions on Power Electronics, Vol.
19, No. 6, pp. 1454-1461, 2004.
[E18] Yu-Huei Lee, Shih-Jung Wang, Chun-Yu Hsieh, and Ke-Horng Chen, “Current mode
DC-DC buck converters with optimal fast-transient control,” IEEE International
Symposium on Circuits and Systems, 2008, pp. 3045 – 3048.
[E19] A. H. Bhat, and P. Agarwal, “DSP-based implementation of capacitor voltage balancing
strategy for a three-phase three-level bidirectional rectifier,” IET Power Electronics, Vol.
2, No. 4, pp. 375-386, 2009.
[E20] A. Yazdani, and R. Iravani, “Control of high-performance switched-mode rectifier
system,” IET Power Electronics, Vol. 152, No. 6, pp. 1451 - 1458, 2005.
[E21] A. E. Leon, J. A. Solsona, and M. I. Valla, “Exponentially convergent estimator to
improve performance of voltage source converters,” IET Power Electronics, Vol. 3, No.
5, pp. 668-680, 2010.
[E22] A. Khaligh, P. Chapman, and S. S. Raghavan, “Control of voltage regulator modules
using anticipated load transients,” IET Power Electronics , Vol. 4 , No. 6, pp. 651 – 656,
2011.
128
[E23] O. Abdel-Rahman, and I. Batarseh, “Dynamic PWM Ramp Signal to Improve Load
Transient in DCM and Mode Hoping Operation,” IEEE Power Electronics Specialists
Conference, 2007, pp. 2016 – 2022.
[E24] V. Yousefzadeh, and S. Choudhury, “Nonlinear digital PID controller for DC-DC
converters,” Twenty-Third Annual IEEE Applied Power Electronics Conference and
Exposition, 2008, pp. 1704 – 1709.
[E25] V. Arikatla, and J. A. Abu Qahouq, “An Adaptive Digital PID controller Scheme for
Power Convrters,” IEEE Energy Conversion Congress and Exposition, 2010, pp. 223-
227.
[E26] Liping Guo, J. Y. Hung, and R. M. Nelms “PID controller modifications to improve
steady-state performance of digital controllers for buck and boost converters,”
Seventeenth Annual IEEE Applied Power Electronics Conference and Exposition, 2002,
pp. 381-388.
[E27] Weihong Qiu, Greg Miller, and Zhixiang Liang, “Dual-Edge Pulse Width Modulation
Scheme for Fast Transient Response of Multiple-Phase Voltage Regulators,” IEEE Power
Electronics Specialists Conference, 2007, pp. 1563 – 1569.
[E28] Yanxia Gao, Shuibao Guo, Yanping Xu, Shi Xuefang Lin, and B. Allard, “FPGA-based
DPWM for digitally controlled high-frequency DC-DC SMPS,” 3rd International
Conference on Power Electronics Systems and Applications, 2009, pp. 1 - 7.
[E29] Shuibao Guo, Yanxia Gao, Yanping Xu, Xuefang Lin-Shi, and B. Allard, “Digital PWM
controller for high-frequency low-power DC-DC switching mode power supply,” IEEE
6th International Power Electronics and Motion Control Conference, 2009, pp. 1340 -
1346.
[E30] J. A. Abu Qahouq, V. Arikatla, and Thanukamalam Arunachalam, “Modified Digital
Pulse Width Modulator for Power Converters with Reduced Modulation Delay,” Journal
of Power Electronics, Accepted in October 2011 for Publication.
[E31] V. Arikatla, and J. A. Abu Qahouq, “An Adaptive Digital PID controller scheme for
power converters,” IET Power Electronics, Accepted in October 2011 for Publication.
CHAPTER 6
[F1] J. A. Abu Qahouq, and V. Arikatla, “Power Converter With Digital Sensorless Adaptive
Voltage Positioning Control Scheme,” IEEE Transactions on Industrial Electronics, Vol.
58 , No. 9, pp. 4105 – 4116, 2011.
[F2] V. Arikatla, and J. A. Abu Qahouq, “An Adaptive Digital PID controller scheme for
power converters,” IEEE Energy Conversion Congress and Exposition (ECCE), 2010,
pp. 223 - 227.
129
[F3] V. Arikatla, and J. A. A. Qahouq, “DC-DC Power Converter with digital PID controller,”
Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition
(APEC), 2011, pp. 327 – 330.
[F4] V. Arikatla, and J.A.A. Qahouq, “Dynamic digital variable switching frequency control
scheme for power converters,” Twenty-Sixth Annual IEEE Applied Power Electronics
Conference and Exposition (APEC), 2011, pp. 253 – 257.
[F5] V. Arikatla, and J.A.A. Qahouq, “Dynamic Response Improvement of Power Converter
Using an Adaptive Frequency Control Law,” IEEE Energy Conversion Congress and
Exposition (ECCE), 2011.
[F6] V. Arikatla, and J. A. Abu Qahouq, “An Adaptive Digital PID controller scheme for
power converters,” IET Power Electronics, Accepted in October 2011 for Publication.