REV. B

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

a 500 mA Differential Driver andDual Low Noise (VF) Amplifiers

AD816*FEATURES

Flexible Configuration

Two Low Noise Voltage Feedback Amplifiers with

High Current Drive, Ideal for ADSL Receivers or

Drivers for Low Impedance Loads such as CRT Coils

Two High Current Drive Amplifiers, Ideal for an ADSL

Differential Driver or Single Ended Drivers for Low

Impedance Loads such as CRT Coils

Thermal Overload Protection

CURRENT FEEDBACK AMPLIFIERS/DRIVERS

High Output Drive

26 dBm Differential Line Drive for ADSL Transmitters

40 V p-p Differential Output Voltage, RL = 50 V @ 1 MHz

500 mA Continuous Current, RL = 5 V1 A Peak Current, 1% Duty Cycle, RL = 15 V for DMT

Low Distortion

–68 dB @ 1 MHz THD, RL = 100 V, VO = 40 V p-p

High Speed

120 MHz Bandwidth (–3 dB)

1500 V/ms Differential Slew Rate, VO = 10 V p-p, G = +5

70 ns Settling Time to 0.1%

VOLTAGE FEEDBACK AMPLIFIERS/RECEIVERS

High Input Performance

4 nV/√Hz Voltage Noise

15 mV Max Input Offset Voltage

Low Distortion

–68 dB @ 1 MHz THD, VO = 10 V p-p, RL = 200 VHigh Speed

100 MHz Bandwidth (–3 dB)

180 V/ms Slew Rate

High Output Drive

70 mA Output Current Drive

APPLICATIONS

ADSL, VDSL and HDSL Line Interface Driver and Receiver

CRT Convergence and Astigmatism Adjustment

Coil and Transformer Drivers

Composite Audio Amplifiers

FUNCTIONAL BLOCK DIAGRAM

OUT1 RECEIVER

–IN1 RECEIVER

+IN1 RECEIVER

+IN1 DRIVER

–IN1 DRIVER

OUT1 DRIVER

–VS

+VS

OUT2 RECEIVER

–IN2 DRIVER

+IN2 DRIVER

+IN2 RECEIVER

–IN2 RECEIVER

NC

TAB IS+VS

NC = NO CONNECT

OUT2 DRIVER

RE

CE

IVE

R A

RE

CE

IVE

R B

AD

816

–VS

+VS

DR

IVE

R A

& B

B

A

15

141312

11

10

987

6

5

4

3

2

1

PRODUCT DESCRIPTIONThe AD816 consists of two high current drive and two lownoise amplifiers. These can be configured differentially for driv-ing low impedance loads and receiving signals over twisted paircable or could be used independently for single ended drivingapplication such as correction circuits within high resolutionCRT Monitors.

The two high output drive amplifiers are capable of supplyinga minimum of 500 mA continuous output current and up to1A peak output current, and when configured differentially,40 V p-p differential output swing can be achieved on ±15 Vsupplies into a load of 50 Ω. The drivers have 120 MHz ofbandwidth and 1,500 V/µs of differential slew rate whilefeaturing total harmonic distortion of –68 dB at 1 MHz into a100 Ω load, specifications required for high frequency telecom-munication subscriber line drivers.

The low noise voltage feedback amplifiers are fully independentand can be configured differentially for use as receiver amplifi-ers within a subscriber line hybrid interface or individually forsignal conditioning or filtering. The low noise of 4 nV/√Hz anddistortion of –68 dB at 1 MHz enable low level signals to beresolved and amplified in the presence of large common-modevoltages. 100 MHz of bandwidth and 180 V/µs of slew ratecombined with a load drive capability of 70 mA enable theseamplifiers to drive passive filters and low inductance coils. TheAD816 has thermal overload protection for system reliabilityand is available in low thermal resistance power packages. TheAD816 operates over the industrial temperature range (–40°Cto +85°C).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1999

OBSOLETE

AD816–SPECIFICATIONSDRIVER AMPLIFIERS

AD816AModel Conditions VS Min Typ Max UnitsDYNAMIC PERFORMANCE

Small Signal Bandwidth (–3 dB) G = +2, RF = 499 Ω, VIN = 0.125 V rms,RL = 100 Ω ±15 100 120 MHzG = +2, RF = 499 Ω, VIN = 0.125 V rms,RL = 100 Ω ± 5 90 110 MHz

Bandwidth (0.1 dB) G = +2, RF = 499 Ω, VIN = 0.125 V rms,RL = 100 Ω ±15 10 MHz

Differential Slew Rate VOUT = 10 V p-p, G = +5, RL = 100 Ω ±15 1400 1500 V/µsSettling Time to 0.1% 10 V Step, G = +2 ±15 70 ns

NOISE/HARMONIC PERFORMANCETotal Harmonic Distortion (Differential) f = 1 MHz, RLOAD = 100 Ω, VOUT = 40 V p-p ±15 –68 dBcInput Voltage Noise f = 10 kHz, G = +2 (Single Ended) ±5, ±15 1.85 nV/√HzInput Current Noise (+IIN) f = 10 kHz, G = +2 ±5, ±15 1.8 pA/√HzInput Current Noise (–IIN) f = 10 kHz, G = +2 ±5, ±15 19 pA/√HzDifferential Gain Error NTSC, G = +2, RLOAD = 25 Ω ±15 0.05 %Differential Phase Error NTSC, G = +2, RLOAD = 25 Ω ±15 0.45 Degrees

DC PERFORMANCEInput Offset Voltage ± 5 5 12 mV

±15 10 15 mVTMIN to TMAX 25 mV

Input Offset Voltage Drift 40 µV/°CDifferential Offset Voltage ±5, ±15 0.5 2 mV

TMIN to TMAX 5 mVDifferential Offset Voltage Drift 5 µV/°C–Input Bias Current ±5, ±15 20 60 µA

TMIN to TMAX 100 µA+Input Bias Current ±5, ±15 2 5 µA

TMIN to TMAX 5 µADifferential Input Bias Current ±5, ±15 10 50 µA

TMIN to TMAX 50 µAOpen-Loop Transresistance VOUT = ±10 V, RL = 1 kΩ ±5, ±15 0.7 2 MΩ

TMIN to TMAX 0.6 MΩINPUT CHARACTERISTICS

Differential Input Resistance +Input ±15 7 MΩ–Input 15 Ω

Differential Input Capacitance ±15 1.4 pFInput Common-Mode Voltage Range ±15 13.5 ± V

± 5 3.5 ± VCommon-Mode Rejection Ratio TMIN to TMAX ±5, ±15 56 60 dBDifferential Common-Mode Rejection Ratio TMIN to TMAX ±5, ±15 80 100 dB

OUTPUT CHARACTERISTICSVoltage Swing Single Ended, RLOAD = 25 Ω ±15 23 24.5 V p-p

± 5 2.2 3.6 V p-pDifferential, RLOAD = 50 Ω ±15 46 49 V p-pTMIN to TMAX ±15 45 V p-p

Continuous Output Current RLOAD = 5 Ω ±15 500 750 mA± 5 200 100 mA

Peak Output Current 10 µs Pulse, 1% Duty Cycle, RL = 15 Ω ±15 1.0 AShort Circuit Current Note 1 ±15 1.0 A

NOTES1See Power Considerations section.

Specifications subject to change without notice.

REV. B–2–

(@ TA = +258C, VS = 615 V dc, RF = 1 kV and RLOAD = 50 V unless otherwise noted)

OBSOLETE

RECEIVER AMPLIFIERS AD816A

Model Conditions VS Min Typ Max UnitsDYNAMIC PERFORMANCE

Small Signal Bandwidth (–3 dB) G = +2, RL = 100 Ω ±15 100 MHzG = +2, RL = 100 Ω ±5 80 MHz

Bandwidth (0.1 dB) G = +2 ±15 30 MHzG = +2 ±5 40 MHz

Slew Rate VOUT = 4 V p-p ±15 180 V/µsSettling Time to 0.1% VOUT = 10 V p-p Step, G = +2 ±15 45 ns

NOISE/HARMONIC PERFORMANCETotal Harmonic Distortion f = 1 MHz, RLOAD = 200 Ω ±15 –68 dBcInput Voltage Noise f = 10 kHz ±5, ± 15 4 nV/√HzCurrent Noise f = 10 kHz ±5, ± 15 2 pA/√HzDifferential Gain Error NTSC, G = +2, RLOAD = 150 Ω ±15 0.04 0.08 %

±5 0.05 0.1 %Differential Phase Error NTSC, G = +2, RLOAD = 150 Ω ±15 0.03 0.1 Degrees

±5 0.06 0.1 DegreesDC PERFORMANCE

Input Offset Voltage ±5, ± 15 7.5 15 mVTMIN to TMAX 15 mV

Offset Voltage Drift 20 µV/°CInput Bias Current ±5, ± 15 5 7 µA

TMIN to TMAX 15 µAInput Offset Current ±5, ± 15 0.5 2 µAOffset Current Drift 1 nA/°COpen-Loop Gain VOUT = ±7.5 V, RLOAD = 150 Ω ±15 3 6 V/mV

TMIN to TMAX ±15 1 V/mVINPUT CHARACTERISTICS

Input Resistance 300 kΩInput Capacitance 1.5 pFInput Common-Mode Voltage Range ±15 +13 +14.3 V

±15 –12 –13.4 V±5 +3.8 +4.3 V±5 –2.7 –3.4 V

Common-Mode Rejection Ratio VCM = ±5 V ±15 82 110 dBOUTPUT CHARACTERISTICS

Output Voltage Swing Single Ended, RLOAD = 150 Ω ±15 25.2 25.5 V p-pTMIN to TMAX ±15 25.2 V p-pSingle Ended, RLOAD = 150 Ω ±5 6.2 6.4 V p-pTMIN to TMAX ±5 6.0 V p-p

Output Current RL = 150 Ω ±15 65 70 mAShort Circuit Current ±15 105 mA

Specifications subject to change without notice.

(@ TA = +258C, VS = 615 V dc, RF = 1 kV and RLOAD = 500 V unless otherwise noted)

REV. B –3–

COMMON CHARACTERISTICSAD816A

Model Conditions VS Min Typ Max Units

MATCHING CHARACTERISTICSCrosstalk:

Driver to Driver f = 1 MHz, VIN = 200 mV rms, RLOAD = 100 Ω ±15 –67 dBDrivers to Receivers f = 1 MHz, VIN = 200 mV rms, RLOAD = 100 Ω ±15 –64 dBReceiver to Receiver f = 1 MHz, VIN = 200 mV rms, RLOAD = 500 Ω ±15 –81 dB

POWER SUPPLYOperating Range ±5 ±18 VQuiescent Current ±15 46 56 mA

TMIN to TMAX ±15 59 mADriver Supply Rejection Ratio TMIN to TMAX ±15, ±5 –49 –66 dBReceiver Supply Rejection Ratio TMIN to TMAX ±15, ±5 –69 –75 dB

Specifications subject to change without notice.

(@ TA = +258C, VS = 615 V dc, RF = 1 kV and RLOAD = 50 V (Driver), RLOAD = 500 V (Receiver)unless otherwise noted)

AD816

OBSOLETE

AD816

REV. B–4–

MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by theAD816 is limited by the associated rise in junction temperature.The maximum safe junction temperature for the plastic encap-sulated parts is determined by the glass transition temperatureof the plastic, about 150°C. Exceeding this limit temporarilymay cause a shift in parametric performance due to a change inthe stresses exerted on the die by the package. Exceeding ajunction temperature of 175°C for an extended period can resultin device failure.

The AD816 has thermal shutdown protection, which guaranteesthat the maximum junction temperature of the die remains below asafe level. However, shorting the output to ground or either powersupply for an indeterminate period will result in device failure.To ensure proper operation, it is important to observe the derat-ing curves and refer to the section on power considerations.

It must also be noted that in high (noninverting) gain configura-tions (with low values of gain resistor), a high level of inputoverdrive can result in a large input error current, which mayresult in a significant power dissipation in the input stage. Thispower must be included when computing the junction tempera-ture rise due to total internal power.

AMBIENT TEMPERATURE – 8C

14

7

4

–50 90–40

MA

XIM

UM

PO

WE

R D

ISS

IPA

TIO

N –

Wat

ts

–30 –20 –10 10 20 30 40 50 60 70 80

13

8

6

5

11

9

12

10

0

TJ = 1508C

3

2

1

0

AD816 AVR, AY

θJA = 418C/W (STILL AIR = 0FT/MIN) NO HEAT SINK

θJA = 168C/W SOLDERED DOWN TO COPPER HEAT SINK AREA (STILL AIR = 0FT/MIN)

AD816 AVR, AY

Figure 1. Plot of Maximum Power Dissipation vs. Tem-perature (Copper Heat Sink Area = 2 in.2)

ABSOLUTE MAXIMUM RATINGS1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V TotalInternal Power Dissipation2

Plastic (Y, YS and VR) . . 3.05 W (Observe Derating Curves)Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 VOutput Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating CurvesStorage Temperature Range

Y, YS, VR Package . . . . . . . . . . . . . . . . . . –65°C to +125°COperating Temperature Range

AD816A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°CLead Temperature Range (Soldering, 10 sec) . . . . . . . +300°CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only. functional operation of thedevice at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.

2Specification is for device in free air: 15-Lead Through Hole and Surface Mount:θJA = 41°C/W.

PIN CONFIGURATION

Y-15 VR-15, YS-15

TOP VIEW

10 12 13 14 15111 2 3 4 5 6 7 8 9

OU

T1

RE

CE

IVE

R–I

N1

RE

CE

IVE

R+I

N1

RE

CE

IVE

R+I

N1

DR

IVE

R–I

N1

DR

IVE

RO

UT

1 D

RIV

ER

–VS

+VS

OU

T2

RE

CE

IVE

R

–IN

2 D

RIV

ER

+IN

2 D

RIV

ER

+IN

2 R

EC

EIV

ER

–IN

2 R

EC

EIV

ER

NC

OU

T2

DR

IVE

R

OU

T1

RE

CE

IVE

R–I

N1

RE

CE

IVE

R+I

N1

RE

CE

IVE

R+I

N1

DR

IVE

R–I

N1

DR

IVE

RO

UT

1 D

RIV

ER

–VS

+VS

OU

T2

RE

CE

IVE

R

–IN

2 D

RIV

ER

+IN

2 D

RIV

ER

+IN

2 R

EC

EIV

ER

–IN

2 R

EC

EIV

ER

NC

OU

T2

DR

IVE

R

TOP VIEW

10 12 13 14 15111 2 3 4 5 6 7 8 9

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD816 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

PackageModel Temperature Range Package Description Option

AD816AY –40°C to +85°C 15-Lead Through-Hole SIP with Staggered Leads and 90° Lead Form Y-15AD816AYS –40°C to +85°C 15-Lead Through-Hole SIP with Staggered Leads and Straight Lead Form YS-15AD816AVR –40°C to +85°C 15-Lead Surface Mount DDPAK VR-15

WARNING!

ESD SENSITIVE DEVICE

OBSOLETE

LOAD RESISTANCE – (Differential – V) (Single-Ended – V/2 )

30

25

010 10k100 1k

20

15

10

5

DIF

FER

EN

TIA

L O

UTP

UT

VO

LTA

GE

– V

olts

p-p

60

50

0

40

30

20

10

VS = 615V

VS = 65V

SIN

GLE

-EN

DE

D O

UTP

UT

VO

LTA

GE

– V

olts

p-p

Figure 2. Driver Output Voltage Swing vs. Load Resistance

FREQUENCY – Hz

100

10

110 100k100 1k 10k

VO

LTA

GE

NO

ISE

– n

V/

Hz

100

10

1

CU

RR

EN

T N

OIS

E –

pA

/ H

z

INVERTING INPUT CURRENT NOISE

NONINVERTING INPUT CURRENT NOISE

INPUT VOLTAGE NOISE

Figure 3. Driver Input Current and Voltage Noise vs.Frequency

FREQUENCY – MHz0.01

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–1000.1

PS

RR

– d

B

1 10 100 300

+PSRR

–PSRR

VS = 615V G = +2 RL = 100V

Figure 4. Driver Power Supply Rejection vs. Frequency

–5–REV. B

Typical Driver Performance Characteristics–AD816

JUNCTION TEMPERATURE – 8C–40 100–20 0 20 40 60 80

60

0

40

30

20

10

50

INP

UT

BIA

S C

UR

RE

NT

– m

A

–IB, VS = 615V

–IB, VS = 65V

+IB, VS = 65V, 615V

Figure 5. Driver Input Bias Current vs. Temperature

FREQUENCY – Hz

–40

–50

–110100 10M1k

TOTA

L H

AR

MO

NIC

DIS

TOR

TIO

N –

dB

c

10k 100k 1M

–60

–70

–80

–90

–100

VS = 615V G = +10 VOUT = 40V p-p

RL = 50V

(DIFFERENTIAL)

RL = 200V

(DIFFERENTIAL)

50V

100V

400V

Figure 6. Driver Total Harmonic Distortion vs. Frequency

FREQUENCY – Hz

80

1010k 100M100k

CO

MM

ON

-MO

DE

RE

JEC

TIO

N –

dB

1M 10M

70

60

50

40

30

20

VS = 615V

1kV

VOUTVIN

1kV

1kV

1kV

Figure 7. Driver Common-Mode Rejection vs. Frequency

OBSOLETE

OUTPUT STEP SIZE – V p-p

0

1400

1000

800

600

400

0 5 10 15 20

SIN

GLE

-EN

DE

D S

LEW

RA

TE –

V/m

s(P

ER

AM

PL

IFIE

R)

G = +5 RL = 100V –SR

200

+SR

DIFFERENTIAL SR

1200

0

2800

2000

1600

1200

800

400

2400

DIF

FER

EN

TIA

L S

LEW

RA

TE –

V/m

s

Figure 8. Driver Slew Rate vs. Output Step Size

VOUT – Volts

15

0

–15–20 20–16 –12 –8 –4 0 4 8 12 16

10

5

–5

–10

VS = 610V

VS = 65V

RT

I OF

FS

ET

– m

V

VS = 615V

TA = +258C

1kV 1kV

RL =25V

VOUT100V

49.9V

VI Nf = 0.1Hz

SINGLEDRIVER

Figure 9. Driver Gain Nonlinearity vs. Output Voltage

10

0%

100

90

1ms5V

Figure 10. Driver 40 V p-p Differential Sine Wave; RL = 50 Ω,f = 100 kHz

AD816–Typical Driver Performance Characteristics

–6– REV. B

LOAD CURRENT – Amps

80

0

–60

40

20

–20

–40

60

–2.0 2.0–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6

VS = 610V

VS = 65V

RT

I OF

FS

ET

– m

V VS = 615V

TA = +258C

1kV 1kV

RL =5V

VOUT100V

49.9V

VI Nf = 0.1Hz

SINGLEDRIVER

Figure 11. Driver Thermal Nonlinearity vs. Output CurrentDrive

FREQUENCY – MHz

40

00 146

DIF

FER

EN

TIA

L O

UTP

UT

VO

LTA

GE

– V

p-p

10

30

20

10

RL = 50V

RL = 25V

RL = 1V

2 4 8 12

RL = 100V

TA = +258C VS = 615V

Figure 12. Driver Large Signal Frequency Response

FREQUENCY – Hz

100

30k 300M100k

CLO

SE

D-L

OO

P O

UTP

UT

RE

SIS

TAN

CE

– V

1M 10M 100M

10

1

0.1

0.01

300k 3M 30M

VS = 65V

VS = 615V

Figure 13. Driver Closed-Loop Output Resistance vs.Frequency

OBSOLETE

AD816

REV. B –7–

Typical Driver Characteristics–

FREQUENCY – Hz100k

INP

UT

LEV

EL

– dB

V

OU

TPU

T LE

VE

L –

dBV

300M1M 10M 100M

–12

–15

–18

–21

–24

–27

3

0

–3

–6

–9

–12

–15

–18

6

–21

–9

–6

–3

0

VIN = 0.5Vrms

VIN = 0.25Vrms

VIN = 125mVrms

VIN = 62.5mVrms

G = +2RF = 499V

RL = 100V

RS = 100V

Figure 17. Driver Small and Large Signal FrequencyResponse, G = +2

FREQUENCY – Hz100k 300M1M

NO

RM

ALI

ZED

FLA

TNE

SS

– d

B

10M 100M

0.1

0

–0.1

–0.2

–0.3

–0.4

VIN = 50mVrms G +5 RL = 100V

RS = 100V

0

–1

–2

–3

–4

–5

–6

–7

1

2

–8

NO

RM

ALI

ZED

FR

EQ

UE

NC

Y R

ES

PO

NS

E –

dB

RF = 499V

RF = 604V

RF = 750V

RF = 604V

RF = 750V

Figure 18. Driver Frequency Response and Flatness,G = +5

FREQUENCY – Hz100k 300M1M 10M 100M

VIN = 200mVrms G +2 RL = 100V

RS = 100V

0

–1

–2

–3

–4

–5

–6

–7

1

2

3

RF = 499V

RF = 750V

RF = 604V

NO

RM

ALI

ZED

FR

EQ

UE

NC

Y R

ES

PO

NS

E –

dB

Figure 19. Driver Frequency Response vs. RF, G = +2

0.040.030.020.010.00

–0.01–0.02–0.03–0.04

DIF

F G

AIN

– %

0.120.100.080.060.040.020.00–0.02–0.04

DIF

F P

HA

SE

– D

eg

rees

G = +2 RF = 1kV

NTSC

1 2 3 4 5 6 7 8 9 10 11

0.50.40.30.20.10.0–0.1–0.2–0.3

GAIN

PHASE

0.0050.000

–0.005–0.010–0.015–0.020–0.025–0.030

0.010

DIF

F G

AIN

– %

DIF

F P

HA

SE

– D

egre

es

1 2 3 4 5 6 7 8 9 10 11

6 BACK TERMINATED LOADS (25 V)

2 BACK TERMINATED LOADS (75 V)

G = +2 RF = 1kV

NTSC GAIN

PHASE

Figure 14. Driver Differential Gain and DifferentialPhase (Per Amplifier)

FREQUENCY – Hz10k 100k 1M 10M 100M 300M

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

CR

OS

STA

LK –

dB

DRIVER B = INPUTDRIVER A = OUTPUT

–100

DRIVER A = INPUTDRIVER B = OUTPUT

VIN = 200mVrms

499V

100V

100V

50V

OUTPUTINPUT

499V

DRIVERA

499V

100V

100V

50V

OUTPUT INPUT

499V

DRIVERB

Figure 15. Driver Output-to-Output Crosstalk vs.Frequency

FREQUENCY – Hz100k 1M 10M 100M 300M

3

0

–3

–6

–9

–12

–15

–18

–21

–24

OU

TPU

T/IN

PU

T LE

VE

L –

dBV

–27

VIN = 1.0Vrms

VIN = 0.5Vrms

VIN = 0.25Vrms

VIN = 125mVrms

VIN = 62.5mVrms

G = +1RF = 499V

RL = 100V

RS = 100V

Figure 16. Driver Small and Large Signal FrequencyResponse, G = +1

OBSOLETE

AD816–Typical Driver Performance Characteristics

–8– REV. B

AD816DRIVER A/B

8

0.1mF

10mF+15V

0.1mF

10mF

7

–15V

RL = 100V100V

55V

VIN

PULSEGENERATOR

TR/TF = 250ps

1kV

1kV

Figure 20. Test Circuit Gain = –1

Figure 21. Driver 500 mV Step Response, G = –1

Figure 22. Driver 4 V Step Response, G = –1

8

0.1mF

10mF+15V

0.1mF

10mF

7

–15V

RL = 100V100V

50V

VIN

PULSEGENERATOR

TR/TF = 250ps

RG

RF

AD816DRIVER A/B

Figure 23. Test Circuit, Gain = 1 + RF/RG

0.1mF

10mF+15V

499V

0.1mF

10mF

7

–15V

RL = 100V100V

50V

VIN

PULSEGENERATOR

TR/TF = 500ps

8

AD816DRIVER A/B

499V

Figure 24. Driver Test Circuit, Gain = +2

Figure 25. 10 V Step Response, G = +2

Figure 26. Driver 400 mV Step Response, G = +2

Figure 27. Driver 20 V Step Response, G = +5

OBSOLETE

Typical Receiver Performance Characteristics–AD816

REV. B –9–

FREQUENCY – Hz

50

40

03 10M10 100 1k 10k 100k 1M

30

20

10

INP

UT

VO

LTA

GE

NO

ISE

– n

V/

Hz

Figure 28. Receiver Input Voltage Noise Spectral Density

FREQUENCY – Hz100k 300M1M 10M 100M

1

0

–1

–2

–3

–4

–5

2

3

4

5

GA

IN –

dB

100V

1kV

50V

VOUT

VIN

1kV

VS = 65V

VS = 615V

Figure 29. Receiver Closed-Loop Gain vs. Frequency,Gain = –1

FREQUENCY – Hz

100

80

01k 10M10k

CM

R –

dB

100k 1M

60

40

1kV

1kV

VOUTVIN

1kV

1kV

Figure 30. Receiver Common-Mode Rejection vs.Frequency

FREQUENCY – Hz

–40

–50

–100100 10M1k

HA

RM

ON

IC D

ISTO

RTI

ON

– d

B

10k 100k 1M

–60

–70

–80

–90

G = +5VOUT = 14V p-p RF = 4kV

RL = 1kV

Figure 31. Receiver Harmonic Distortion vs. Frequency

FREQUENCY – Hz100k 300M1M

INP

UT

LEV

EL

– dB

V

10M 100M

G = +2 RF = 1kV

CF = 2.2pF RL = 100V

RS = 0V

3

0

–3

–6

–9

–12

–15

–18

6

9

–21

OU

TPU

T LE

VE

L (R

TO) –

dB

V

–3

–6

–9

–12

–15

–18

–21

–24

0

3

–27

VIN = 0.5Vrms

VIN = 1.0Vrms

VIN = 0.25Vrms

VIN = 0.0625Vrms

VIN = 0.125Vrms

Figure 32. Receiver Small and Large Signal FrequencyResponse, Gain = +2

FREQUENCY – Hz100 1k 10k 100k 1M 10M 100M

100

90

10

50

40

30

20

70

60

80

PS

R –

dB POSITIVE

SUPPLY

NEGATIVESUPPLY

Figure 33. Receiver Power Supply Rejection vs. Frequency

OBSOLETE

REV. B

AD816–Typical Receiver Performance Characteristics

AD816REC A/B

8

0.1mF

10mF+15V

10mF7

–15V

RL

50V

VIN

PULSEGENERATOR

TR/TF = 500ps

1kV

1kV

0.1mF

2.2pF

VOUT

Figure 34. Test Circuit, Gain = +2

Figure 35. Receiver 10 V Step Response, G = +2

Figure 36. Receiver 400 mV Step Response, G = +2

FREQUENCY – MHz0.1 300

CR

OS

STA

LK –

dB

1 10 100

–40

–50

–60

–70

–80

–90

–100

–30

–20

–10

0

0.01

RECEIVER A = INPUT RECEIVER B = OUTPUT

RECEIVER B : INPUT RECEIVER A : OUTPUT

VIN = 200mVrms

1kV 100V

50V

OUTPUTINPUT

1kV

REC A

2.2pF

1kV100V

50V

OUTPUT INPUT

1kV

REC B

2.2pF

Figure 37. Receiver Output-to-Output Crosstalkvs. Frequency

–10–

AD816REC A/B

8

0.1mF

10mF+15V

10mF7

–15V

RL = 500V

50V

VIN

PULSEGENERATOR

TR/TF = 250ps

1kV

1kV

0.1mFVOUT

Figure 38. Test Circuit, Gain = –1

5V

50ns

Figure 39. Receiver 10 V Step Response, G = –1

50ns

Figure 40. Receiver 400 mV Step Response, G = –1

FREQUENCY – MHz0.1 3001 10 100

–40

–50

–60

–70

–80

–90

–100

–30

–20

–10

0

CR

OS

STA

LK –

dB

0.01

DRIVER A: INPUTRECEIVER B: OUTPUT

VIN = 200mVrms

DRIVER B: INPUT RECEIVER A: OUTPUT

DRIVER A: INPUTRECEIVER A: OUTPUT

DRIVER B: INPUT RECEIVER A: OUTPUT

499V

100V50V

INPUT

499V

DRV A100V

OUTPUT

1kV100V50V

OUTPUTINPUT

1kV2.2pF

REC A

499V

100V50V

OUTPUT

INPUT

499V

DRV B

100V

1kV

100V 50V

OUTPUT

INPUT

1kV

REC B

2.2pF

Figure 41. Driver-to-Receiver Crosstalk vs. Frequency

OBSOLETE

AD816

REV. B –11–

Table I. Driver Resistor Values

RF (V) RG (V)

G = +1 604 ∞–1 499 499+2 499 499+5 499 125+10 1k 110

DRIVER DC ERRORS AND NOISEThere are three major noise and offset terms to consider in acurrent feedback amplifier. For offset errors refer to the equa-tion below. For noise error the terms are root-sum-squared togive a net output error. In the circuit below (Figure 43), theyare input offset (VIO) which appears at the output multiplied bythe noise gain of the circuit (1 + RF/RG), noninverting inputcurrent (IBN × RN) also multiplied by the noise gain, and theinverting input current, which when divided between RF and RG

and subsequently multiplied by the noise gain always appear atthe output as IBI × RF. The input voltage noise of the AD816 isless than 4 nV/√Hz. At low gains, however, the inverting inputcurrent noise times RF is the dominant noise source. Carefullayout and device matching contribute to better offset and drift.The typical performance curves in conjunction with the equationsbelow can be used to predict the performance of the AD816 inany application.

VOUT =VIO 1+

RF

RG

± IBN RN 1+RF

RG

± IBI RF

IBI

IBN

RG

RN

RF

VOUTVIO AD816DRIVERS

Figure 43. Driver Output Offset Voltage

THEORY OF OPERATION (RECEIVER)Each AD816 receiver is a wide band high performance opera-tional amplifier. It also provides a constant slew rate, bandwidthand settling time over its entire specified temperature range.

The AD816 receiver consists of a degenerated NPN differentialpair driving matched PNPs in a folded-cascode gain stage. Theoutput buffer stage employs emitter followers in a class ABamplifier which deliver the necessary current to the load whilemaintaining low levels of distortion.

A protection resistor in series with the noninverting input isrequired in circuits where the input to the receiver could besubject to transients on continuous overload voltages exceedingthe ±6 V maximum differential limit. The resistor providesprotection for the input transistors, by limiting their maximumbase current.

THEORY OF OPERATION (DRIVER)The AD816 driver is a dual current feedback amplifier with high(500 mA) output current capability. Being a current feedbackamplifier, the AD816 driver’s open-loop behavior is expressedas transimpedance, ∆VO/∆I–IN, or TZ. The open-loop trans-impedance behaves just as the open-loop voltage gain of a volt-age feedback amplifier, that is, it has a large dc value and de-creases at roughly 6 dB/octave in frequency.

Since RIN is proportional to 1/gM, the equivalent voltage gain isjust TZ × gM, where the gM in question is the transconductanceof the input stage. Figure 42 shows the driver connected as afollower with gain. Basic analysis yields the following results:

VO

VIN

= G ×TZ S( )

TZ S( ) + G × RIN + RF

where:

G = 1+ RF

RG

RIN = 1/gM ≈ 25 Ω

RIN

VIN

RF

VOUT

RG

RN

Figure 42. Current-Feedback Amplifier Operation

Recognizing that G × RIN << RF for low gains, it can be seen tothe first order that bandwidth for this amplifier is independentof gain (G).

Considering that additional poles contribute excess phase athigh frequencies, there is a minimum feedback resistance belowwhich peaking or oscillation may result. This fact is used todetermine the optimum feedback resistance, RF. In practiceparasitic capacitance at the inverting input terminal will also addphase in the feedback loop so that picking an optimum value forRF can be difficult.

Achieving and maintaining gain flatness of better than 0.1 dB atfrequencies above 10 MHz requires careful consideration ofseveral issues.

Choice of Feedback and Gain ResistorsThe fine scale gain flatness will, to some extent, vary withfeedback resistance. It is therefore recommended that onceoptimum resistor values have been determined, 1% tolerancevalues should be used if it is desired to maintain flatness over awide range of production lots. Table I shows optimum valuesfor several useful gain configurations. These should be used as astarting point in any application.

OBSOLETE

AD816

REV. B–12–

PRINTED CIRCUIT BOARD LAYOUTCONSIDERATIONSAs to be expected for a wideband amplifier, PC board parasiticscan affect the overall closed-loop performance. Of concern arestray capacitances at the output and the inverting input nodes. Ifa ground plane is to be used on the same side of the board asthe signal traces, a space (5 mm min) should be left around thesignal lines to minimize coupling.

POWER SUPPLY BYPASSINGAdequate power supply bypassing can be critical when optimiz-ing the performance of a high frequency circuit. Inductance inthe power supply leads can form resonant circuits that producepeaking in the amplifier’s response. In addition, if large currenttransients must be delivered to the load, then bypass capacitors(typically greater than 1 µF) will be required to provide the bestsettling time and lowest distortion. A parallel combination of10.0 µF and 0.1 µF is recommended. Under some low frequencyapplications, a bypass capacitance of greater than 10 µF may benecessary. Due to the large load currents delivered by the AD816,special consideration must be given to careful bypassing. Theground returns on both supply bypass capacitors as well as signalcommon must be “star” connected as shown in Figure 44.

RF

RG(OPTIONAL) RF

+VS

+OUT

–OUT

–VS

+IN

–IN

DRIVER A

DRIVER B

RF RG

RF

RG

IN

IN

RECEIVER A

RECEIVER B

OUT

OUT

Figure 44. Signal Ground Connected in “Star”Configuration

POWER CONSIDERATIONSThe 500 mA drive capability of the AD816 driver enables it todrive a 50 Ω load at 40 V p-p when it is configured as a dif-ferential driver. This implies a power dissipation, PIN, of nearly5 watts. To ensure reliability, the junction temperature of theAD816 should be maintained at less than 175°C. For this rea-son, the AD816 will require some form of heat sinking in mostapplications. The thermal diagram of Figure 45 gives the basic

relationship between junction temperature (TJ) and variouscomponents of θJA.

TJ =TA + PIN θJA Equation 1

θA (JUNCTION TODIE MOUNT)

θB (DIE MOUNTTO CASE)

θA + θB = θ JCCASE

TA

TJ

θ JC θCA

TAθ JA

TJ

PIN

WHERE:PIN = DEVICE POWER DISSIPATIONTA = AMBIENT TEMPERATURETJ = JUNCTION TEMPERATUREθ JC = THERMAL RESISTANCE – JUNCTION TO CASEθ CA = THERMAL RESISTANCE – CASE TO AMBIENT

Figure 45. A Breakdown of Various Package ThermalResistances

Figure 46 gives the relationship between output voltage swinginto various loads and the power dissipated by the AD816 (PIN).This data is given for both sine wave and square wave (worstcase) conditions. It should be noted that these graphs are formostly resistive (phase < ±10°) loads. When the power dissipationrequirements are known, Equation 1 and the graph on Figure 47can be used to choose an appropriate heat sinking configuration.

4

3

P IN

– W

atts

10 20 30 40

2

1

VOUT – Volts p-p

RL = 50V

RL = 100V

RL = 200V

f = 1kHz

SQUARE WAVE

SINE WAVE

VS = 615V

Figure 46. Total Power Dissipation vs Differential DriverOutput VoltageOBSOLETE

AD816

REV. B –13–

Normally, the AD816 will be soldered directly to a copper pad.Figure 47 plots θJA against size of copper pad. This data pertainsto copper pads on both sides of G10 epoxy glass board connectedtogether with a grid of feedthroughs on 5 mm centers.

This data shows that loads of 100 ohms or greater will usuallynot require any more than this. This is a feature of the AD816’s15-lead power SIP package.

An important component of θJA is the thermal resistance of thepackage to heatsink. The data given is for a direct solderedconnection of package to copper pad. The use of heatsinkgrease either with or without an insulating washer will increasethis number. Several options now exist for dry thermal connec-tions. These are available from Bergquist as part # SP600-90.Consult with the manufacturer of these products for details oftheir application.

COPPER HEAT SINK AREA (TOP AND BOTTOM) – mm2

35

30

100 2.5k0.5k

θ JA

– 8C

/W

1k 1.5k 2k

25

20

15

AD816AVR, AY (θJC = 28C/W)

1 2 3COPPER HEAT SINK AREA (TOP AND BOTTOM) – in 2

Figure 47. Power Package Thermal Resistance vs. HeatSink Area

Other Power ConsiderationsThere are additional power considerations applicable to theAD816. First, as with many current feedback amplifiers, there is anincrease in supply current when delivering a large peak-to-peakvoltage to a resistive load at high frequencies. This behavior isaffected by the load present at the amplifier’s output. Figure 12summarizes the full power response capabilities of the AD816driver. These curves apply to the differential driver applications(right-hand side of Figure 52). In Figure 12, maximum continu-ous peak-to-peak output voltage is plotted vs. frequency forvarious resistive loads. Exceeding this value on a continuousbasis can damage the AD816.

The AD816 is equipped with a thermal shutdown circuit. Thiscircuit ensures that the temperature of the AD816 die remainsbelow a safe level. In normal operation, the circuit shuts downthe AD816 at approximately 180°C and allows the circuit toturn back on at approximately 140°C. This built-in hysteresismeans that a sustained thermal overload will cycle betweenpower-on and power-off conditions. The thermal cycling typi-cally occurs at a rate of 1 ms to several seconds, depending onthe power dissipation and the thermal time constants of thepackage and heat sinking. Figures 48 and 49 illustrate the ther-mal shutdown operation after driving OUT1 to the + rail, andOUT2 to the – rail, and then short-circuiting to ground eachoutput of the AD816. The AD816 will not be damaged bymomentary operation in this state, but the overload conditionshould be removed.

Figure 48. OUT2 Shorted to Ground Through a 2 ΩResistor, Square Wave Is OUT1, RF = 1 kΩ, RG = 222 Ω

Figure 49. OUT1 Shorted to Ground Through a 2 ΩResistor, Square Wave Is OUT2, RF = 1 kΩ, RG = 222 ΩOBSOLETE

AD816

REV. B–14–

APPLICATIONSADSL TransceiverThe AD816 is designed for the primary purpose of providing anintegrated solution for the transmit and receive functions of anADSL modem. ADSL or Asymmetrical Digital Subscriber Lineis a means for delivering up to 6 Mbps from a telephone centraloffice (CO) into a home over the conventional telephone twistedpair (local loop) and a few hundred kbps simultaneously in theopposite direction.

The transmit/receive block is commonly referred to as a hybrid,which is an old telephone term, and the function was originallyperformed with passive circuitry in early phone systems. Thehybrid’s function is to deliver maximum transmit power downthe line, while providing the receive circuitry with a maximumreceive signal and a minimized (self) transmit signal. As the linegets longer, this separation becomes much more difficult, be-cause the transmit signal must be larger to reach the other endwith acceptable SNR, while the receive signal is more attenu-ated by the longer line.

The figure of merit for the performance of the hybrid is com-monly called trans-hybrid loss and is a measure of how muchthe transmit signal that appears in the receive circuit has beenattenuated relative to the amplitude of the transmit signal itself.It is measured in dBs and is a function of frequency.

In addition to the passive circuits that have been used over time,active circuit techniques can enhance the hybrid’s performance.Figure 50 shows one of the various hybrid circuits that uses theAD816 in an ADSL application. The high power op amps serveas the transmitter, while the low noise amplifiers serve as thereceiver.

The power amplifiers of the AD816 (D1 and D2) are arrangedin a differential configuration that receives its inputs from thedifferential outputs of a D/A converter. The outputs differen-tially drive the transformer primary with a turns ratio of 1:2.The line on the secondary side of the transformer has an imped-ance of 120 Ω. Thus one quarter of this resistance (30 Ω) isrequired for back termination on the primary side due to theimpedance scaling by the square of the turns ratio. This resis-tance is divided in half (15 Ω) and put on each side of the drivebuffers for symmetry (R101 and R201).

The receive section (R1 and R2) is configured as a pair of differ-ence amplifiers that together produce a differential output thatconsists of the receive signal in addition to the transmit signalattenuated by the trans-hybrid loss.

The circuit is highly symmetrical, so a single-ended explanationcan be easily generalized to understand the differential opera-tion. D1 output terminals (Pin 6 of the AD816) drives the topof the primary of T1 through R101. A voltage divider is formed

+15V

0.1mF 10mF

8

6

715V

4

5

–15V

7

9

715V

11

10

D1

AD816

806V

V+

V– R202196V

R203196V

R2041.18kV

L20112mH

R20115V

R10115V

2

3

1

R106348V

R105162V

R1071kV

R1082.37kV

RCV OUT+

1 2 4

10 9 6

8

7

5

T1XFRMR

C6010.1mF

C6020.1mF

TELEPHONE

TWISTED PAIRD2

0.1mF 10mF

R102196V

R103196V

R1041.18kV

C1018.2mF

L10112mH

R1AD816

13

12

14

R206348V

R205162V

R2071kV

R2082.37kV

RCV OUT–

R2AD816

C2018.2mF

Figure 50. AD816 as an ADSL Transceiver

OBSOLETE

AD816

REV. B –15–

by R101 and all the downstream circuitry comprised of T1, thetransmission line and its termination. For an ideal transformer,transmission line and termination, this will appear to be 15 Ω,and thus the signal appearing at Pins 1 and 2 of T1 will be theoutput of D1 divided by two in the ideal case. This signal isapplied to the input of R1 (Receive 1 of the AD816) (Pin 3) viaR105.

In some ADSL systems (DMT), there is a need to transmithigher crest factor signals. Typically this is done by increasingthe turns ratio of T1 to as much as 4:1. In this case, R101 andR201 would be 3.75 Ω, and the peak current of the AD816(1 A) would be the drive limit of the transmitter.

R1 is configured as a difference amplifier. The negative side(Pin 2) is driven by another signal that is a divided down versionof the output of D1. This circuit is formed by R102 as one sideof the voltage divider along with R103, C101, R104 and L101as the other half of the divider. If the frequency dependentimpedance part of this circuit matches the transformer, trans-mission line and termination impedance, then the signalsapplied to both sides of the difference-amp-configured R1 willbe the same, and the transmit signal will be totally subtractedout by the circuit.

In a real-world situation, it is not practical (or even possible) tosubtract out all of the transmit signal (100% trans-hybrid loss),but only provide a first order cancellation which goes a long waytoward reducing the dynamic range of the RCVOUT signal.The overall performance of this circuit depends on the ability tobuild a lumped element network that matches the impedance ofthe transmission line over the frequency range required forADSL (≈ 20 kHz to 1.1 MHz).

The circuits formed by D2 and R2 of the AD816 are totallysymmetric with those formed by D1 and R1 and work in thesame fashion. All the components in the D1, R1 circuits that arenumbered with 100 range numbers are numbered with 200range numbers in the D2, R2 circuits.

The receive signal from the telephone line creates a differentialsignal across the primary of T1. There is, however, a two to onereduction in amplitude due to turns ratio of T1. This differen-tial signal is applied to the + inputs (Pins 3 and 12) of R1 andR2. The receive amplifiers buffer this signal and present a differ-ential output at Pins 1 and 14. There is no significant receivesignal applied to the negative inputs of R1 and R2 due to theattenuating effects of R101 and R201 and the low outputimpedances of D1 and D2.

Thus, the overall circuit provides first order cancellation of thetransmit signal and differential buffering of the receive signal.

Dual Composite AmplifierA composite amplifier uses two different op amps together in acircuit to yield an overall performance that has some of theadvantages of each op amp. In the case of the AD816, two com-posite amplifiers can be constructed that offer the low noise ofthe receiver amps in addition to the high current output of thedriver amps.

The circuit in Figure 51 shows an example of such a circuit. Ituses receiver amp R1 for the low noise first stage and driver D1for the high output current second stage. Both local and overallfeedback are used to get the desired response.

6

4

5VOUT

2

3R1

D1VIN

Figure 51. AD816 Composite Amplifier

Creating Differential SignalsIf only a single-ended signal is available to drive the AD816 anda differential output signal is desired, a circuit can be used toperform the single-ended to differential conversion.

The circuit shown in Figure 52 performs this function. It usesthe AD816 with the gain of one receiver set at +1 and the gainof the other at –1. The 1 kΩ resistor across the input terminalsof the follower makes the noise gain (NG = 2) equal to theinverter’s. The two receiver outputs then differentially drive theinputs to the AD816 driver with no common-mode signal to firstorder.

6

4

5

8

+15V

10

7

–15V

RF499V

RL

9

11

0.1mF 10mF

RG100V

RF499V

0.1mF 10mF

1

8

+15V

0.1mF

2

1kV

4

–15V

1kV

7

0.1mF

6

5

1kV

3

AD816

100V

100V

1kV

AD816

AD816

AD816

RECEIVER #1

RECEIVER #2

DRIVER #1

DRIVER #2

Figure 52. Differential Driver with Single-EndedDifferential Converter

OBSOLETE

AD816

REV. B–16–

C21

91b

–0–1

2/99

(re

v. B

)P

RIN

TE

D IN

U.S

.A.

15-Lead Surface Mount DDPAK(VR-15)

10.080 (2.03)0.065 (1.65)2 PLACES

0.69

4 (1

7.63

)0.

684

(17.

37)

PIN 1

0.516(13.106)

0.110(2.79)BSC

0.042(1.066)TYP

0.137(3.479)TYP

0.394(10.007)

0.152 (3.86)0.148 (3.76)

0.600 (15.24)BSC

0.079 (2.006)DIA2 PLACES

15

0.024 (0.61)0.014 (0.36)

0.063 (1.60)0.057 (1.45)

8°0°

0.08

8 (2

.24)

0.06

8 (1

.72)

0.42

6 (1

0.82

)0.

416

(10.

57)

SEATINGPLANE

0.031 (0.79)0.024 (0.60)

0.100 (2.54)BSC

0.798 (20.27)0.778 (19.76)

0.182 (4.62)0.172 (4.37)

0.146 (3.70)0.138 (3.50)

15-Lead Through-Hole SIP with Staggered Leads and 908 Lead Form

(Y-15)

0.063 (1.60)0.057 (1.45)

0.671±0.006

(17.043±0.152)SHORT

LEAD

0.024 (0.61)0.014 (0.36)

0.666±0.006(16.916±0.152)LONGLEAD 0.

691

±0.0

10(1

7.55

1 ±0

.254

)0.

766

±0.0

10(1

9.45

6 ±0

.254

)0.

791

±0.0

10(2

0.09

1 ±0

.254

)

0.69

4 (1

7.63

)0.

684

(17.

37)

PIN 1

0.110(2.79)BSC 0.394

(10.007)

0.152 (3.86)0.148 (3.76)

0.080 (2.03)0.065 (1.65)2 PLACES

0.51

6 (1

3.10

6)

0.042(1.066)TYP

0.137(3.479)TYP

0.079(2.006) DIA2 PLACES

0.42

6 (1

0.82

)0.

416

(10.

57)

1 15

0.700 (17.78) BSC

SEATINGPLANE

0.031 (0.79)0.024 (0.60)

0.050(1.27)BSC

0.798 (20.27)0.778 (19.76)

0.182 (4.62)0.172 (4.37)

0.209 ±0.010(5.308 ±0.254)

OUTLINE DIMENSIONSDimensions shown in inches and (mm).

15-Lead Through-Hole SIP with Staggered Leadsand Straight Lead Form

(YS-15)

0.080 (2.03)0.065 (1.65)2 PLACES

0.69

4 (1

7.63

)0.

684

(17.

37)

PIN 1

0.110(2.79)BSC

0.042(1.07)TYP

0.137(3.48)TYP

0.394(10.007)

0.152 (3.86)0.148 (3.76)

0.700 (17.78) BSC0.079(2.007) DIA2 PLACES

0.42

6 (1

0.82

)0.

416

(10.

57)

0.51

6 (1

3.10

6)

1 15

0.063 (1.60)0.057 (1.45)

0.627±0.010

(15.926±0.254)SHORT

LEAD

0.601±0.010(15.265±0.254)LONGLEAD

0.176 (4.47)0.150 (3.81)

0.710 (18.03)0.690 (17.53)

0.200(5.08)BSC

0.169(4.29)BSC

0.024 (0.61)0.014 (0.36)

0.031 (0.79)0.024 (0.60)

0.050 (1.27)BSC

0.798 (20.27)0.778 (19.76)

0.182 (4.62)0.172 (4.37)

SEATINGPLANE

OBSOLETE