acemi technology corp. - alfacomponent.com · table of contents 1. cover & contents ... dot...

Confidential Document

FG020400DNSWAG01 REV:5 Page: 1 /23

ACEMI TECHNOLOGY Corp.

TFT Module Specification

ITEM NO.: FG020400DNSWAG01

Table of Contents

1. COVER & CONTENTS !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 1

2. RECORD OF REVISION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 2

3. APPLICATION!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 3

4. FEATURES!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 3

5. GENERAL SPECIFICATIONS !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 3

6. ABSOLUTE MAXIMUM RATINGS !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 3

7. ELECTRICAL CHARACTERISTICS !!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 4

8. OPTICAL CHARACTERISTIC !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 11

9. INPUT / OUTPUT TERMINALS!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 14

10. BLOCK DIAGRAM !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 17

11. QUALITY ASSURANCE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 19

12. LOT NUMBERING SYSTEM !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 20

13. LCM NUMBERING SYSTEM !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 20

14. PRECAUTIONS IN USE LCM !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 21

15. OUTLINE DRAWING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 22

16. PACKAGE INFORMATION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 23

Customer Companies R&D Dept. Q.C. Dept. Eng. Dept. Prod. Dept.

ALEX ERIC PAUL HELEN

Approved by Version: Issued Date: Sheet Code: Total Pages:

5

2005/03/17 23

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2. RECORD OF REVISION

Rev Date Item Page Comment

1 24/NOV/04 1. Initial preliminary

2 28/DEC/04 old P/N# FG020400DNSWA-01

3 7/JAN/05 3,15 3,22 1. Change: OUTLINE DRAWING from

FG020400S-G1 REV:1 to REV 2 2. Reduce Active Area dimension from 2.39 to 2.36.

4 16/FEB/05 7.7 11 Add Power ON/OFF timing.

5 17/MAR/05 8,15 12,22

New model numbering system is updated from old P/N#FG020400DNSWA-G1 1.Add Definition of Brightness Uniformity (Buni): 2.Change: OUTLINE DRAWING from

FG020400S-0G1 REV:2 to FG020400S-01REV 5 3. Change: FPC length from 100±5mm to 50±3mm.

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3. Application This technical specification applies to 2.4 color TFT-LCD panel. panel is designed for camcorder, digital camera printer and other electronic products which require high quality flat colorl displays. 4. Features " Support 8-bit data (RGB) or CCIR656/CCIR601 8 bit format. " Support the SPI commands setting, the operation parameters setting internally. " Support Low power control mode (Standby mode). " PWM function is embedded. " Right and left shift capability. " Up and down scan capability. " Our components and processes are compliant to RoHS standard 5. GENERAL Specifications Parameter Specifications Unit Screen Size 2.4 (diagonal) inch Surface Treatment Anti-Glare Display Format 480 x 234 dots Active Area 48 (W) x 35.685 (H) mm Dot Pitch 0.1(W) x 0.1525 (H) mm Pixel Configuration R.G.B Delta Outline Dimension 58.14 (W) x 47.4 (H) x 3.2 Max.(T) mm Weight TBD g View Angle direction 6 oclock

Operation 0~60 °C Temperature Range Storage -30~80 °C

6. Absolute Maximum Ratings: (vss=vssa=0V)

Parameter Symbol MIN. MAX. Unit Power supply voltage (1) VDD -0.3 +7.0 V Power supply voltage (2) VDDA -0.3 +7.0 V Power supply voltage (3) VGH -0.3 +32.0 V Power supply voltage (4) VEE -22.0 +0.3 V Power supply voltage (5) VGH-VEE -0.3 +45.0 V Logic Output Voltage VOUT1 -0.3 +7.0 V Input voltage Vin -0.3 VDD+0.3 V Note:

All of the voltages listed above are with respective to VSS=0V. Device is subject to be damaged permanently if stresses beyond those absolute maximum ratings listed above.

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7. Electrical Characteristics 7-1 DC Electrical Characteristics

(VSS=VSSA=0V, TA=25) Parameter Symbol MIN. TYP MAX. Unit Remark

Power supply voltage (1) VDD 3.0 3.3 3.6 V Power supply voltage (2) VDDA 5 V Power supply voltage (3) VGH T.B.D V Power supply voltage (4) VEE T.B.D V Low level input voltage VIL 0 - 0.3 VDD V CLKIN, HSD, VSD, DIN[7:0],

SPCK, SPDA, SPENA

High level input voltage VIH 0.7 VDD - VDD V CLKIN, HSD, VSD, DIN[7:0], SPCK, SPDA, SPENA

Analog operating current IVDDA - - TBD mA VGH Supply current IVGH - - TBD uA VEE Supply current IVEE - - TBD uA Digital operating current IVDD - - TBD mA

7-2 Backlight Driving for Power Consumption

Pin No Symbol Description Remark 12 VLED Input terminal (Hi voltage side) 13 GLED Input terminal (Low voltage side)

Parameter Symbol Min. Typ. Max. Unit Remark LED voltage VL -- TBD -- V IL=20 mA Ta= 25 °C LED current IL -- 20 -- mA Ta= 25 °C

VLED GLED

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7-3 AC Characteristics

7.3.1 Input signal characteristics 7.3.2 Digital RGB interface

Parameter Symbol MIN. TYP MAX. Unit Remark CLK period TOSC 94 104 114 ns Data setup time TSU 12 - - ns Data hold time THD 12 - - ns HSD period TH 61.5 63.5 65.5 us HSD pulse width THS 4 4.7 5.4 us HSD rising time TCr - - 700 ns HSD falling time TCf - - 300 ns VSD pulse width TVS 1 3 5 TH VSD rising time TVr - - 700 ns VSD falling time TVf - - 1.5 us HSD falling to VSD falling time for odd field THVO1 0.3 - - us

VSD falling to HSD rising time for odd field THVO2 1 - - us

HSD rising to VSD falling time for even field THVE 1 - - us

NTSC 15 VSD-DEN time PAL TVSE - 24 - TH

HSD-DEN time THF 75 - 120 TOSC DEN pulse width TEP - 480 - TOSC DEN-STH time TDES - 3 - TOSC

NTSC - 262.5 - TH VSD period PAL - 312.5 - TH

PS: when SYNC mode is used, 1st data start from 106th clock after HSD falling 7.3.3 CCIR601 Interface Parameter Symbol Min. Typ. Max. Unit. CLK period TOSC - 37 - ns Data setup time TSU 12 - - ns Data hold time THD 12 - - ns

NTSC THL - 276 - TOSC HSD data blanking pulse width

PAL THL - 288 - TOSC

7.3.4 CCIR656 Interface Parameter Symbol Min. Typ. Max. Unit. CLK period TOSC - 37 - ns Data setup time TSU 12 - - ns Data hold time THD 12 - - ns

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7.4 SPI timing characteristics Parameter Symbol Min. Typ. Max. Unit. SPCK period TCK 60 - - ns SPCK high width TCKH 30 - - ns SPCK low width TCKL 30 - - ns Data setup time TSU1 12 - - ns Data hold time THD1 12 - - ns SPENA to SPCK setup time TCS 20 - - ns SPENA to SPDA hold time TCE 20 - - ns SPENA high pulse width TCD 50 - - ns SPDA output latency TCR - 1/2 - TCK

# SPI “read” timing

1 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0SPDA

SPCK

SPENA

TCR

TCSTCE

TCD

TCKH TCKL

TCK

TSU1 THD1

# SPI “write” timing

0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0SPDA

SPCK

SPENA

TCSTCE

TCD

TCKH TCKL

TCK

TSU1 THD1

7-5 Hardware reset timing Parameter Symbol Min. Typ. Max. Unit. RESETB low pulse width TRSB 200 - - ns

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7.6 Waveform 7.6.1 Timing Controller Timing Chart

7.6.2 Clock and Data waveform

# CCIR601 ( HSDPOL = “H” )

CLKIN

Y0 Cr0 Cb2Y1Cb0DATA

TOSC

TSU THD

HSD

Blanking data

# CCIR656

CLKIN

Y Cr CbY Y CrCbDATA

TOSC

TSU THD

# Digital RGB

CLKIN

TSU THD

GR G B RDATA

TOSC

DEN

Blanking data

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7.6.3 Digital RGB timing waveform 7.6.3.1 HSD and VSD timing for digital RGB mode

# Odd field

HSD

VSDTHVO1

THVO2

# Even field

HSD

VSD

THVE

7.6.3.2 HSD and horizontal control timing waveform for digital RGB mode

CKV

THS

1 OEH

2

OEV

3

HSD

OEH

STH1(2)

CKV

OEV

POL

~ ~~ ~

~ ~~ ~

~ ~~ ~

T

T

T

T

T

T

(internal)

(internal)

(internal)

(internal)

(internal)

DEN

~ ~

TDES

THE

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7.6.3.3 HSD and vertical shift clock timing waveform

HSD

STV1(2)

CKV

stv

Tsuv

(in terna l)

(in ternal)

T

7.6.3.4 HSD and vertical control timing waveform

HSD

VSD

OEH

STV1(2)

POL(Even field)

POL(Odd field)

TVS

TVS1

~ ~~ ~

(internal)

(internal)

(internal)

(internal)

DENTEP

TVSE

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7.6.3.5 CCIR601 timing waveform # NTSC mode, even field ( HSDPOL = “H”, VSDPOL = “H” )

Line 262 Line 263 Line 264 Line 265 Line 266 Line 267 Line 268 Line 269 Line 286

BLANKINGDATA

Line 285

DATA

LINE DATA

HSD

VSD

THL

# NTSC mode, odd field ( HSDPOL = “H”, VSDPOL = “H” )

LINE DATA

VSD

HSD

DATA


BLANKINGDATA

Line 22

THL

# PAL mode, even field ( HSDPOL = “H”, VSDPOL = “H” )


BLANKINGDATA

Line 335

DATA

LINE DATA

HSD

VSD

THL

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# PAL mode, odd field ( HSDPOL = “H”, VSDPOL = “H” )

LINE DATA

VSD

HSD

DATA


BLANKINGDATA

Line 22

THL

7.7 Power ON/OFF sequence To prevent the device from damage due to latch-up, the power ON/OFF sequence shown below

must be followed.

Power ON: VDD, VDDA→ VEE→ input signals→ VGH

Power OFF: VGH→ input signals → VEE → VDD, VDDA

8. Optical Characteristics 8-1. Specification:

Ta = 25°C

Parameter Symbol Condition MIN. TYP. MAX. Unit Remarks Horizontal φ ±45 ±50 deg

θ (to 12 oclock) 10 15 deg

Viewing Angle

Vertical θ (to 6 oclock)

CR≥10

30 35 deg

Note 8-2

Contrast Ratio CR 100 120 Note 8-1 Response time Rise Tr 15 -- ms Fall Tf

θ=0° φ=0° 20 -- ms Note 8-4

Uniformity U 70 % Note 8-5 Brightness 200 250 -- cd/m2 Note 8-2

x 0.300 Chromaticity White y θ=0° 0.330

Note 8-2

Luminance when LCD is White Note 8-1：CR ＝ Luminance when LCD is Black

Contrast Ratio is measured in optimum common electrode voltage. The test configurations of contrast ratio see section 8-2 .

Input signal VEE

VDD,VDDA

VGH

VSS

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Note 8-2 :1.Topcon BM-7(fast) luminance meter 1.0° field of view is used in the testing (after 2 minutes operation ).

2. LED current =20mA.

Note 8-3 : The definitions of viewing angles diagrams:

Note 8-4: The definition of response time:

1 0 0 % 9 0 %

1 0 %

0 %

W h i t e W h i t e

Brightness

B l a c k

T r T f

Note 8-5: Definition of Brightness Uniformity (Buni):

Minimum luminance of 9 points Buni ＝ Maximum luminance of 9points

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8-2. Testing configuration $ LCD Display $ R, G, B Waveform of Pattern A at Testing Point $ R,G, B Waveform of Pattern B at Testing Point

500mm

BM-7(fast)

LCD

Backlight

R,G,B signal Pattern

generator

input

Pattern A Pattern B

Testing Point Testing Point

16ms 16ms

VW

VW=1.1V +/- 0.2V

16ms 16ms

Vb=5.2V +/-0.2V

Caution: 1. Environmental illumination≦1 lux 2. Before test CR, Vcom voltage must

be adjusted carefully to get the best CR.

RGB waveform VCOM

VCOM RGB waveform

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9. Input / Output Terminals 9-1 PIN Connections Pin No Symbol I/O Description Remark

1 VFB I PWM feedback reference voltage. Default is 1.2 V

2 DRV O PWM drive output signal

3 VCOML IO VCOM reference low level voltage. Connect 1uF Cap to VSSA.

4 VCOMH IO VCOM reference high level voltage. Connect 1uF cap to VSSA.

5 VCOM I VCOM input signal if VCOMOUT function is disable.

6 VGH VI Gate output high voltage.

7 VGL VI Gate output low voltage.

8 VEE VI Negative power supply. If Cs-on-common is implemented, short to VGL.

9 VDDA VI Analog power voltage. This power connects to Source Driver.

10 VSSA VI Analog GND. This power connects to Source Driver.

11 VSS VI Digital GND.

12 VLED VI Power supply of LED back light, ( 20 mA constant current, 14 V or higher)

13 GLED VI Ground of LED back light

14 N.C -- No connection.

15 RESETB I Active low global reset signal input. Normally pull high.

16 SPENA I Serial port Data Enable Signal.

17 SPCK Serial port Clock.

18 SPDA I/O Serial port Data input/output.

19 HSD I Horizontal sync input with negative polarity.

20 VSD I Vertical sync input with negative polarity.

21 DB7 I Digital image data input bit 7.








29 CLKIN I Input data sampling clock at rising edge.

30 VDD VI Digital power voltage.

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9-2 Pixel Arrangement and input connector pin NO.

HX8211 Gate wiring G1..N.C G2..N.C 1 2 3 4 5 6 478 479 480 G3..N.C 1 B R G B R G B R G G4 2 R G B R G B R G B 3 B R G B R G B R G 4 R G B R G B R G B 5 B R G B R G B R G 232 R G B R G B R G B 233 B R G B R G B R G 234 R G B R G B R G B G237 G238..N.C G239..N.C G240..N.C

30 1

Note: HX8211 Control register (R01H),CF1=1 & CF2=1

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Register Description:

Please refer the specification of HX8211A for detail.

Code Reg No. Register Name

D7 D6 D5 D4 D3 D2 D1 D0

Set Initialization Description

00H Function Control COM RSTB0 STBYB XAO VSET NPC UID RIL 7DH RIL: Source shift direction. UID: Gate scan direction. NPC: Video signal selector. VSET: Internal / External gamma correction selector. XAO: Gate driver output to normal / High selector. STBYB: Standby mode, Low enable. RSTB0: Reset all registers, Low enable. CPM:VCOM circuit enable, low active.

01H Data Control VSDPOL HSDPOL SEL1 SEL0 RESERVE DITH CF2 CF1 C3H CF2/1: Color filter mode selector. DITH: Dithering ON/OFF setting. SEL1/0: interface setting. HSDPOL: define the signal polarity of HSD in CCIR601 input mode.

02H Source Driver stare pixel control RESERVE RESERVE RESERVE STHST4 STHST3 STHST2 STHST1 STHST0 00H Source driver start pulse position control register.

03H Gate Driver stare pixel control RESERVE RESERVE RESERVE RESERVE STVST3 STVST2 STVST1 STVST0 00H Gate driver start pulse position control register.

04H VCOM Voltage High Level control RESERVE RESERVE RESERVE VVOMH4 VVOMH3 VVOMH2 VVOMH1 VVOMH0 05H VCOM voltage high level control register.

05H VCOM Voltage Swing control RESERVE RESERVE VCOMA4 VCOMA3 VCOMA2 VCOMA1 VCOMA0 VCOMAG 11H VCOM voltage swing level control register.

06H Gamma Reference Voltage Selection I GAM13 GAM12 GAM11 GAM10 GAM03 GAM02 GAM01 GAM00 26H Gamma reference voltage selector I.

07H Gamma Reference Voltage Selection II GAM33 GAM32 GAM31 GAM30 GAM23 GAM22 GAM21 GAM20 77H Gamma reference voltage selector II.

08H Gamma Reference Voltage Selection III RESERVE RESERVE RESERVE RESERVE GAM43 GAM42 GAM41 GAM40 0AH Gamma reference voltage selector III.

09H Block control RESERVE RESERVE RESERVE RESERVE RESERVE RESERVE PINV PWM 00H Block control register.

0AH Source Driver Start Dot control RESERVE RESERVE RESERVE STHD4 STHD3 STHD2 STHD1 STHD0 00H Source driver start pulse dot position control register.

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Confidential

Document


10. Block Diagram

LCD Panel 480 x 234

G5,7,9,..237 G4,6,8..236

S1 S480

HX8211

VDD,VDDA VSSA,VEE,

VCOM,VGH VGL,VCOML, VCOMH

DRV VFB

DB0~DB7 CLKIN,HSD,VSD

SPDA,SPENA, SPCK RSETB

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10.1 Application Circuit

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11. QUALITY ASSURANCE Test Condition

11.1.1 Temperature and Humidity(Ambient Temperature)

Temperature : 20 ± 5°C Humidity : 65 ± 5%

11.1.2 Operation

Unless specified otherwise, test will be conducted under function state.

11.1.3 Container Unless specified otherwise, vibration test will be conducted to the product itself without putting it in a container.

11.1.4 Test Frequency

In case of related to deterioration such as shock test. It will be conducted only once.

11.1.5 Test Method

No. Reliability Test Item & Level Test Level

1 High Temperature Storage Test T=80°C,240hrs

2 Low Temperature Storage Test T=-30°C,240hrs

3 High Temperature Operation Test T=60°C,240hrs

4 Low Temperature Operation Test T=0°C,240hrs

5 High Temperature and High Humidity Operation Test

T=60°C,95% RH,240hrs

6 Thermal Cycling Test (No operation)

-20°C → +25°C → +70°C,50 Cycles 30 min 5min 50 min

7 Vibration Test (No operation)

Frequency:10 ~ 55 Hz

Amplitude:1.0 mm

Sweep Time:11min

Test Period:6 Cycles for each Direction of X,Y,Z

8 Shock Test (No operation)

100G, 6ms Direction：± X,± Y,± Z

Cycle：3 times

9 Electrostatic Discharge Test (No operation)

150pF,330Ω

Air:± 15KV;Contact: ± 8KV

10 times/point;4 points/panel face

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12. LOT NUMBERING SYSTEM

9 7 4 2 Production week number Production year

13. LCM NUMBERING SYSTEM

FG 020400 D N S W A G 01

VERSION :01 RoHS View direction & Temp. Range

A– Bottom view 6H & Normal temp.

B– Bottom view 6H & Wide temp.

CTop View & Normal temp

DTop View & Wide temp.

Backlight Color

W White Y Yellow Green

G - green

Backlight

S edge light LED B/L

CCCFL B/L LCD Polarize type

NNegative R Reflective Mtransmissive F transflective

LCD type A TFT analog

D TFT digital

Series code 020400, 2.4 inch ,0 LCD type,0 PCB type Model type

FG–Standard TFT Module

FXCustom TFT Module

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14. PRECAUTION FOR USING LCM

1. LIQUID CRYSTAL DISPLAY (LCD) LCD is made up of glass, organic sealant, organic fluid, and polymer based polarizers. The following precautions should be taken when handing, (1). Keep the temperature within range of use and storage. Excessive temperature and humidity could cause polarization degredation, polarizer peel off or bubble. (2). Do not contact the exposed polarizers with anything harder than an HB pencil lead. To clean dust off the display surface, wipe gently with cotton, chamois or other soft material soaked in petroleum benzin. (3). Wipe off saliva or water drops immediately. Contact with water over a long period of time may cause polarizer deformation or color fading, while an active LCD with water condensation on its surface will cause corrosion of ITO electrodes. (4). Glass can be easily chipped or cracked from rough handling, especially at corners and edges. (5). Do not drive LCD with DC voltage. 2. Liquid Crystal Display Modules 2.1 Mechanical Considerations LCM are assembled and adjusted with a high degree of precision. Avoid excessive shocks and do not make any alterations or modifications. The following should be noted. (1). Do not tamper in any way with the tabs on the metal frame. (2). Do not modify the PCB by drilling extra holes, changing its outline, moving its components or modifying its pattern. (3). Do not touch the elastomer connector, especially insert an backlight panel (for example, EL). (4). When mounting a LCM make sure that the PCB is not under any stress such as bending or twisting . Elastomer contacts are very delicate and missing pixels could result from slight dislocation of any of the elements. (5). Avoid pressing on the metal bezel, otherwise the elastomer connector could be deformed and lose contact, resulting in missing pixels. 2.2. Static Electricity LCM contains CMOS LSI’s and the same precaution for such devices should apply, namely (1). The operator should be grounded whenever he/she comes into contact with the module. Never touch any of the conductive parts such as the LSI pads, the copper leads on the PCB and the interface terminals with any parts of the human body. (2). The modules should be kept in antistatic bags or other containers resistant to static for storage. (3). Only properly grounded soldering irons should be used. (4). If an electric screwdriver is used, it should be well grounded and shielded from commutator sparks.

(5) The normal static prevention measures should be observed for work clothes and working benches; for the latter conductive (rubber) mat is recommended. (6). Since dry air is inductive to statics, a relative humidity of 50-60% is recommended. 2.3 Soldering (1). Solder only to the I/O terminals. (2). Use only soldering irons with proper grounding and no leakage. (3). Soldering temperature : 280°C ± 10°C (4). Soldering time: 3 to 4 sec. (5). Use eutectic solder with resin flux fill. (6). If flux is used, the LCD surface should be covered to avoid flux spatters. Flux residue should be removed after wards. 2.4 Operation (1). The viewing angle can be adjusted by varying the LCD driving voltage V0. (2). Driving voltage should be kept within specified range; excess voltage shortens display life. (3). Response time increases with decrease in temperature. (4). Display may turn black or dark blue at temperatures above its operational range; this is (however not pressing on the viewing area) may cause the segments to appear “fractured”. (5). Mechanical disturbance during operation (such as pressing on the viewing area) may cause the segments to appear “fractured”. 2.5 Storage If any fluid leaks out of a damaged glass cell, wash off any human part that comes into contact with soap and water. Never swallow the fluid. The toxicity is extremely low but caution should be exercised at all the time. 2.6 Limited Warranty Unless otherwise agreed between DATA IMAGE and customer, DATA IMAGE will replace or repair any of its LCD and LCM which is found to be defective electrically and visually when inspected in accordance with DATA IMAGE acceptance standards, for a period on one year from date of shipment. Confirmation of such date shall be based on freight documents. The warranty liability of DATA IMAGE is limited to repair and/or replacement on the terms set forth above. DATA IMAGE will not responsible for any subsequent or consequential events.

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15. OUTLINE DRAWING

3. Connector: Molex 54132-3092 or equivalent70%

200 cd/m2 (Min)1. Brightness :

2. Uniformity :

Note:

LCM OUTLINE DIMENSION

250 cd/m2 (Typ)

FG020400S-01

12/28/04'

5

Detail AScale 2/1

4. for RoHS

480x234 Dots2.4"

5. Tolerance is ±0.3 unless otherwise noted.

Change V.A dimension from 51.2x37.8mm to 50.9x37.2mm2 02/21/05'Modify Note:4. from "for RoHs" to "for RoHS"2 02/21/05'

2

2

22

Delete "PRELIMINARY"2 02/21/05'

2

Follow module code change, DWG. NO. from FG020400S-G1 rev.3 change to FG020400S-01 rev.43 02/25/05'

3

Change FPC length from 100±5mm to 50±3mm4 03/16/05'

4

APPROVEDAUTH

REVISIONS

DESCRIPTION DATEAPPROVE:

DRAWN:

CHECK:

DATE:

SCALE

TITLE:

DWG. NO.

SHEET OF1 1

REV.

1 / 1

DATAIMAGE

UNITSM M

A B C D E F

1

2

3

4

5

6

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16.PACKAGE INFORMATION

Carton

Antistatic bag

Form Drier

LCM

Antistatic form

Antistatic tray

Form

Drier

Cover tray

(Antistatic tray)

where it FPC

cable is put under the other module.)

( Put the 2 modules opposite side for each other,

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